EP3684953A1

EP3684953A1 - Measurement of double layer capacitance in a nanopore sequencing cell

Info

Publication number: EP3684953A1
Application number: EP18778427.7A
Authority: EP
Inventors: Jason KOMADINA; Pirooz Parvarandeh
Original assignee: F Hoffmann La Roche AG; Roche Diagnostics GmbH
Current assignee: F Hoffmann La Roche AG; Roche Diagnostics GmbH
Priority date: 2017-09-22
Filing date: 2018-09-21
Publication date: 2020-07-29
Also published as: JP7005751B2; JP2020535398A; WO2019057890A1; CN111212919A; CN111212919B

Abstract

Techniques relate to measuring the double-layer capacitance of a sequencing cell. In certain embodiments, the double-layer capacitance is measured before the formation of a membrane over a well in the sequencing cell. The double - layer capacitor is pre-charged to an initial voltage level. A capacitor with a known capacitance value is used to repeatedly charge or discharge the double-layer capacitor. The rate that the double-layer capacitor is charged or discharged is used to determine the double-layer capacitance. In some embodiments, the double-layer capacitance is measured after the formation of the bilayer and a nanopore. The double-layer capacitor is pre-charged to an initial voltage level. A voltage level different from the initial voltage level is then applied to the sequencing cell. The timing associated with the decay of the voltage level on the double-layer capacitor is used to determine the double-layer capacitance.

Description

MEASUREMENT OF DOUBLE LAYER CAPACITANCE IN A NANOPORE SEQUENCING CELL

BACKGROUND

[0001] Nanopore membrane devices having pore sizes on the order of one nanometer in internal diameter have shown promise in rapid nucleotide sequencing. When a voltage signal is applied across a nanopore immersed in a conducting fluid, the electric field can move ions in the conducting fluid through the nanopore. The movement of ions in the conducting fluid through the nanopore can cause a small ion current. The voltage applied can also move the molecule (or molecular proxies of the molecule to be sequenced) to be sequenced into, through, or out of the nanopore. The level of the ion current (or a corresponding voltage) depends on the sizes and chemical structures of the nanopore and the particular molecule that has been moved into the nanopore.

[0002] As an alternative to a DNA molecule (or other nucleic acid molecule to be sequenced) moving through the nanopore, a molecule (e.g., a nucleotide being added to a DNA strand) can include a particular tag of a particular size and/or structure that acts as a proxy. The ion current or a voltage in a circuit including the nanopore (e.g., at an integrating capacitor) can be measured as a way of measuring the resistance of the nanopore corresponding to the molecule, thereby allowing the detection of the particular molecule in the nanopore, and the particular nucleotide at a particular position of a nucleic acid.

[0003] A nanopore-based sequencing chip can incorporate a large number of sensor cells configured as an array for parallel DNA sequencing. During the fabrication and/or usage of the nanopore-based sequencing chip, various parameters may need to be measured at different stages of the manufacturing and/or sequencing process for purposes such as quality assurance, uniformity check, baseline calibration, data normalization, and/or base calling. BRIEF SUMMARY

[0004] Techniques described herein relate to nanopore-based nucleic acid sequencing. A double-layer capacitor Cdbi with a capacitance value Cdbi may exist at an interface between the electrolyte and a working electrode in a nanopore sequencing cell. The capacitance value Cdbi may change over time causing a decay in measurements performed for a constant applied voltage. A higher Cdbimay reduce an intra-cycle decay. Knowing Cdbi on a per cell basis may allow intelligent adjustment to the measured data for accurate base calling. The Cdbi may be measured before and/or after the formation of the bilayer and nanopore in a nanopore cell.

[0005] In certain embodiments, the Cdbi can be measured after adding the electrolyte to the nanopore cell, but before the formation of a membrane (e.g., a bilayer) over a well in the sequencing cell and formation of a nanopore. The double-layer capacitor may be pre-charged to an initial voltage level. A capacitor with a known capacitance value, for example, a capacitor Cint associated with one or more integrating circuits used in measurements (hereinafter referred to as integrating capacitor) and having a known capacitance value Cint, may be used to repeatedly charge or discharge the double-layer capacitor. Voltage levels on the double-layer capacitor may be measured after certain number of charges or discharges. The rate that the double-layer capacitor is charged or discharged can be used to determine the ratio between cdbi and Cint, and thus the absolute value of Cdbi when Cint is known.

[0006] For example, the integrating capacitor may be repeatedly disconnected from the double-layer capacitor, charged to a known voltage level different from the initial voltage level of the double-layer capacitor, and reconnected to the double-layer capacitor. In each of such cycles, the integrating capacitor may increase or decrease the voltage level on the double-layer capacitor by an amount depending on the initial voltage difference between the double-layer capacitor and the integrating capacitance and depending on the ratio between Cdbi and Cint. [0007] In some embodiments, the Cdbi may be measured after the formation of the bilayer and nanopore, at which point, a resistor R_pOTe (e.g., an open channel resistor) with a resistance r_pOTe and/or a capacitor (CBiiayer) associated with the nanopore may have been formed. The double-layer capacitor may be pre-charged to an initial voltage level. A voltage level different from the initial voltage level may then be applied to the bulk electrolyte above the lipid bilayer and nanopore. The voltage difference may cause the voltage level on the double-layer capacitor to charge or discharge (i.e., decay) through the resistor and/or capacitor associated with the nanopore. The voltage level on the double-layer capacitor may be measured at a certain sampling rate or at certain time instants. The time constant (x~r_p0reCdbi) of the decay of the voltage level on the double-layer capacitor can be used to determine the caw when Tpore IS known.

[0008] These and other embodiments of the invention are described in detail below. For example, other embodiments are directed to systems, devices, and computer readable media associated with methods described herein.

[0009] A better understanding of the nature and advantages of embodiments of the present invention may be gained with reference to the following detailed description and the accompanying drawings

BRIEF DESCRIPTION OF THE DRAWINGS

[0010] FIG. 1 is a simplified structue illustrating an embodiment of a nanopore cell in an example nanopore-based sequencing chip. [0011] FIG. 2 illustrates an example nanopore cell in a nanopore sensor chip that can be used to characterize a polynucleotide or a polypeptide.

[0012] FIG. 3 illustrates an embodiment of a nanopore cell performing nucleotide sequencing using a nanopore-based sequencing-by-synthesis (Nano- SBS) technique. [0013] FIG. 4 illustrates a double-layer capacitor formed at an interface between a conductive electrode and an adjacent liquid electrolyte.

[0014] FIG. 5 illustrates a pseudo-capacitance effect that can be formed concurrently with the formation of a double-layer capacitor as shown in FIG. 4, at an interface between a conductive electrode and an adjacent liquid electrolyte [0015] FIG. 6 illustrates an example electric circuit representing an electrical model of a nanopore cell.

[0016] FIG. 7 illustrates example control and measurement signals on a nanopore cell during nucleotide sequencing. [0017] FIG. 8 illustrates an example small signal model for non-faradaic conduction in a nanopore cell.

[0018] FIG. 9 shows example data points captured from a nanopore cell during bright periods and dark periods of AC cycles.

[0019] FIG. 10A illustrates an example configuration of a circuit in a nanopore cell for establishing a baseline during a step response capacitance measurement, according to certain embodiments.

[0020] FIG. 10B illustrates an example configuration of a circuit in a nanopore cell for measuring negative step response during a step response capacitance measurement, according to certain embodiments. [0021] FIG. IOC illustrates an example configuration of a circuit in a nanopore cell for measuring positive step response during a step response capacitance measurement, according to certain embodiments.

[0022] FIG. 11 illustrates example AC step signals for measuring a double-layer capacitance using a step response capacitance measurement technique, according to certain embodiments.

[0023] FIG. 12A illustrates example results for measuring a double-layer capacitor with a lower capacitance using a step response capacitance measurement technique, according to certain embodiments.

[0024] FIG. 12B illustrates example results for measuring a double-layer capacitor with a higher capacitance using a step response capacitance measurement technique, according to certain embodiments. [0025] FIG. 13 illustrates the decay of the voltage signal on a double-layer capacitor during a step response capacitance measurement, according to certain embodiments.

[0026] FIG. 14 illustrates the correlation between double-layer capacitance measured using electrochemical impedance spectroscopy (EIS) and the decay time measured using a step response capacitance measurement technique.

[0027] FIG. 15 illustrates an example step response capacitance measurement technique for measuring the capacitance of a double-layer capacitor with a higher capacitance, according to certain embodiments. [0028] FIG. 16 is a flow chart illustrating an example method of step response capacitance measurement, according to certain embodiments.

[0029] FIG. 17A illustrates an example configuration of a circuit in a nanopore cell during a charge titration capacitance measurement, according to certain embodiments. [0030] FIG. 17B illustrates an example configuration of a circuit in a nanopore cell for charging an integrating capacitor during a charge titration capacitance measurement, according to certain embodiments.

[0031] FIG. 17C illustrates an example configuration of a circuit in a nanopore cell for discharging an integrating capacitor during a charge titration capacitance measurement, according to certain embodiments.

[0032] FIG. 18 illustrates example simulation results of charge titration capacitance measurement for different capacitance ratio between the capacitance of a double-layer capacitor and the capacitance of an integrating capacitor, according to certain embodiments. [0033] FIG. 19 is a flow chart illustrating an example method of charge titration capacitance measurement, according to certain embodiments.

[0034] FIG. 20 is a block diagram of an example computer system usable with systems and methods of the present disclosure, according to certain embodiments. DEFINITIONS

[0035] "Nucleic acid" may refer to deoxyribonucleotides or ribonucleotides and polymers thereof in either single- or double-stranded form. The term may encompass nucleic acids containing known nucleotide analogs or modified backbone residues or linkages, which are synthetic, naturally occurring, and non- naturally occurring, which have similar binding properties as the reference nucleic acid, and which are metabolized in a manner similar to the reference nucleotides. Examples of such analogs may include, without limitation, phosphorothioates, phosphoramidites, methyl phosphonates, chiral-methyl phosphonates, 2-O-methyl ribonucleotides, peptide -nucleic acids (PNAs).The term nucleic acid may be used interchangeably with gene, cDNA, mR A, oligonucleotide, and polynucleotide.

[0036] Unless otherwise indicated, a particular nucleic acid sequence also implicitly encompasses conservatively modified variants thereof (e.g., degenerate codon substitutions) and complementary sequences, as well as the sequence explicitly indicated. Specifically, degenerate codon substitutions may be achieved by generating sequences in which the third position of one or more selected (or all) codons is substituted with mixed-base and/or deoxyinosine residues (Batzer et al., Nucleic Acid Res. 19:5081 (1991); Ohtsuka et al., J. Biol. Chem. 260:2605-2608 (1985); Rossolini et al, Mol. Cell. Probes 8:91-98 (1994)). The term nucleic acid is used interchangeably with gene, cDNA, mRNA, oligonucleotide, and

polynucleotide.

[0037] The term "nucleotide " in addition to referring to the naturally occurring ribonucleotide or deoxyribonucleotide monomers, may be understood to refer to related structural variants thereof, including derivatives and analogs, that are functionally equivalent with respect to the particular context in which the nucleotide is being used {e.g., hybridization to a complementary base), unless the context clearly indicates otherwise.

[0038] The term "template" may refer to a single stranded nucleic acid molecule that is copied into a complementary strand of DNA nucleotides for DNA synthesis. In some cases, a template may refer to the sequence of DNA that is copied during the synthesis of mRNA. [0039] The term "primer" may refer to a short nucleic acid sequence that provides a starting point for DNA synthesis. Enzymes that catalyze the DNA synthesis, such as DNA polymerases, can add new nucleotides to a primer for DNA replication. [0040] "Nanopore" refers to a pore, channel or passage formed or otherwise provided in a membrane. A membrane can be an organic membrane, such as a lipid bilayer, or a synthetic membrane, such as a membrane formed of a polymeric material. The nanopore can be disposed adjacent or in proximity to a sensing circuit or an electrode coupled to a sensing circuit, such as, for example, a complementary metal oxide semiconductor (CMOS) or field effect transistor (FET) circuit. In some examples, a nanopore has a characteristic width or diameter on the order of 0.1 nanometers (nm) to about 1000 nm. Some nanopores are proteins.

[0041] As used herein, the term "bright period" may generally refer to the time period when a tag of a tagged nucleotide is forced into a nanopore by an electric field applied through an AC signal. The term "dark period" may generally refer to the time period when a tag of a tagged nucleotide is pushed out of the nanopore by the electric field applied through the AC signal. An AC cycle may include the bright period and the dark period. In different embodiments, the polarity of the voltage signal applied to a nanopore cell to put the nanopore cell into the bright period (or the dark period) may be different.

[0042] As used herein, the term "signal value" may refer to a value of the sequencing signal output from a sequencing cell. According to certain

embodiments, the sequencing signal may be an electrical signal that is measured and/or output from a point in a circuit of one or more sequencing cells e.g., the signal value may be (or represent) a voltage or a current. The signal value may represent the results of a direct measurement of voltage and/or current and/or may represent an indirect measurement, e.g., the signal value may be a measured duration of time for which it takes a voltage or current to reach a specified value. A signal value may represent any measurable quantity that correlates with the resistivity of a nanopore and from which the resistivity and/or conductance of the nanopore (threaded and/or unthreaded) may be derived. DETAILED DESCRIPTION

[0043] Techniques disclosed herein relate to nanopore-based nucleic acid sequencing. In various embodiments, methods for more accurately characterizing components (e.g., a double-layer capacitor) of an individual nanopore cell (also referred to as a sequencing cell) or a group of nanopore cells are provided. The components may be characterized at different stages of the sequencing process for purposes such as quality assurance, uniformity check, baseline calibration, data normalization, and/or base calling.

[0044] In nanopore-based sequencing-by-synthesis (Nano-SBS), the interface between a working electrode (e.g., Pt or TiN) and a liquid electrolyte in a nanopore cell may behave like a capacitor, which may be referred to as a double-layer capacitor (Cdbi). Characterizing the double-layer capacitors of the nanopore cells may inform the quality of the manufactured nanopore cells, such as the uniformity of the cells or defects in the cells. The capacitance Cdbi of double-layer capacitor Cdbi may affect an intra-cycle voltage decay of a voltage applied to the cell and other characteristics of the measurement signals, as well as normalization of measured signal values and thus the accuracy of the base calling. For a very large Cdbi, the intra-cycle decay of the measured data may be negligible. For smaller values of Cdbi, the intra-cycle decay may be more significant and may complicate the normalization of the measured data. It is thus desirable to know the value of Cdbi on a per cell basis such that intelligent adjustments to the measured data may be made. For example, with the knowledge of the capacitance value Cdbi of the double- layer capacitor for individual nanopore cells, data normalization can be performed for individual cells. [0045] Some existing techniques may be used to measure the double-layer capacitance. However, some of these techniques, such as the Electrochemical Impedance Spectroscopy (EIS) technique, may not be able to measure the double- layer capacitances of individual cells. Some techniques may require external instruments for measuring the double-layer capacitance. Some techniques may not be able to measure the double-layer capacitance at an early stage of the sequencing process, such as before the formation of a membrane over a well of a sequencing cell and a nanopore formed in the membrane. Some available techniques may need a long time for the measurement or may not be as accurate as desired for accurate sequencing.

[0046] Techniques disclosed herein provide methods for characterizing the double-layer capacitor at different stages of the sequencing process. The double- layer capacitor may be formed when the working electrode is in contact with liquid electrolyte, where the interface between the working electrode and the liquid electrolyte exhibits the capacitive behavior. Thus, the double-layer capacitor may be measured either before or after the formation of the bilayer and the nanopore in the nanopore cell. The disclosed methods may be used to more efficiently and more accurately measure the double-layer capacitances for individual cells or a group of cells at the beginning of a sequencing process (e.g., prior to the introduction of a bilayer or a pore).

I. NANOPORE SEQUENCING CELL [0047] A nanopore cells in nanopore sensor chip may be implemented in many different ways. For example, in some embodiments, tags of different sizes and/or chemical structures may be attached to different nucleotides in a nucleic acid molecule to be sequenced. In some embodiments, a complementary strand to a template of the nucleic acid molecule to be sequenced may be synthesized by hybridizing differently polymer-tagged nucleotides with the template. In some implementations, the nucleic acid molecule and the attached tags may both move through the nanopore, and an ion current passing through the nanopore may indicate the nucleotide that is in the nanopore because of the particular size and/or structure of the tag attached to the nucleotide. In some implementations, only the tags may be moved into the nanopore. There may also be many different ways to detect the different tags in the nanopores.

A. Nanopore sequencing cell structure

[0048] FIG. 1 is a simplified structure illustrating an embodiment of a nanpore cell 100 in a nanopore based sequencing chip. Nanopore cell 100 may include a well formed by dielectrical material, such as oxide 106. A membrane 102 may be formed over the surface of the well to cover the well. In some embodiments, membrane 102 may be a lipid bilayer. A bulk electrolyte 114 that may contain, for example, soluble protein nanopore transmembrane molecular complexes (PNTMC) and the analyte of interest, is placed onto the surface of the cell. A single PNTMC 104 may be inserted into membrane 102 by electroporation. The individual membranes in the array are neither chemically nor electrically connected to each other. Thus, each cell in the array is an independent sequencing machine, producing data unique to the single polymer molecule associated with the PNTMC. PNTMC 104 operates on the analytes and modulates the ionic current through the otherwise impermeable bilayer.

[0049] Analog measurement circuitry 112 is connected to a metal working electrode 110 covered by a thin film of electrolyte 108. The thin film of electrolyte 108 is isolated from the bulk electrolyte 114 by the ion-impermeable membrane 102. PNTMC 104 crosses membrane 102 and provides the only path for ionic current to flow from the bulk liquid to working electrode 110. The cell also includes a counter electrode (CE) 116, which is an electrochemical potential sensor. The cell also includes a reference electrode 117.

[0050] FIG. 2 illustrates an embodiment of an example nanopore cell 200 in a nanopore sensor chip, that can be used to characterize a polynucleotide or a polypeptide. Nanopore cell 200 may include a well 205 formed of dielectric layers 201 and 204; a membrane, such as a lipid bilayer 214 formed over well 205; and a sample chamber 215 on lipid bilayer 214 and separated from well 205 by lipid bilayer 214. Well 205 may contain a volume of electrolyte 206, and sample chamber 215 may hold bulk electrolyte 208 containing a nanopore, e.g., a soluble protein nanopore transmembrane molecular complexes (PNTMC), and the analyte of interest (e.g., a nucleic acid molecule to be sequenced).

[0051] Nanopore cell 200 may include a working electrode 202 at the bottom of well 205 and a counter electrode 210 disposed in sample chamber 215. A signal source 228 may apply a voltage signal between working electrode 202 and counter electrode 210. A single nanopore (e.g., a PNTMC) may be inserted into lipid bilayer 214 by an electroporation process caused by the voltage signal, thereby forming a nanopore 216 in lipid bilayer 214. The individual membranes (e.g., lipid bilayers 214 or other membrane structures) in the array may be neither chemically nor electrically connected to each other. Thus, each nanopore cell in the array may be an independent sequencing machine, producing data unique to the single polymer molecule associated with the nanopore that operates on the analyte of interest and modulates the ionic current through the otherwise impermeable lipid bilayer.

[0052] As shown in FIG. 2, nanopore cell 200 may be formed on a substrate 230, such as a silicon substrate. Dielectric layer 201 may be formed on substrate 230. Dielectric material used to form dielectric layer 201 may include, for example, glass, oxides, nitrides, and the like. An electric circuit 222 for controlling electrical stimulation and for processing the signal detected from nanopore cell 200 may be formed on substrate 230 and/or within dielectric layer 201. For example, a plurality of patterned metal layers (e.g., metal 1 to metal 6) may be formed in dielectric layer 201, and a plurality of active devices (e.g., transistors) may be fabricated on substrate 230. In some embodiments, signal source 228 is included as a part of electric circuit 222. Electric circuit 222 may include, for example, amplifiers, integrators, analog-to-digital converters, noise filters, feedback control logic, and/or various other components. Electric circuit 222 may be further coupled to a processor 224 that is coupled to a memory 226, where processor 224 can analyze the sequencing data to determine sequences of the polymer molecules that have been sequenced in the array.

[0053] Working electrode 202 may be formed on dielectric layer 201, and may form at least a part of the bottom of well 205. In some embodiments, working electrode 202 is a metal electrode. For non-faradaic conduction, working electrode

202 may be made of metals or other materials that are resistant to corrosion and oxidation, such as, for example, platinum, gold, titanium nitride, and graphite. For example, working electrode 202 may be a platinum electrode with electroplated platinum. In another example, working electrode 202 may be a titanium nitride (TiN) working electrode. Working electrode 202 may be porous, thereby increasing its surface area and a resulting capacitance associated with working electrode 202. Because the working electrode of a nanopore cell may be independent from the working electrode of another nanopore cell, the working electrode may be referred to as cell electrode in this disclosure.

[0054] Dielectric layer 204 may be formed above dielectric layer 201. Dielectric layer 204 forms the walls surrounding well 205. Dielectric material used to form dielectric layer 204 may include, for example, glass, oxide, silicon mononitride (SiN), polyimide, or other suitable hydrophobic insulating material . The top surface of dielectric layer 204 may be silanized. The silanization may form a hydrophobic layer 220 above the top surface of dielectric layer 204. In some embodiments, hydrophobic layer 220 has a thickness of about 1.5 nanometer (nm).

[0055] Well 205 formed by dielectric layer 204 includes volume of electrolyte 206 above working electrode 202. Volume of electrolyte 206 may be buffered and may include one or more of the following: lithium chloride (LiCl), sodium chloride (NaCl), potassium chloride (KCl), lithium glutamate, sodium glutamate, potassium glutamate, lithium acetate, sodium acetate, potassium acetate, calcium chloride

(CaCk), strontium chloride (SrCk), manganese chloride (MnCk), and magnesium chloride (MgCk). In some embodiments, volume of electrolyte 206 has a thickness of about three microns (μιη).

[0056] As also shown in FIG. 2, a membrane may be formed on top of dielectric layer 204 and span across well 205. In some embodiments, the membrane may include a lipid monolayer 218 formed on top of hydrophobic layer 220. As the membrane reaches the opening of well 205, lipid monolayer 218 may transition to lipid bilayer 214 that spans across the opening of well 205. The lipid bilayer may comprise or consist of phospholipid, for example, selected from diphytanoyl- phosphatidylcholine (DPhPC), l,2-diphytanoyl-sn-glycero-3-phosphocholine, 1,2-

Di-O-Phytanyl-sn-Glycero-3-phosphocholine (DoPhPC), palmitoyl-oleoyl- phosphatidylcholine (POPC), dioleoyl-phosphatidyl-methylester (DOPME), dipalmitoylphosphatidylcholine (DPPC), phosphatidylcholine,

phosphatidylethanolamine, phosphatidylserine, phosphatidic acid,

phosphatidylinositol, phosphatidylglycerol, sphingomyelin, 1 ,2-di-O-phytanyl-sn- glycerol; 1 ,2-dipalmitoyl-sn-glycero-3-phosphoethanolamine-N- [methoxy(polyethylene glycol)-350], l,2-dioleoyl-sn-glycero-3- phosphoethanolamine-N-lactosyl; GM1 Ganglioside, Lysophosphatidylcholine (LPC) or any combination thereof.

[0057] As shown, lipid bilayer 214 is embedded with a single nanopore 216, e.g., formed by a single PNTMC. As described above, nanopore 216 may be formed by inserting a single PNTMC into lipid bilayer 214 by electroporation. Nanopore 216 may be large enough for passing at least a portion of the analyte of interest and/or small ions (e.g., Na⁺, K⁺, Ca²⁺, CI^") between the two sides of lipid bilayer 214.

[0058] Sample chamber 215 is over lipid bilayer 214, and can hold a solution of the analyte of interest for characterization. The solution may be an aqueous solution containing bulk electrolyte 208 and buffered to an optimum ion

concentration and maintained at an optimum pH to keep the nanopore 216 open. Nanopore 216 crosses lipid bilayer 214 and provides the only path for ionic flow from bulk electrolyte 208 to working electrode 202. In addition to nanopores (e.g., PNTMCs) and the analyte of interest, bulk electrolyte 208 may further include one or more of the following: lithium chloride (LiCl), sodium chloride (NaCl), potassium chloride (KC1), lithium glutamate, sodium glutamate, potassium glutamate, lithium acetate, sodium acetate, potassium acetate, calcium chloride (CaCk), strontium chloride (SrCk), Manganese chloride (MnCk), and magnesium chloride (MgCk).

[0059] Counter electrode (CE) 210 may be an electrochemical potential sensor. In some embodiments, counter electrode 210 may be shared between a plurality of nanopore cells, and may therefore be referred to as a common electrode. In some cases, the common potential and the common electrode may be common to all nanopore cells, or at least all nanopore cells within a particular grouping. The common electrode can be configured to apply a common potential to the bulk electrolyte 208 in contact with the nanopore 216. Counter electrode 210 and working electrode 202 may be coupled to signal source 228 for providing electrical stimulus (e.g., voltage bias) across lipid bilayer 214, and may be used for sensing electrical characteristics of lipid bilayer 214 (e.g., resistance, capacitance, and ionic current flow). In some embodiments, nanopore cell 200 can also include a reference electrode 212.

[0060] In some embodiments, various checks may be made during creation of the nanopore cell as part of verification or quality control. Once a nanopore cell is created, further verification steps can be performed, e.g., to identify nanopore cells that are performing as desired (e.g., one nanopore in each cell). Such verification checks can include physical checks, voltage calibration, open channel calibration, and identification of cells with a single nanopore.

B. Detection signals of nanopore sequencing cell [0061] Nanopore cells in nanopore sensor chip may enable parallel sequencing using a single molecule nanopore-based sequencing by synthesis (Nano-SBS) technique.

[0062] FIG. 3 illustrates an embodiment of a nanopore cell 300 performing nucleotide sequencing using the Nano-SBS technique. In the Nano-SBS technique, a template 332 to be sequenced (e.g., a nucleotide acid molecule or another analyte of interest) and a primer may be introduced into bulk electrolyte 308 in the sample chamber of nanopore cell 300. As examples, template 332 can be circular or linear. A nucleic acid primer may be hybridized to a portion of template 332 to which four differently polymer-tagged nucleotides 338 may be added. [0063] In some embodiments, an enzyme (e.g., a polymerase 334, such as a DNA polymerase) may be associated with nanopore 316 for use in the synthesizing a complementary strand to template 332. For example, polymerase 334 may be covalently attached to nanopore 316. Polymerase 334 may catalyze the

incorporation of nucleotides 338 onto the primer using a single stranded nucleic acid molecule as the template. Nucleotides 338 may comprise tag species ("tags") with the nucleotide being one of four different types: A, T, G, or C. When a tagged nucleotide is correctly complexed with polymerase 334, the tag may be pulled (loaded) into the nanopore by an electrical force, such as a force generated in the presence of an electric field generated by a voltage applied across lipid bilayer 314 and/or nanopore 316. The tail of the tag may be positioned in the barrel of nanopore 316. The tag held in the barrel of nanopore 316 may generate a unique ionic blockade signal 340 due to the tag's distinct chemical structure and/or size, thereby electronically identifying the added base to which the tag attaches.

[0064] As used herein, a "loaded" or "threaded" tag may be one that is positioned in and/or remains in or near the nanopore for an appreciable amount of time, e.g., 0.1 millisecond (ms) to 10000 ms. In some cases, a tag is loaded in the nanopore prior to being released from the nucleotide. In some instances, the probability of a loaded tag passing through (and/or being detected by) the nanopore after being released upon a nucleotide incorporation event is suitably high, e.g., 90% to 99%.

[0065] In some embodiments, before polymerase 334 is connected to nanopore 316, the conductance of nanopore 316 may be high, such as, for example, about 300 picosiemens (300 pS). As the tag is loaded in the nanopore, a unique conductance signal (e.g., signal 340) is generated due to the tag's distinct chemical structure and/or size. For example, the conductance of the nanopore can be about

60 pS, 80 pS, 100 pS, or 120 pS, each corresponding to one of the four types of tagged nucleotides. The polymerase may then undergo an isomerization and a transphosphorylation reaction to incorporate the nucleotide into the growing nucleic acid molecule and release the tag molecule. [0066] In some cases, some of the tagged nucleotides may not match

(complementary bases) with a current position of the nucleic acid molecule (template). The tagged nucleotides that are not base-paired with the nucleic acid molecule may also pass through the nanopore. These non-paired nucleotides can be rejected by the polymerase within a time scale that is shorter than the time scale for which correctly paired nucleotides remain associated with the polymerase. Tags bound to non-paired nucleotides may pass through the nanopore quickly, and be detected for a short period of time (e.g., less than 10 ms), while tags bounded to paired nucleotides can be loaded into the nanopore and detected for a long period of time (e.g., at least 10 ms). Therefore, non-paired nucleotides may be identified by a downstream processor based at least in part on the time for which the nucleotide is detected in the nanopore. [0067] A conductance (or equivalently the resistance) of the nanopore including the loaded (threaded) tag can be measured via a current passing through the nanopore, thereby providing an identification of the tag species and thus the nucleotide at the current position. In some embodiments, a direct current (DC) signal can be applied to the nanopore cell (e.g., so that the direction at which the tag moves through the nanopore is not reversed). However, operating a nanopore sensor for long periods of time using a direct current can change the composition of the electrode, unbalance the ion concentrations across the nanopore, and have other undesirable effects that can affect the lifetime of the nanopore cell. Applying an alternating current (AC) waveform can reduce the electro-migration to avoid these undesirable effects and have certain advantages as described below. The nucleic acid sequencing methods described herein that utilize tagged nucleotides are fully compatible with applied AC voltages, and therefore an AC waveform can be used to achieve these advantages. [0068] The ability to re-charge the electrode during the AC detection cycle can be advantageous when sacrificial electrodes, electrodes that change molecular character in the current-carrying reactions (e.g., electrodes comprising silver), or electrodes that change molecular character in current-carrying reactions are used. An electrode may deplete during a detection cycle when a direct current signal is used. The recharging can prevent the electrode from reaching a depletion limit, such as becoming fully depleted, which can be a problem when the electrodes are small (e.g., when the electrodes are small enough to provide an array of electrodes having at least 500 electrodes per square millimeter). Electrode lifetime in some cases scales with, and is at least partly dependent on, the width of the electrode. [0069] Suitable conditions for measuring ionic currents passing through the nanopores are known in the art and examples are provided herein. The

measurement may be carried out with a voltage applied across the membrane and pore. In some embodiments, the voltage used may range from -400 mV to +400 mV. The voltage used is preferably in a range having a lower limit selected from - 400 mV, -300 mV, -200 mV, -150 mV, -100 mV, -50 mV, -20 mV, and 0 mV, and an upper limit independently selected from +10 mV, +20 mV, +50 mV, +100 mV, +150 mV, +200 mV, +300 mV, and +400 mV. The voltage used may be more preferably in the range of 100 mV to 240 mV and most preferably in the range of 160 mV to 240 mV. It is possible to increase discrimination between different nucleotides by a nanopore using an increased applied potential. Sequencing nucleic acids using AC waveforms and tagged nucleotides is described in US Patent

Publication No. US 2014/0134616 entitled "Nucleic Acid Sequencing Using Tags," filed on November 6, 2013, which is herein incorporated by reference in its entirety. In addition to the tagged nucleotides described in US 2014/0134616, sequencing can be performed using nucleotide analogs that lack a sugar or acyclic moiety, e.g., (S)-Glycerol nucleoside triphosphates (gNTPs) of the five common nucleobases: adenine, cytosine, guanine, uracil, and thymine (Horhota et al, Organic Letters, 8:5345-5347 [2006]).

[0070] In some implementations, additionally or alternatively, other signal values, such as electric current values may be measured and used to identify the nucleotide threaded in a nanopore.

II. DOUBLE LAYER CAPACITANCE IN THE NANOPORE CELL

[0071] An electrical double layer may exist on the interface between a conductive electrode and its surrounding electrolyte as observed in, for example, a supercapacitor. At this interface, two layers of ions with opposing polarity may form if a voltage is applied. The two layers may be formed as ions from the electrolyte are adsorbed towards the electrode surface. The two layers of ions (one of which may or may not be absorbed onto the electrode surface) may be separated by a layer of solvent (e.g., water) molecules (not shown in FIG. 4) that acts like a dielectric in a typical capacitor. The thickness of the layer of solvent molecules may be on the order of angstroms. Charges separated by the layer of solvent molecules may thus form a capacitor. The double-layer capacitance is the capacity of storing electrical energy by means of the electrical double-layer effect. The capacitance value of the double-layer capacitor may depend on many factors, such as the electrode potential, temperature, ionic concentrations, types of ions, oxide layers, electrode roughness, impurity adsorption, etc. [0072] In a nanopore cell, such as nanopore cells 100, 200, and 300, a

capacitance may be associated with the working electrode and the liquid

electrolyte. The capacitance associated with the working electrode and the liquid electrolyte may also be referred to as an electrochemical capacitance (celectrochemical). The electrochemical capacitance Celectrochemical may include a double-layer capacitance and may further include a pseudo-capacitance. The ratio between the capacitance CBiiayer of the bilayer capacitor CBilayer and the electrochemical capacitance Celectrochemical associated with the working electrode may be adjusted to achieve optimal overall system performance. For example, increased system performance may be achieved by reducing CBiiayer while maximizing

Celectrochemical. The value of the bilayer capacitor CBiiayer may be adjusted by, for example, changing the area of the well or changing the membrane material. The value of the electrochemical capacitance Celectrochemical may be adjusted by, for example, changing the area of the well or changing the porosity of the working electrode material .

[0073] FIG. 4 illustrates a double-layer capacitor 430 that is formed at an interface between a conductive electrode 410 (e.g., working electrode 110 , 202, or 302) and an adjacent liquid electrolyte 420 (e.g., bulk electrolyte 114, 208, or 308). As described above, a conductive electrode may be made of metals or other materials that are resistant to corrosion and oxidation, such as, for example, platinum, gold, titanium nitride, and graphite. For example, the conductive electrode may be a platinum electrode with electroplated platinum. In another example, the conductive electrode may be a titanium nitride (TiN) working electrode. In some cases, the conductive electrode may be porous. In some implementations, the conductive electrode may be formed by disposing a porous

TiN electrode layer on the conductive layer. Thus, the electrolyte may penetrate through the spaces between the columnar TiN structures, vertically down the uncovered portion of the conductive electrode, and then horizontally to the covered portion of conductive electrode that is underneath dielectric layer as shown in FIG. 2, thereby increasing its surface area and a resultant capacitance associated with the conductive electrode. [0074] When a voltage is applied, electronic charges (positive or negative) may accumulate on the electrode at the interface between the conductive electrode and adjacent liquid electrolyte. In the example shown, the electrode surface is negatively charged, resulting in the accumulation of positively charged species 440 in the electrolyte. In another example, the polarity of all charges may be opposite to the example shown. The charge in the electrode may be balanced by reorientation of dipoles and accumulation of ions of opposite charge in the electrolyte near the interface. The accumulation of charges on both sides of the interface between the electrode and electrolyte that are separated by a small distance due to the finite size of charged species and solvent molecules in the electrolyte creates a capacitive effect. Thus, the term "double layer" may refer to the ensemble of electronic and ionic charge distribution in the vicinity of the interface between the electrode layer and the bulk liquid electrolyte layer.

[0075] FIG. 5 illustrates a pseudo-capacitance effect that can be formed concurrently with the formation of a double-layer capacitor as in FIG. 4, at an interface between a conductive electrode 510 and an adjacent liquid electrolyte 520. A pseudo-capacitor may store electrical energy faradaically by electron charge transfer between the electrode and the electrolyte. This may be accomplished through electrosorption, reduction-oxidation reactions, or intercalation processes. FIG. 5 shows a double-layer capacitor 530 with the addition of pseudo-capacitance from charge transfer resulting in adsorption, intercalation, or reduction-oxidation reactions limited by available surface area (represented by solid circles).

[0076] It is desirable for the working electrode to have a high capacitance, thereby reducing its impedance effect on the circuit, which can cause the voltage levels to move slightly as a result of charge built up after multiple measurements.

III. ELECTRIC MODEL OF NANOPORE SEQUENCING CELL

[0077] FIG. 6 illustrates an electric circuit 600 ( which may include portions of electric circuit 222 in FIG. 2) representing an electrical model in a nanopore cell, such as nanopore cell 200. As described above, in some embodiments, electric circuit 600 includes a counter electrode 640 (e.g., counter electrode 210) that may be shared between a plurality of nanopore cells or all nanopore cells in a nanopore sensor chip, and may therefore also be referred to as a common electrode. The common electrode can be configured to apply a common potential to the bulk electrolyte (e.g., bulk electrolyte 208) in contact with the lipid bilayer (e.g., lipid bilayer 214) in the nanopore cells by connecting to a voltage source Viiq 620. In some embodiments, an AC non-Faradaic mode may be utilized to modulate voltage Viiq with an AC signal (e.g., a square wave) and apply it to the bulk electrolyte in contact with the lipid bilayer in the nanopore cell. In some embodiments, Viiq is a square wave with a magnitude of ±200-250 mV and a frequency between, for example, 25 and 600 Hz. The bulk electrolyte between counter electrode 640 and the lipid bilayer may be modeled by a large capacitor (not shown), such as 100 μΡ or larger.

[0078] FIG. 6 also shows an electrical model 622 representing the electrical properties of a working electrode 602 (e.g., working electrode 202) and the lipid bilayer (e.g., lipid bilayer 214). Electrical model 622 includes a capacitor 626

(CBiiayer) that models a capacitance associated with the lipid bilayer and a resistor Rpore 628 that models a variable resistance associated with the nanopore, which can change based on the presence of a particular tag in the nanopore. Electrical model 622 also includes a capacitor Cdbi 624 having a double-layer capacitance caw and representing the electrical properties of working electrode 602 and the well (e.g., well 205) of the cell. Working electrode 602 may be configured to apply a distinct potential independent from the working electrodes in other nanopore cells.

[0079] Pass device 606 may be a switch that can be used to connect or disconnect the lipid bilayer and the working electrode from electric circuit 600. Pass device 606 may be controlled by a memory bit to enable or disable a voltage stimulus to be applied across the lipid bilayer in the nanopore cell. Before lipids are deposited to form the lipid bilayer, the impedance between the two electrodes may be very low because the well of the nanopore cell is not sealed, and therefore pass device 606 may be kept open to avoid a short-circuit condition. Pass device 606 may be closed after lipid solvent has been deposited to the nanopore cell to seal the well of the nanopore cell. [0080] Electric circuit 600 may further include an on-chip integrating capacitor Cint 608 (neap). Integrating capacitor Cint 608 may be pre-charged by using a reset signal 603 to close switch 601, such that integrating capacitor Cint 608 is connected to a voltage source V_pre 605. In some embodiments, voltage source V_pre 605 provides a constant positive voltage with a magnitude of, for example, 900 mV.

When switch 601 is closed, integrating capacitor Cint 608 may be pre-charged to the positive voltage level of voltage source V_pre 605.

[0081] After integrating capacitor Cint 608 is pre-charged, reset signal 603 may be used to open switch 601 such that integrating capacitor Cint 608 is disconnected from voltage source V_pre 605. At this point, depending on the level of voltage source Vu_q, the potential of counter electrode 640 may be at a level higher than the potential of working electrode 602 (and integrating capacitor Cint 608), or vice versa. For example, during a positive phase of a square wave from voltage source Viiq (e.g., the bright or dark period of the AC voltage source signal cycle), the potential of counter electrode 640 is at a level higher than the potential of working electrode 602. During a negative phase of the square wave from voltage source Vu_q (e.g., the dark or bright period of the AC voltage source signal cycle), the potential of counter electrode 640 is at a level lower than the potential of working electrode 602. Thus, in some embodiments, integrating capacitor Cint 608 may be further charged during the bright period from the pre-charged voltage level of voltage source V_pre 605 to a higher level, and discharged during the dark period to a lower level, due to the potential difference between counter electrode 640 and working electrode 602. In other embodiments, the charging and discharging may occur in dark periods and bright periods, respectively. [0082] Integrating capacitor Cint 608 may be charged or discharged for a fixed period of time, depending on the sampling rate of an analog-to-digital converter (ADC) 610, which may be higher than 1 kHz, 5 kHz, 10 kHz, 100 kHz, or more. For example, with a sampling rate of 1 kHz, integrating capacitor Cint 608 may be charged/discharged for a period of about 1 ms, and then the voltage level may be sampled and converted by ADC 610 at the end of the integration period. A particular voltage level would correspond to a particular tag species in the nanopore, and thus correspond to the nucleotide at a current position on the template.

[0083] After being sampled by ADC 610, integrating capacitor Cint 608 may be pre-charged again by using reset signal 603 to close switch 601, such that integrating capacitor Cint 608 is connected to voltage source V_pre 605 again. The steps of pre-charging integrating capacitor Cint 608, waiting for a fixed period of time for integrating capacitor Cint 608 to charge or discharge, and sampling and converting the voltage level of integrating capacitor by ADC 610 can be repeated in cycles throughout the sequencing process. [0084] A digital processor 630 can process the ADC output data, e.g., for normalization, data buffering, data filtering, data compression, data reduction, event extraction, or assembling ADC output data from the array of nanopore cells into various data frames. In some embodiments, digital processor 630 can perform further downstream processing, such as base determination. Digital processor 630 can be implemented as hardware (e.g., in a GPU, FPGA, ASIC, etc.) or as a combination of hardware and software.

[0085] Accordingly, the voltage signal applied across the nanopore can be used to detect particular states of the nanopore. One of the possible states of the nanopore is an open-channel state when a tag-attached polyphosphate is absent from the barrel of the nanopore. Another four possible states of the nanopore each correspond to a state when one of the four different types of tag-attached polyphosphate nucleotides (A, T, G, or C) is held in the barrel of the nanopore. Yet another possible state of the nanopore is when the lipid bilayer is ruptured.

[0086] When the voltage level on integrating capacitor Cint 608 is measured after a fixed period of time, the different states of a nanopore may result in

measurements of different voltage levels. This is because the rate of the voltage decay (decrease by discharging or increase by charging) on integrating capacitor Cint 608 (i.e., the steepness of the slope of a voltage on integrating capacitor Cint 608 versus time plot) depends on the nanopore resistance (e.g., the resistance of resistor R_pOTe 628). More particularly, as the resistance associated with the nanopore in different states is different due to the molecules' (tags') distinct chemical structures, different corresponding rates of voltage decay may be observed and may be used to identify the different states of the nanopore. The voltage decay curve may be an exponential curve with an RC time constant τ = RC, where R is the resistance associated with the nanopore (i.e., Rpore 628) and C is the capacitance associated with the membrane (i.e., capacitor 626 (CBiiayer)) in parallel with R. A time constant of the nanopore cell can be, for example, about 200-500 ms. The decay curve may not fit exactly to an exponential curve due to the detailed implementation of the bilayer, but the decay curve may be similar to an exponential curve and is monotonic, thus allowing detection of tags. [0087] In some embodiments, the resistance associated with the nanopore in an open-channel state may be in the range of 100 MOhm to 20 GOhm. In some embodiments, the resistance associated with the nanopore in a state where a tag is inside the barrel of the nanopore may be within the range of 200 MOhm to 40 GOhm. In other embodiments, integrating capacitor Cint 608 may be omitted, as the voltage leading to ADC 610 will still vary due to the voltage decay in electrical model 622.

[0088] The rate of the decay of the voltage on integrating capacitor Cint 608 may be determined in different ways. As explained above, the rate of the voltage decay may be determined by measuring a voltage decay during a fixed time interval. For example, the voltage on integrating capacitor 608 may be first measured by ADC

610 at time tl, and then the voltage is measured again by ADC 610 at time t2. The voltage difference is greater when the slope of the voltage on integrating capacitor Cint 608 versus time curve is steeper, and the voltage difference is smaller when the slope of the voltage curve is less steep. Thus, the voltage difference may be used as a metric for determining the rate of the decay of the voltage on integrating capacitor Cint 608, and thus the state of the nanopore cell.

[0089] In other embodiments, the rate of the voltage decay can be determined by measuring a time duration that is required for a selected amount of voltage decay. For example, the time required for the voltage to drop or increase from a first voltage level VI to a second voltage level V2 may be measured. The time required is less when the slope of the voltage vs. time curve is steeper, and the time required is greater when the slope of the voltage vs. time curve is less steep. Thus, the measured time required may be used as a metric for determining the rate of the decay of the voltage Vncap on integrating capacitor Cint 608, and thus the state of the nanopore cell. One skilled in the art will appreciate the various circuits that can be used to measure the resistance of the nanopore, e.g., including current measurement techniques.

[0090] In some embodiments, electric circuit 600 may not include a pass device (e.g., pass device 606) and an extra capacitor (e.g., integrating capacitor 608 (Cint)) that are fabricated on-chip, thereby facilitating the reduction in size of the nanopore-based sequencing chip. Due to the thin nature of the membrane (lipid bilayer), the capacitance associated with the membrane (e.g., capacitor 626

(CBiiayer)) alone can suffice to create the required RC time constant without the need for additional on-chip capacitance. Therefore, capacitor 626 may be used as the integrating capacitor, and may be pre-charged by the voltage signal V_pre and subsequently be discharged or charged by the voltage signal Vu_q. The elimination of the extra capacitor and the pass device that are otherwise fabricated on-chip in the electric circuit can significantly reduce the footprint of a single nanopore cell in the nanopore sequencing chip, thereby facilitating the scaling of the nanopore sequencing chip to include more and more cells (e.g., having millions of cells in a nanopore sequencing chip).

IV. DATA SAMPLING IN NANOPORE CELL

[0091] To perform sequencing of a nucleic acid, the voltage level of integrating capacitor (e.g., integrating capacitor Cint 608 (n_cap) or capacitor 626 (CBiiayer)) can be sampled and converted by the ADC (e.g., ADC 610) while a tagged nucleotide is being added to the nucleic acid. The tag of the nucleotide can be pushed into the barrel of the nanopore by the electric field across the nanopore that is applied through the counter electrode and the working electrode, for example, when the applied voltage is such that Vu_q is lower than Vpre. A. Threading

[0092] A threading event is when a tagged nucleotide is attached to the template (e.g., nucleic acid fragment), and the tag goes in and out of the barrel of the nanopore. This can happen multiple times during a threading event. When the tag is in the barrel of the nanopore, the resistance of the nanopore may be higher, and a lower current may flow through the nanopore.

[0093] During sequencing, a tag may not be in the nanopore in some AC cycles (referred to as an open-channel state), where the current is the highest because of the lower resistance of the nanopore. When a tag is attracted into the barrel of the nanopore, the nanopore is in a bright mode. When the tag is pushed out of the barrel of the nanopore, the nanopore is in a dark mode.

B. Bright and dark period

[0094] During an AC cycle, the voltage on integrating capacitor may be sampled multiple times by the ADC. For example, in one embodiment, an AC voltage signal is applied across the system at, e.g., about 100 Hz, and an acquisition rate of the

ADC can be about 2000 Hz per cell. Thus, there can be about 20 data points (voltage measurements) captured per AC cycle (cycle of an AC waveform). Data points corresponding to one cycle of the AC waveform may be referred to as a set. In a set of data points for an AC cycle, there may be a subset captured when, for example, Viiq is lower than V_pre, which may correspond to a bright mode (period) where the tag is forced into the barrel of the nanopore. Another subset may correspond to a dark mode (period) where the tag is pushed out of the barrel of the nanopore by the applied electric field when, for example, Viiq is higher than V_pre.

C. Measured voltages [0095] For each data point, when the switch 601 is opened, the voltage at the integrating capacitor (e.g., integrating capacitor Cint 608 (n_cap) or capacitor 626 (CBiiayer)) will change in a decaying manner as a result of the charging/discharging by Viiq, e.g., as an increase from V_pre to Vu_q when Vu_q is higher than V_pre or a decrease from V_pre to Viiq when Vu_q is lower than V_pre. The final voltage values may deviate from Viiq as the working electrode charges. The rate of change of the voltage level on the integrating capacitor may be governed by the value of the resistance of the bilayer, which may include the nanopore, which may in turn include a molecule (e.g., a tag of a tagged nucleotides) in the nanopore. The voltage level can be measured at a predetermined time after switch 601 opens.

[0096] Switch 601 may operate at the rate of data acquisition. Switch 601 may be closed for a relatively short time period between two acquisitions of data, typically right after a measurement by the ADC. The switch allows multiple data points to be collected for each cycle. If switch 601 remains open, the voltage level on the integrating capacitor, and thus the output value of the ADC, would fully decay and stay there. Such multiple measurements can allow higher resolution with a fixed ADC (e.g. 8-bit to 14-bit due to the greater number of measurements, which may be averaged). The multiple measurements can also provide kinetic information about the molecule threaded into the nanopore. The timing information may allow the determination of how long a threading takes place. This can also be used in helping to determine whether multiple nucleotides that are added to the nucleic acid strand are being sequenced.

[0097] FIG. 7 illustrates example control and measured signals on a nanopore cell during nucleotide sequencing, prior to introducing tags. Therefore, the nanopore is effectively in a consistent open-channel state, and the measured signal may not show insertion of any tags in the nanopore. An AC voltage source, such as voltage source Vu_q 620, may be utilized as a reference voltage Vu_q 710 on a counter electrode (e.g., counter electrode 640) of a nanopore cell. In FIG. 7, reference voltage Viiq 710 may be a square wave voltage signal with labeled bright periods and dark periods. Corresponding control signals, such as a reset signal 720 (e.g., reset signal 603 used to control switch 601 for connecting integrating capacitor Cmt 608 and double-layer capacitor (Cdbi) 624 to voltage source V_pre 605), are also shown.

[0098] In each frame, reset signal 720 may be high in the precharging period Tprecharge, during which the double-layer capacitor (e.g., Cdbi 624) may be connected to, for example, voltage source V_pre 605, and may be precharged to V_pre. Reset signal 720 may be low in the integrating period 1 integrating, during which the double- layer capacitor may be connected to reference voltage Vu_q 710 through, for example, Rpore 628 and/or capacitor 626 (CBikyer), and may be charged or discharged by reference voltage Vu_q 710. In the example shown in FIG. 7, during the bright periods, reference voltage Vu_q 710 is lower than V_pre, and thus the double-layer capacitor is discharged. During the dark periods, reference voltage Viiq 710 is higher than V_pre, and thus the double-layer capacitor is charged.

[0099] The voltage level on the double-layer capacitor may be measured from an integrating capacitor (e.g., integrating capacitor Cint 608) using an ADC (e.g., ADC 610). The voltage Vncap 730 across the integrating capacitor over time is shown in

FIG. 7. The "saw tooth" shape of the voltage results from the discharging (during bright periods) and charging (during dark periods) of the double-layer capacitor during the bright and dark periods. Each "saw tooth" may correspond to each measurement sample that is taken. For example, during the bright period for each measurement sample, the double-layer capacitor may be pre-charged to 0.90 V, and this voltage/charge is dissipated by the resistor R_pOTe of the nanopore until the next pre-charge of the double-layer capacitor for the next measurement sample. In this example, during the dark period for each measurement sample, the double-layer capacitor is first pre-charged/dissipated (reset) to 0.90 V and this voltage is increased at a rate associated with the resistance of the nanopore until the next pre- charge/reset of the capacitor for the next measurement sample.

[0100] It is noted that FIG. 7 shows a few measurement samples in a bright or dark period for ease of illustration. More or less measurement samples may be captured in each period. For example, tens of samples or even hundreds of samples may be captured in a bright or dark period. It is also noted that some other control signals may be used for the sequencing but may not be shown in FIG. 7. It is further noted that, in some implementations, reference voltage Viiq 710 may be at a constant level while voltage source V_pre may be an AC signal.

[0101] FIG. 8 illustrates an example small signal model 800 for non-faradaic conduction in a nanopore cell as described above. The small signal model may include a double-layer capacitor Cdbi 804 with a capacitance of Cdbi, an optional integrating capacitor Cint 806, a pore resistor R_pOTe 802 with a resistance r_pOTe representing the nanopore, and a bilayer capacitor CBiiayer 808 representing the bilayer (e.g., lipid bilayer 214). FIG. 8 shows that double-layer capacitor Cdbi 804 may be charged or discharged through pore resistor R_pOTe 802 and bilayer capacitor CBiiayer 808. Bilayer capacitor CBiiayer 808 may be small and thus the impedance of

CBiiayer 808 may be much larger compared with R_p0re 802. Therefore, bilayer capacitor CBiiayer 808 may be optional (as shown by dotted line) in small signal model 800. Small signal model 800 may be used to determine the decay of the voltage signal on double-layer capacitor Cdbi 804. For example, the decay may have a time constant τ determined by x~r_p0reCdbi, where time constant τ may represent the time required for the voltage level to decay to 1/e ~ 36.8% of the initial value.

[0102] In some embodiments, the resistance associated with the nanopore in an open-channel state may be in the range of 100 MOhm to 20 GOhm. In some embodiments, the resistance associated with the nanopore in a state where a tag is inside the barrel of the nanopore may be within the range of 200 MOhm to 60

GOhm.

[0103] The rate of the decay of the voltage on integrating capacitor Cint 608 may be determined in different ways. As explained above, the rate of the voltage decay may be determined by measuring a voltage decay during a fixed time interval. For example, the voltage on integrating capacitor Cint 608 may be first measured by

ADC 610 at time tl, and then the voltage is measured again by ADC 610 at time t2. The voltage difference is greater when the slope of the voltage on integrating capacitor Cint 608 versus time curve is steeper, and the voltage difference is smaller when the slope of the voltage curve is less steep. Thus, the voltage difference may be used as a metric for determining the rate of the decay of the voltage on integrating capacitor Cint 608, and thus the state of the nanopore cell.

[0104] In other embodiments, the rate of the voltage decay can be determined by measuring a time duration that is required for a selected amount of voltage decay. For example, the time required for the voltage to drop or increase from a first voltage level VI to a second voltage level V2 may be measured. The time required is less when the slope of the voltage vs. time curve is steeper, and the time required is greater when the slope of the voltage vs. time curve is less steep. Thus, the measured time required may be used as a metric for determining the rate of the decay of the voltage on integrating capacitor Cmt 608, and thus the state of the nanopore cell. One skilled in the art will appreciate the various circuits that can be used to measure the resistance of the nanopore, e.g., including current measurement techniques.

[0105] FIG. 9 shows example data points captured from a nanopore cell during bright periods and dark periods of AC cycles. In FIG. 9, the change in the data points is exaggerated for illustration purpose. The voltage (V_pre) applied to the working electrode or the integrating capacitor is at a constant level, such as 900 mV. A voltage signal 910 (Vu_q) applied to the counter electrode of the nanopore cells is an AC signal shown as a rectangular wave, where the duty cycle may be any suitable value, such as less than or equal to 90%, for example, about 40%.

[0106] During a bright period 920, voltage signal 910 (Vuq) applied to the counter electrode is lower than the voltage V_pre applied to the working electrode, such that a tag may be forced into the barrel of the nanopore by the electric field caused by the different voltage levels applied at the working electrode and the counter electrode (e.g., due to the charge on the tag and/or flow of the ions). When switch 601 is opened, , the voltage at a node before the ADC (e.g., at an integrating capacitor) will decrease. After a voltage data point is captured (e.g., after a specified time period), switch 601 may be closed and the voltage at the

measurement node will increase back to Vpre again. The process can repeat to measure multiple voltage data points. In this way, multiple data points may be captured during the bright period. [0107] As shown in FIG. 9, a first data point 922 (also referred to as first point delta (FPD)) in the bright period after a change in the sign of the Vu_q signal may be lower than subsequent data points 924. This may be because there is no tag in the nanopore (open channel), and thus it has a low resistance and a high discharge rate. In some instances, first data point 922 may exceed the Viiq level as shown in FIG. 9. This may be caused by the capacitance of the bilayer coupling the signal to the on- chip capacitor. Data points 924 may be captured after a threading event has occurred, i.e., a tag is forced into the barrel of the nanopore, where the resistance of the nanopore and thus the rate of discharging of the integrating capacitor depends on the particular type of tag that is forced into the barrel of the nanopore. Data points 924 may decrease slightly for each measurement due to charge built up at the double-layer capacitor (e.g., Cdbi 804), as mentioned below.

[0108] During a dark period 930, voltage signal 910 (Vuq) applied to the counter electrode is higher than the voltage (V_pre) applied to the working electrode, such that any tag would be pushed out of the barrel of the nanopore. When switch 601 is opened, the voltage at the measurement node increases because the voltage level of voltage signal 910 (Vuq) is higher than V_pre. After a voltage data point is captured (e.g., after a specified time period), switch 601 may be closed and the voltage at the measurement node will decrease back to V_pre again. The process can repeat to measure multiple voltage data points. Thus, multiple data points may be captured during the dark period, including a first point delta 932 and subsequent data points 934. As described above, during the dark period, any nucleotide tag is pushed out of the nanopore, and thus minimal information about any nucleotide tag is obtained, besides for use in normalization. Therefore, the output voltage signals from the cells during the dark period may have little or no use.

[0109] FIG. 9 also shows that during bright period 940, even though voltage signal 910 (Vuq) applied to the counter electrode is lower than the voltage (V_pre) applied to the working electrode, no threading event occurs (open-channel). Thus, the resistance of the nanopore is low, and the rate of discharging of the integrating capacitor is high. As a result, the captured data points, including a first data point 942 and subsequent data points 944, show low voltage levels. [0110] The voltage measured during a bright or dark period might be expected to be about the same for each measurement of a constant resistance of the nanopore (e.g., made during a bright mode of a given AC cycle while one tag is in the nanopore), but this may not be the case when charge builds up at double-layer capacitor Cdbi. This charge build-up can cause the time constant of the nanopore cell to become longer. As a result, the voltage level may be shifted, thereby causing the measured value to decrease for each data point in a cycle. Thus, within a cycle, the data points may change somewhat from data point to another data point, as shown in FIG. 9. Thus, it may desirable to measure the double-layer capacitance for data normalization and baseline adjustment in order to more accurately determine the bases associated with the measured voltage levels. D. Determining bases

[0111] For each usable nanopore cell of the nanopore sensor chip, a production mode can be run to sequence nucleic acids. The ADC output data captured during the sequencing can be normalized to provide greater accuracy. Normalization can account for offset effects, such as cycle shape and baseline shift. After normalization, embodiments can determine clusters of voltages for the threaded channels, where each cluster corresponds to a different tag species, and thus a different nucleotide. The clusters can be used to determine probabilities of a given voltage corresponding to a given nucleotide. As another example, the clusters can be used to determine cutoff voltages for discriminating between different nucleotides (bases). Further details regarding normalization can be found in U.S.

Patent Applications 15/632,190 and 15/628,353, which are incorporated by reference in their entirety.

[0112] Further details regarding the sequencing operation can be found in, for example, U.S. Patent Publication No. 2016/0178577 entitled "Nanopore-Based Sequencing With Varying Voltage Stimulus," U.S. Patent Publication No.

2016/0178554 entitled "Nanopore-Based Sequencing With Varying Voltage Stimulus," U.S. Patent Application No. 15/085,700 entitled "Non-Destructive Bilayer Monitoring Using Measurement Of Bilayer Response To Electrical Stimulus," and U.S. Patent Application No. 15/085,713 entitled "Electrical Enhancement Of Bilayer Formation," which are incorporated by reference in their entirety.

V. DOUBLE LAYER CAPACITANCE MEASUREMENT

[0113] The double-layer capacitance may be measured using various methods. For example, electrochemical impedance spectroscopy (EIS) is a technique for characterizing electrochemical systems and for determining the contribution of electrode or electrolytic processes in these systems. EIS can be used to determine the dynamics of linked or mobile charges in the volume of the interface regions between any liquid and solid material. The EIS technique works in the frequency domain and is based on the concept that an interface can be seen as a combination of passive electrical circuit elements, i.e., resistance, capacitance, and inductance.

When an alternating signal of small amplitude (e.g., 5 to 20 mV) is applied to an electrode inserted into an electrolyte, the resulting current may be obtained and used to determine the impedance based on Ohm's law. The initial disturbance (applied) and the response of the electrode may be compared by measuring the phase shift of the current and voltage components or by the measurements of their amplitudes. This can be done in time domain or in frequency domain using external instruments such as a spectrum analyzer or frequency response analyzer. However, because a current measured through the electrolyte may include current passing through multiple working electrodes (e.g., over 1000 working electrodes) exposed to the electrolyte, the EIS technique may not measure the double-layer capacitance of individual cells either before or after the formation of the bilayer and nanopore. Furthermore, the EIS technique may capture resistive components as part of the total impedance, rather than only measuring the capacitive components. In addition, accuracy of the EIS technique may be limited by the amplitude of the response to stimulus, and by the obfuscating effects of parasitic contributions from cells not being measured. For these and some other reasons, the accuracy of the EIS measurement may be limited.

[0114] Methods disclosed herein can more accurately measure the double-layer capacitor of an individual (nanopore) cell or a group of (nanopore) cells at different stages of the sequencing process. One example method may measure the double- layer capacitance before the formation of the bilayer and nanopore by repeatedly charging or discharging the double-layer capacitor using a smaller capacitor with a known capacitance value and a known initial voltage level, which may be referred to as a charge titration capacitance measurement (CTCM) technique. Another example method may measure the double-layer capacitance after the formation of the bilayer and nanopore by charging the double-layer capacitor and measuring the decay of the voltage on the double-layer capacitor through the nanopore to a reference voltage level, which may be referred to as a step response capacitance measurement (SRCM) technique. Both CTCM and SRCM techniques may be performed using existing circuits on the nanopore sensor chip. Thus, external instruments may not be needed for the measurement. In addition, the measurement can be performed fairly quickly, such as less than about a minute, instead of 15-20 minutes using some other techniques.

A. Step Response Capacitance Measurement (SRCM)

[0115] As described above with respect to FIG. 8, the small signal model of a nanopore cell may include a double-layer capacitor Cdbi with a capacitance of Cdbi, an integrating capacitor Cint, a pore resistor R_pOTe with a resistance r_pOTe representing the nanopore, and a bilayer capacitor CBikyer representing the bilayer. The double- layer capacitor Cdbi (and integrating capacitor Cint) may be charged or discharged through pore resistor R_pOTe and bilayer capacitor CBikyer (which may be negligible). Thus, the decay of voltage level on the double-layer capacitor Cdbi or integrating capacitor Cint may have a time constant τ determined by x~r_p0reCdbi. By measuring the decay of the voltage level on the double-layer capacitor or integrating capacitor Cint, the time constant and thus Cdbi may be determined with a known r_pOTe. In some implementations, the time constant, rather the double-layer capacitance, may be used for the normalization because the decay is also affected by the resistance of the pore resistor R_pOTe. In some implementations, the decay time may be determined by measuring the changes of the current flowing through double-layer capacitor Cdbi and pore resistor R_pOTe over time.

[0116] In some implementations of the SRCM technique, the bilayer may be formed and the nanopore may be inserted as described above. A voltage level (V_pre) may be applied to the working electrode and a voltage level (Vu_q) may be applied to the counter electrode. Subsequently, the working electrode may be disconnected from V_pre, and a slow square wave AC signal with a small amplitude may be applied to the counter electrode Vu_q, which may cause the voltage level on the double-layer capacitor and integrating capacitor Cint to shift and then decay (charge and discharge) during an AC cycle. The time required for the intra-cycle signal decay to reach a set fraction of its initial value may be determined based on, for example, the measured voltage signals on the integrating capacitor Cint. The time constant obtained may be used for data normalization. In some implementations, the SRCM-based double-layer capacitance measurement may be performed for each sequencing process, such that the sequencing signal for each sequencing process may have a recent associated SRCM-based double-layer capacitance measurement result.

1. Circuits for step response

[0117] FIG. 10A illustrates an example configuration of a circuit 1000 in a nanopore cell for establishing a baseline during a step response capacitance measurement, according to certain embodiments. Circuit 1000 may include a double-layer capacitor Cdbi 1004, a pore resistor R_pOTe 1002, a bilayer capacitor CBikyer 1008, an integrating capacitor Cint 1006, a switch 1010 for connecting the working electrode and integrating capacitor Cint 1006 to a voltage source Vpre, a switch 1012 for connecting integrating capacitor Cint 1006 to an ADC 1014. In FIG. 10A, a voltage signal V_pre may have been connected to the working electrode through switch 1010, a voltage signal Vu_q at a level of V_seq may have been connected to the counter electrode. The working electrode may have disconnected from Vpre, and the nanopore cell may have reached a steady state.

[0118] FIG. 10B illustrates an example configuration of circuit 1000 in a nanopore cell for measuring the negative step response during a step response capacitance measurement, according to certain embodiments. In FIG. 10B, a negative step signal (e.g., at a level equal to Vseq-AV) may be applied to the counter electrode (Vu_q), which may cause the voltage level on the working electrode (and double-layer capacitor Cdbi 1004) to drop instantaneously (because the voltage across double-layer capacitor Cdbi 1004 cannot change instantaneously) and then decay (increase) gradually. A series of samples may be captured by ADC 1014 during the decay by repeatedly switching on and off switch 1012 for sampling voltage Vncap across integrating capacitor Cint 1006 (which may equal to the voltage VWE on the working electrode. [0119] FIG. IOC illustrates an example configuration of circuit 1000 in a nanopore cell for measuring positive step response during a step response capacitance measurement, according to certain embodiments. In FIG. IOC, a positive step signal (e.g., at a level equal to V_seq+AV) may be applied to the counter electrode (Viiq) , which may cause the voltage level on the working electrode (and double-layer capacitor Cdbi 1004) to increase instantaneously (because the voltage across double-layer capacitor Cdbi 1004 cannot change instantaneously) and then decay (decrease) gradually. A series of samples may be captured by ADC 1014 during the decay by repeatedly switching on and off switch 1012 for sampling the voltage Vncap across integrating capacitor Cint 1006.

2. Signals for step response

[0120] FIG. 11 illustrates an example AC signal 1100 for measuring a double- layer capacitance using a step response capacitance measurement technique, according to certain embodiments. AC signal 1100 may be applied to the counter electrode (Vu_q). In the specific example shown in FIG. 11, AC signal 1100 may be at 225 mV for about 30 seconds to establish a steady state on the working electrode as discussed above. After that, a number of cycles (e.g., 6) of a square wave signal with an offset of 225 mV, an amplitude of 20 mV (40 mV peak-to-peak), and a frequency of 0.2 Hz (i.e., a period of 5 seconds) may be applied to the counter electrode. During the 2.5-second period in each cycle when AC signal 1100 is at

245 mV, voltage Vncap across the integrating capacitor may be sampled multiple times (e.g., tens or hundreds of times) to measure the positive step decay curve. During the 2.5-second period in each cycle when AC signal 1100 is at 205 mV, voltage Vncap across the integrating capacitor may be sampled multiple times to measure the negative step decay curve.

[0121] It is noted that AC signal 1100 shown in FIG. 11 is just one possible implementation of the technique disclosed herein. In various implementations, different frequencies, amplitudes, and/or offset may be used. Furthermore, in various implementations, different number of cycles of square wave signal may be used. In one implementation, a single cycle of square wave may be used. In some implementations, more than one cycle of square wave may be used and an average of the results measured in multiple cycles of the square wave may be taken to reduce the noise and improve the accuracy of the measurement results.

[0122] In some implementations, AC signal 1100 may be applied to the working electrode, while the voltage on the counter electrode (Vu_q) may be kept at a steady state. During the time period in each cycle when AC signal 1100 is high, voltage

Vncap across the integrating capacitor may be sampled multiple times (e.g., tens or hundreds of times) to measure a decay curve. During the time period in each cycle when AC signal 1100 is low, voltage Vncap across the integrating capacitor may be sampled multiple times to measure a decay curve. In some implementations, when voltage Vncap is being measured, the working electrode may be temporally disconnected from AC signal 1100.

[0123] FIG. 12A illustrates example results for measuring a double-layer capacitor with a lower capacitance using a step response capacitance measurement technique, according to certain embodiments. An AC signal 1210 including a hold period 1240 and a number of AC cycles 1250 of a square wave as described above with respect to AC signal 1100 of FIG. 11 may be applied to the counter electrode (Viiq). The measured voltages (represented by, for example, 8-bit ADC output values (0-255)) across the integrating capacitor (i.e., voltage levels on the working electrode) are represented by a measured signal 1220, which may include may data points, such as tens or hundreds or more of data points. As can be seen in FIG.

12 A, for a double-layer capacitor with a lower capacitance, the decay is faster and may appear larger for each voltage step in the square wave, and the baseline shift is relative low for both the positive step and the negative step.

[0124] FIG. 12B illustrates example results for measuring a double-layer capacitor with a higher capacitance using a step response capacitance measurement technique, according to certain embodiments. AC signal 1210 including a hold period and a number of cycles of a square wave as described above with respect to AC signal 1100 of FIG. 11 may be applied to the counter electrode (Viiq). The measured voltages (represented by, for example, 8-bit ADC output values (0-255)) across the integrating capacitor (i.e., voltage levels on the working electrode) are represented by a measured signal 1230. As can be seen in FIG. 12B, for a double- layer capacitor with a higher capacitance, the decay is relative slow and small for each voltage step in the square wave, and the baseline to which the voltage decays may shift significantly and may be different for the positive step and the negative step. [0125] More detailed description and analysis of the waveform of the measured signal 1220 or 1230 for double-layer capacitance measurement using the SRCM technique are provided below.

[0126] FIG. 13 illustrates the decay of a voltage signal 1300 on a double-layer capacitor or an integrating capacitor during a step response capacitance

measurement, according to certain embodiments. Measured voltage signal 1300 shown in FIG. 13 includes voltages levels 1310 measured in a hold period. The hold period may be sufficiently long (e.g., about 30 seconds) such that voltage signal 1300 may decay to a steady state (not changing or changing very little) before the end of the hold period for determining a hold baseline. For example, the median of the last 30 sample points captured in the hold period may be used as the value for hold baseline 1320.

[0127] For each positive step, voltage levels on the working electrode may be measured as a series of data points. The first few (e.g., 5) data points may be removed from data analysis as these data points may be captured when the voltage signal on the working electrode has an overshoot. In some implementations, a rolling mean filtering may be performed on the data points to average the waveform. The last few (e.g., 10) data points in the positive step period may be used to determine a positive baseline level 1360. Each data point may then be adjusted by subtracting positive baseline level 1360 from the measured voltage level for each data point. The maximum voltage level 1330 among the adjusted data points in the positive step period may be used as the positive gain of the nanopore cell, which may be proportional to the open-channel gain of the nanopore cell, and may depend on the bilayer capacitance or the integrating capacitance, and the pore resistance r_pOTe of the nanopore cell (~l/(r_p0reCint)). The time it takes for the voltage level on the working electrode to decay from the positive gain value

(voltage level 1330) to, for example, 75% of the positive gain (voltage level 1340) may be determined as the 75% decay time pos_75. The time it takes for the voltage level on the working electrode to decay from the positive gain value (voltage level 1330) to, for example, 50%> of the positive gain (voltage level 1350) may be determined as the 50%> decay time pos_50. The 75% decay time pos_75 and/or 50% decay time pos_50 may then be used to determine the decay time constant x~rporeCdbi or the double-layer capacitance as described below. It is noted that, in different implementations, the decay time can be determined based on the time it takes for the voltage level on the working electrode to decay to levels other than 75%) or 50%) of the positive gain. [0128] In some implementations, corresponding data points captured in different positive step periods may be averaged and used as the waveform for a single positive step period for determining the above described parameters, such as positive gain, positive baseline, pos_75, pos_50, decay times for other voltage levels, the decay time constant, and the double-layer capacitance. The accuracy of the measurement may be improved by averaging the results from positive step periods.

[0129] Additionally or alternatively, for each negative step, data points can be captured and analyzed in a similar way to determine parameters such as negative gain, negative baseline, 75% negative decay time, 50%> negative decay time, decay times for other voltage levels, decay time constant, double-layer capacitance, etc.

For example, in some implementations, the measurement results from the negative steps may be used to verify the measurement results from the positive steps or vice versa, as the measurement results from the negative steps and the measurement results from the positive steps are generally similar, although not necessarily the same.

3. Accuracy

[0130] FIG. 14 illustrates the correlation between double-layer capacitance measured using electrochemical impedance spectroscopy (EIS) and decay time measured using the step response capacitance measurement technique. In FIG. 14, x-axis represents the average double-layer capacitance (in pF per cell) measured for a nanopore chip using EIS. Y-axis represents the decay time measured for individual cells on a corresponding nanopore chip using SRCM technique, where the distribution of the decay time measured for individual cells on a nanopore chip is represented by a mean value and a standard deviation value. [0131] FIG. 14 shows that the Pearson correlation coefficient of the correlation between the average double-layer capacitance on a nanopore chip measured using EIS and the statistical mean value of the 50% positive decay time pos_50 (in blue) measured for individual cells on a corresponding nanopore chip measured using the SRCM technique is very close to 1 (about 0.987). FIG. 14 also shows that the Pearson correlation coefficient of the correlation between the average double-layer capacitance on a nanopore chip measured using EIS and the statistical mean value of the 75%) positive decay time pos_75 (in green) measured for individual cells on a corresponding nanopore chip measured using the SRCM technique is about 0.931. Thus, there is a very good correlation between the average double-layer capacitance measured using EIS and the 50%> or 75% positive decay time measured using the SRCM technique. The correlation may thus be used to determine the capacitance value based on the measured decay time.

4. Example decay for high capacitance

[0132] FIG. 15 illustrates an example step response capacitance measurement technique for measuring the capacitance of a double-layer capacitor with a higher capacitance (e.g., > 300 pF), according to certain embodiments. As described above, for a double-layer capacitor with a large capacitance value, the decay may be slow. As such, at the end of a positive step period, the voltage level on the double-layer capacitor may not have decayed to the actual positive baseline. Thus, the last measurements at the end of the period cannot be used as the baseline for determining when a specific percentage of decay has occurred, e.g., 75% or 50%>. In such a situation, the baseline from the hold period can be used instead. For example, the median of the last 30 sample points captured in the hold period may be used as the value for hold baseline 1520 as well as the default value for the baseline for determining the decay rate. [0133] To illustrate this example, for each positive (or negative) step, voltage levels 1570 on the working electrode may not have decayed to the actual positive baseline because of the slow decay (large decay time constant), as compared to voltage levels 1580 for a double-layer capacitor with a small capacitance value. Thus, the positive baseline 1560 measured at the end of the positive step period may be much higher than the actual positive baseline. If positive baseline 1560 is used as the baseline to adjust the data points, the resultant positive gain determined based on the adjusted data points may be much lower than the actual positive gain of the cell. As a result, the measured time for the voltage level on the working electrode to decay from the positive gain value to 75 % (shown as voltage level

1545) or 50% (shown as voltage level 1555) of the positive gain may be shorter than the actual 75% (or 50%) positive decay time. Thus, a large error may occur in the measurement results.

[0134] In some implementations, hold baseline 1520 may be used as the positive baseline for measuring double-layer capacitor with a large capacitance value without sacrificing the accuracy of the measurement. This is because, as described above, for a double-layer capacitor with a large capacitance value, the baseline shift may be relative small. Thus, each data point may be adjusted by subtracting the voltage level of hold baseline 1520 from the measured voltage level for each data point. The maximum voltage level 1530 among the adjusted data points in the positive step period may be used as the positive gain of the nanopore cell. The time it takes for the voltage level on the working electrode to decay from the positive gain value (voltage level 1530) to 75% of the positive gain (voltage level 1540) may be determined as the 75% decay time pos_75. The time it takes for the voltage level on the working electrode to decay from the positive gain value (voltage level

1530) to 50%) of the positive gain (voltage level 1550) may be determined as the 50%) decay time pos_50. The 75% decay time pos_75 and/or 50%> decay time pos_50 may then be used to more accurately determine the decay time constant x~rporeCdbi and/or the double-layer capacitance. 5. Flowchart

[0135] FIG. 16 is a flow chart 1600 illustrating an example method of step response capacitance measurement, according to certain aspects of the present disclosure. The method may be performed after the formation of a bilayer and/or a nanopore in the nanopore cell. In the example method, the capacitance of a double- layer capacitor formed between the electrolyte and a working electrode of the nanopore cell may be measured by measuring the decay of the voltage level on the working electrode through the nanopore, where a time constant of the decay may be proportional to the capacitance of the double-layer capacitor and the equivalent resistance of the nanopore.

[0136] At block 1610, an electrolyte may be added to a nanopore cell so that the electrolyte may be in contact with the working electrode of the nanopore cell located in a well of the nanopore cell. As described above, the electrolyte may include, for example, one or more of the following: lithium chloride (LiCl), sodium chloride (NaCl), potassium chloride (KC1), lithium glutamate, sodium glutamate, potassium glutamate, lithium acetate, sodium acetate, potassium acetate, calcium chloride (CaCk), strontium chloride (SrCk), Manganese chloride (MnCk), and magnesium chloride (MgCk).

[0137] At block 1620, a bilayer covering the well may be formed as described above with respect to, for example, FIGS. 1-3. The bilayer may separate the bulk electrolyte above the bilayer from the electrolyte within the well. A nanopore may also be formed in the bilayer as described above. The nanopore may form a path between the bulk electrolyte and the electrolyte within the well. The bilayer and the nanopore may be modeled as a bilayer capacitor and a pore resistor as described above with respect to, for example, FIGS. 6, 8, and 10.

[0138] Optionally, the working electrode may be connected to a voltage source at a first voltage level (e.g., V_pre) and a second voltage level may be applied to the electrolyte above the bilayer (e.g., Vu_q). Thus, the double-layer capacitor may be charged with the voltage across the capacitor equal to the difference between the first voltage level and the second voltage level (V_pre-Viiq). Subsequently, the working electrode may be disconnected from the voltage source at a first voltage level (e.g., V_pre), while the second voltage level may still be applied to the electrolyte above the bilayer. This will cause the voltage level on the working electrode to decay gradually. The second voltage level may be applied for a sufficient period of time (e.g., 30 seconds) for the voltage level on the working electrode to reach a steady state (baseline). In some implementations, a plurality of voltage levels may be measured on the working electrode at a plurality of time instants while the second voltage level is applied to the electrolyte. The plurality of voltage levels on the working electrode measured at the plurality of time instants may be used to determine a hold baseline as described above with respect to, for example, FIG. 13 and 15.

[0139] At block 1630, the double-layer capacitor formed at the interface between the electrolyte and the working electrode may be pre-charged. For example, the working electrode may be connected to a voltage source at a first voltage level (e.g., Vpre) and a second voltage level may be applied to the electrolyte above the bilayer (e.g., Vu_q). Thus, the double-layer capacitor may be charged with the voltage across the capacitor equal to the difference between the first voltage level and the second voltage level (Vpre-Vuq). Subsequently, the working electrode may be disconnected from the voltage source at a first voltage level (e.g., Vpre).

[0140] At block 1640, a step voltage signal may be applied to the bulk electrolyte as described above with respect to, for example, FIGS. 1 1-13 and 15. The step voltage signal may be a part of a square wave or a rectangular wave AC signal. The step voltage signal may be a positive step signal or a negative step signal. The step voltage signal may cause the voltage level at the working electrode to

increase/decrease instantaneously and then decay gradually.

[0141] At block 1650, a plurality of voltage levels may be measured on the working electrode at a plurality of time instants while the step voltage signal is applied to the bulk electrolyte. The measurement of the plurality of voltage levels may be performed as described above with respect to, for example, FIGS. 13 and 15. [0142] At block 1660, a time of decay of the voltage level on the working electrode may be determined based on the plurality of voltage levels on the working electrode measured at the plurality of time instants. For example, as described above with respect to, for example, FIGS. 13 and 15, the 75% decay time, 50% decay time, or 37 % (i.e., lie) decay time may be determined based on the plurality of voltage levels measured on the working electrode. As described, for large double-layer capacitors, the hold baseline may be used as the positive or negative baseline for determining the gain and decay time.

[0143] At block 1670, the capacitance of the double-layer capacitor may be determined based on the time of decay of the voltage level on the working electrode. For example, the capacitance of the double-layer capacitor may be determined based on the 37 % decay time (i.e., the decay time constant) because the decay time constant is proportional to the double-layer capacitor and the resistance of the nanopore. The capacitance of the double-layer capacitor may also be determined based on a correlation between the double-layer capacitance and the time of decay of the voltage level (e.g., 75% decay time, 50% decay time, or 37% decay time) as shown in FIG. 14.

[0144] It is noted that even though FIG. 16 describes the data processing as a sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the operations may be rearranged. An operation may have additional steps not included in the figure. Some operations may be optional, and thus may be omitted in various embodiments. Some operations described in one block may be performed together with operations at another block. For example, some operations may be performed in parallel.

Furthermore, embodiments of the methods may be implemented in hardware, software, firmware, middleware, microcode, hardware description languages, or any combination thereof.

B. Charge Titration Capacitance Measurement (CTCM)

[0145] As described above, the SRCM technique may be used to measure the double-layer capacitance after the formation of the nanopore. However, it may not be able to measure the double-layer capacitance at an early stage of the sequencing process, such as before the formation of the bilayer and the nanopore. According to certain aspects of this disclosure, a charge titration capacitance measurement technique may be used to measure the double-layer capacitance of individual cells at an early stage of the sequencing process, for example, at any time after an electrolyte (buffer) is applied to the cell to contact the working electrode.

[0146] In one example, after a liquid (e.g., a buffer or an electrolyte) is added to the well of a cell and is in contact with one surface of the working electrode at the bottom of the well, a voltage level may be applied to the buffer, for example, through a counter electrode. Another voltage level may be applied to the other surface of the working electrode through an electrical circuit. Thus, an initial voltage (potential difference) may be applied to the double-layer capacitor to store initial electric charges in the double-layer capacitor. After the initial charges are stored in the double-layer capacitor, a switching capacitor circuit may use a switching capacitor (e.g., the integrating capacitor) with a known capacitance value and initial voltage level to repeatedly charge or discharge the double-layer capacitor in each charge or discharge cycle. The charge or discharge can be achieved by alternately connecting the switching capacitor (Cmt) to a signal source with a known voltage level and to the working electrode. When the switching capacitor is connected to the signal source with the known voltage level, the switching capacitor may be charged or discharged to store a known number of charges. When the switching capacitor is connected to the working electrode, the charges may be redistributed between the switching capacitor and the double-layer capacitor such that the potential at a terminal of the switching capacitor that is connected to the working electrode and the potential at the working electrode are the same. Thus, if the initial voltage level at the terminal of the switching capacitor that is later connected to the working electrode is higher than the initial voltage level at the working electrode, after the connection, the switching capacitor may charge the double-layer capacitor. Otherwise, the switching capacitor may discharge the double-layer capacitor. [0147] In a simplified example, a double-layer capacitor Cdbi may have a capacitance of Cdbi and an initial voltage Vi across the double-layer capacitor Cdbi, and a switching capacitor Cint may have a capacitance of Cint and an initial voltage V₂ across the switching capacitor Cint. When the two capacitors are connected in parallel, the voltage across the two capacitors may become:

y _ CdblVl +CjntV2

³ c_dbi+c_int

Therefore, the voltage change on the double-layer capacitor after each charge redistribution is:

cdbl + ^cint If Cint is much smaller than cdbl, the voltage change AVmay be written as:

AV =— (V₂ - V .

cdbl

Thus, the rate of voltage change is proportional to ^²^. For example, if V₂ is zero

cdbl

(i.e., switching capacitor Cint is grounded after each charge redistribution), the double-layer capacitor will be discharged by switching capacitor Cint, and the voltage change on switching capacitor Cint for each discharge is:

AV = -— i.

cdbl

If V₂ is greater than Vi, the double-layer capacitor is being charged by switching capacitor Cint. By repeatedly charging or discharging the double-layer capacitor using a switching capacitor having a known capacitance and initial voltage level, and measuring the voltage change on the double-layer capacitance after certain number of charge or discharge cycles, the ratio between Cint and Cdbi may be determined.

[0148] If the charging/discharging cycles are performed at a certain rate (e.g., 1000 cycles per second), the rate at which Cdbi is charged or discharged may be proportional to Cint and the frequency / of the charging/discharging cycles. For example, if Cint is grounded after each charge redistribution, Cint may act as a resistive element with an impedance of l/(fa_nt) to ground. Thus, the decay of the voltage across the double-layer capacitor may have a time constant l~ZAw/(fcmt).

1. Circuits for charge titration

[0149] FIG. 17A illustrates an example configuration of a circuit 1700 in a cell during an example charge titration capacitance measurement, according to certain embodiments. Circuit 1700 may be a simplified electrical model of a cell before the bilayer and the nanopore are formed. Circuit 1700 may include a double-layer capacitor Cdbi 1702, a switching (integrating) capacitor Cint 1704, an ADC 1806, and switches 1708, 1710, and 1712. FIG. 17A shows the configuration of circuit 1700 after a voltage level Vu_q is applied to a liquid (buffer or electrolyte) that is in contact with the working electrode, where switches 1708, 1710, and 1712 are open. As descried above, the voltage level Vu_q can be applied to the liquid through the counter electrode. The voltage level on the working electrode VWE may be equal to Viiq. The voltage Vncap across switching capacitor Cint may be at any level, for example, equal to a pre-charge level V_pre.

[0150] FIG. 17B illustrates an example configuration of circuit 1700 for charging an integrating capacitor during a charge titration capacitance measurement, according to certain embodiments. In FIG. 17B, switch 1710 is closed, and thus the voltage Vncap across switching capacitor Cint may be charged to a level equal to the pre-charge level V_pre. The voltage level Vu_q may still be applied to the liquid and thus the voltage level VWE on the working electrode may still be equal to Vu_q.

[0151] FIG. 17C illustrates an example configuration of circuit 1700 for discharging an integrating capacitor during a charge titration capacitance measurement, according to certain embodiments. In FIG. 17C, switch 1710 is opened and switch 1708 is closed. Thus, the voltage level Vncap across switching capacitor Cint is equal to the voltage level VWE at the working electrode, which may be equal to Vu_q+AV due to the charge redistribution caused by the different voltage levels Vncap and VWE before switch 1708 is closed. The value of AV may be proportional to the ratio between the capacitance values of switching capacitor Cint 1704 and double-layer capacitor Cdbi 1702. [0152] After the charge redistribution shown in FIG. 17C, another charging cycle may begin. Switch 1708 may be opened and switch 1710 may be closed as shown in FIG. 17B to recharge switching capacitor Cint 1704. After switching capacitor Cint 1704 is recharged to V_pre, switch 1710 may be opened and switch 1708 may be closed as shown in FIG. 17C such that recharge switching capacitor Cint 1704 may charge double-layer capacitor Cdbi 1702 again.

[0153] The above-described charging cycle may be repeated, for example, tens, hundreds, or thousands of times to gradually charge or discharge double-layer capacitor Cdbi 1702. Vncap (and thus VWE) may be measured periodically, after certain number of cycles, or at a given time during the repeated charging cycles by opening switches 1708 and 1710 and closing switch 1712 to connect switching capacitor Cint 1704 to ADC 1706.

2. Simulation Results

[0154] FIG. 18 illustrates example simulation results of charge titration capacitance measurement for different capacitance ratios between the capacitance of double-layer capacitor Cdbi and the capacitance of switching capacitor Cint, according to certain embodiments. The voltage level on double-layer capacitor Cdbi may be increased gradually after each charging cycle. The time constant for the charging may be proportional to the ratio between the capacitance of double-layer capacitor Cdbi and the capacitance of switching capacitor Cint, and may be inversely proportional to the rate of the charging cycles. When the ratio between the capacitance of double-layer capacitor Cdbi and the capacitance of switching capacitor Cint is large, the measured voltage on switching capacitor Cint after charge redistribution may be close to a linear function of the number of charging cycles performed. A measured curve of voltage level on Cint may be matched to a simulated curve show in FIG. 18, and the corresponding ratio between the capacitance of double-layer capacitor Cdbi and the capacitance of switching capacitor Cint for the matched simulated curve may be the ratio between the double- layer capacitance to be measured and the capacitance of switching capacitor Cint used for the measurement. As one example, if a measured curve matches curve 1810 and the capacitance of switching capacitor Cint used for the measurement is about 67 fF, the capacitance of double-layer capacitor Cdbi can be determined to be about 150 pF. Similarly, if a measured curve matches curve 1820 and the capacitance of switching capacitor Cintused for the measurement is about 26 fF, the capacitance of double-layer capacitor Cdbi can be determined to be about 150 pF. 3. Flowchart

[0155] FIG. 19 is a flow chart 1900 illustrating an example method of charge titration capacitance measurement, according to certain aspects of the present disclosure. The method may be performed at an early stage of a sequencing process, for example, after an electrolyte is added to the cell but before the formation of a bilayer and/or a nanopore in the cell. In the example method, the capacitance of a double-layer capacitor formed between the electrolyte and a working electrode of the cell may be measured by performing repeated charging cycles to charge or discharge the double-layer capacitor with a small switching capacitor that is pre-charged to a known voltage level at the beginning of each charging cycle. The ratio between the capacitance of the double-layer capacitor and the capacitance of the switching capacitor can be determined based on the voltage change on the double-layer capacitor after a number of charging cycles.

[0156] At block 1910, an electrolyte may be added to a cell. The electrolyte may enter a well of a cell such that the electrolyte is in contact with a working electrode of the cell located in the well. As described above, the electrolyte may include, for example, one or more of the following: lithium chloride (LiCl), sodium chloride (NaCl), potassium chloride (KC1), lithium glutamate, sodium glutamate, potassium glutamate, lithium acetate, sodium acetate, potassium acetate, calcium chloride (CaCk), strontium chloride (SrCk), Manganese chloride (MnCk), and magnesium chloride (MgCk).

[0157] At block 1920, a first voltage level may be applied to the electrolyte. As described above, when a voltage is applied between the electrolyte and the working electrode, a double-layer capacitor may be formed at the interface between the electrolyte and the working electrode due to the electrical double-layer effect. Applying the first voltage level to the electrolyte may cause the working electrode to be pre-charged to the first voltage level.

[0158] At block 1930, a number of charging cycles may be performed. Each charging cycle may include setting a switching capacitor to a known initial voltage level (e.g., a second voltage level), and charging or discharging the double-layer capacitor by the switching capacitor pre-charged to the second voltage level.

[0159] More specifically, at block 1932, the switching capacitor may be connected to a voltage source at a second voltage level different from the first voltage level to pre-charge the witching capacitor to the second voltage level. For example, the switching capacitor may be connected to a voltage source V_pre using switch 1710. As described above, the second voltage level may be lower or higher than the first voltage level. For example, in some implementations, the second voltage level may be zero such that the switching capacitor may be completely discharged. In some implementations, the second voltage level may be higher than the first voltage level.

[0160] At block 1934, after the switching capacitor is set to the second voltage level, the switching capacitor may be disconnected from the voltage source, for example, by disconnecting switch 1710.

[0161] At block 1936, the switching capacitor may be connected to the working electrode (e.g., through switch 1708), thereby causing redistribution of charges stored in the switching capacitor and the double-layer capacitor as described above with respect to, for example, FIG. 17C. For example, if the second voltage is higher than the first voltage level, charges may be transferred from the switching capacitor to the double-layer capacitor to charge the double-layer capacitor, and the voltage level at the working electrode may be higher than the first voltage level. If the second voltage level is lower than the first voltage level, charges may be transferred to the switching capacitor from the double-layer capacitor to discharge the double-layer capacitor, and the voltage level at the working electrode may be lower than the first voltage level. [0162] At block 1938, after the charge redistribution, the switching capacitor may be disconnected from the working electrode, for example, by opening switch 1708.

[0163] If the switching capacitor is much smaller than the double-layer capacitor, the voltage level at the working electrode may change little after each charging cycle. A number of charging cycles, such as tens, hundreds, or thousands of cycles, may be performed before the voltage level at the working electrode (and the switching capacitor) is sampled and measured. If a large switching capacitor is used, the voltage level at the working electrode (and the switching capacitor) may be sampled and measured after one or more charging cycles.

[0164] At block 1940, the switching capacitor may be connected to a

measurement circuit to measure a third voltage level on the switching capacitor. For example, the switching capacitor may be connected to an ADC through switch 1712 shown in FIGS. 17A-17C. The third voltage level on the switching capacitor (and the working electrode) may be measured after the switching capacitor is connected to the working electrode but before the switching capacitor is connected to the voltage source at the second voltage level in the next charging cycle. For example, the third voltage level on the switching capacitor may be measured after block 1738. [0165] At block 1950, the capacitance of the double-layer capacitor may be determined based on the capacitance of the switching capacitor, the number of charging cycles performed before the measurement of the third voltage level, and the difference between the first voltage level and the third voltage level. As described above, the difference between the first voltage level and the third voltage level may be a function of the number of charging cycles performed before the measurement of the third voltage level and the ratio between the capacitance of the double-layer capacitor and the capacitance of the switching capacitor. Thus, the ratio between the capacitance of the double-layer capacitor and the capacitance of the switching capacitor may be determined based on the number of charging cycles performed before the measurement of the third voltage level and the difference between the first voltage level and the third voltage level. For example, as shown by line 1830 in FIG. 18, after 200 charging cycles, the ratio between the capacitance of the double-layer capacitor and the capacitance of the switching capacitor may be determined based on the measured voltage change (or a ratio of voltage change) on the switching capacitor (and the working electrode). For example, if the measured voltage change (or the ratio of voltage change) is at a value shown by point 1840, the ratio between the capacitance of the double-layer capacitor and the capacitance of the switching capacitor may be determined to be 1000. The actual capacitance of the double-layer capacitor may then be determined based on the known capacitance value of the switching capacitor, which may be designed and manufactured more precisely.

[0166] In some implementations, the operations at blocks 1930 and 1940 may be performed repeatedly for multiple iterations to more accurately determine the ratio between the capacitance of the double-layer capacitor and the capacitance of the switching capacitor and thus the capacitance of the double-layer capacitor. Each iteration providing a measurement of the capacitance. For example, rather than using one data point on the simulated curves shown in FIG. 18 (which may be susceptible to noise), a number of measurements and capacitance ratio

determination may be performed, and an average ratio may be used as the determined capacitance ratio. In some embodiments, as described above, a measured voltage change curve may be best matched to a simulated voltage change curve to determine the capacitance ratio.

[0167] It is noted that even though FIG. 19 describes the data processing as a sequential process, many of the operations can be performed in parallel or concurrently. In addition, the order of the operations may be rearranged. An operation may have additional steps not included in the figure. Some operations may be optional, and thus may be omitted in various embodiments. Some operations described in one block may be performed together with operations at another block. For example, some operations may be performed in parallel.

Furthermore, embodiments of the methods may be implemented in hardware, software, firmware, middleware, microcode, hardware description languages, or any combination thereof. VI. COMPUTER SYSTEM

[0168] Any of the computer systems mentioned herein may utilize any suitable number of subsystems. Examples of such subsystems are shown in FIG. 16 in computer system 10. In some embodiments, a computer system includes a single computer apparatus, where the subsystems can be the components of the computer apparatus. In other embodiments, a computer system can include multiple computer apparatuses, each being a subsystem, with internal components. A computer system can include desktop and laptop computers, tablets, mobile phones and other mobile devices. [0169] The subsystems shown in FIG. 20 are interconnected via a system bus 75.

Additional subsystems such as a printer 74, keyboard 78, storage device(s) 79, monitor 76, which is coupled to display adapter 82, and others are shown.

Peripherals and input/output (I/O) devices, which couple to I/O controller 71, can be connected to the computer system by any number of means known in the art such as input/output (I/O) port 77 (e.g., USB, FireWire^®). For example, I/O port 77 or external interface 81 (e.g. Ethernet, Wi-Fi, etc.) can be used to connect computer system 10 to a wide area network such as the Internet, a mouse input device, or a scanner. The interconnection via system bus 75 allows the central processor 73 to communicate with each subsystem and to control the execution of a plurality of instructions from system memory 72 or the storage device(s) 79 (e.g., a fixed disk, such as a hard drive, or optical disk), as well as the exchange of information between subsystems. The system memory 72 and/or the storage device(s) 79 may embody a computer readable medium. Another subsystem is a data collection device 85, such as a camera, microphone, accelerometer, and the like. Any of the data mentioned herein can be output from one component to another component and can be output to the user.

[0170] A computer system can include a plurality of the same components or subsystems, e.g., connected together by external interface 81, by an internal interface, or via removable storage devices that can be connected and removed from one component to another component. In some embodiments, computer systems, subsystem, or apparatuses can communicate over a network. In such instances, one computer can be considered a client and another computer a server, where each can be part of a same computer system. A client and a server can each include multiple systems, subsystems, or components.

[0171] Aspects of embodiments can be implemented in the form of control logic using hardware (e.g. an application specific integrated circuit or field

programmable gate array) and/or using computer software with a generally programmable processor in a modular or integrated manner. As used herein, a processor includes a single-core processor, multi-core processor on a same integrated chip, or multiple processing units on a single circuit board or networked. Based on the disclosure and teachings provided herein, a person of ordinary skill in the art will know and appreciate other ways and/or methods to implement embodiments of the present invention using hardware and a combination of hardware and software.

[0172] Any of the software components or functions described in this application may be implemented as software code to be executed by a processor using any suitable computer language such as, for example, Java, C, C++, C#, Objective-C, Swift, or scripting language such as Perl or Python using, for example,

conventional or object-oriented techniques. The software code may be stored as a series of instructions or commands on a computer readable medium for storage and/or transmission. A suitable non-transitory computer readable medium can include random access memory (RAM), a read only memory (ROM), a magnetic medium such as a hard-drive or a floppy disk, or an optical medium such as a compact disk (CD) or DVD (digital versatile disk), flash memory, and the like. The computer readable medium may be any combination of such storage or

transmission devices.

[0173] Such programs may also be encoded and transmitted using carrier signals adapted for transmission via wired, optical, and/or wireless networks conforming to a variety of protocols, including the Internet. As such, a computer readable medium may be created using a data signal encoded with such programs. Computer readable media encoded with the program code may be packaged with a compatible device or provided separately from other devices (e.g., via Internet download). Any such computer readable medium may reside on or within a single computer product (e.g. a hard drive, a CD, or an entire computer system), and may be present on or within different computer products within a system or network. A computer system may include a monitor, printer, or other suitable display for providing any of the results mentioned herein to a user.

[0174] Any of the methods described herein may be totally or partially performed with a computer system including one or more processors, which can be configured to perform the steps. Thus, embodiments can be directed to computer systems configured to perform the steps of any of the methods described herein, potentially with different components performing a respective steps or a respective group of steps. Although presented as numbered steps, steps of methods herein can be performed at a same time or in a different order. Additionally, portions of these steps may be used with portions of other steps from other methods. Also, all or portions of a step may be optional. Additionally, any of the steps of any of the methods can be performed with modules, units, circuits, or other means for performing these steps.

[0175] The specific details of particular embodiments may be combined in any suitable manner without departing from the spirit and scope of embodiments of the invention. However, other embodiments of the invention may be directed to specific embodiments relating to each individual aspect, or specific combinations of these individual aspects.

[0176] A recitation of "a", "an" or "the" is intended to mean "one or more" unless specifically indicated to the contrary. The use of "or" is intended to mean an "inclusive or," and not an "exclusive or" unless specifically indicated to the contrary. Reference to a "first" component does not necessarily require that a second component be provided. Moreover reference to a "first" or a "second" component does not limit the referenced component to a particular location unless expressly stated. The term "based on" is intended to mean "based at least in part on." [0177] All patents, patent applications, publications, and descriptions mentioned herein are incorporated by reference in their entirety for all purposes. None is admitted to be prior art.

Claims

Patent Claims

1. A method for measuring a capacitance of a double-layer capacitor in a sequencing cell, the method comprising: receiving an electrolyte by the sequencing cell such that the electrolyte is in contact with a working electrode of the sequencing cell located in a well of the sequencing cell; forming a nanopore in a membrane covering the well, the membrane separating the electrolyte; pre-charging the double-layer capacitor formed at the interface between the electrolyte and the working electrode; applying a step voltage signal to the electrolyte above the membrane or the working electrode; measuring a plurality of voltage or current levels on the working electrode or the electrolyte above the membrane at a plurality of time instants during a time period when the step voltage signal is applied; determining a decay time of voltage levels on the working electrode or the electrolyte above the membrane based on the plurality of voltage or current levels measured on the working electrode or the electrolyte above the membrane at the plurality of time instants; and determining the capacitance of the double-layer capacitor based on the decay time of the voltage levels on the working electrode or the electrolyte above the membrane.

2. The method of claim 1, wherein pre-charging the double-layer capacitor comprises: connecting the working electrode to a voltage source at a first voltage level; applying a second voltage level to the electrolyte above the membrane; and disconnecting the working electrode from the voltage source.

3. The method of claim 1, further comprising, before applying the step voltage signal to the electrolyte above the membrane: connecting the working electrode to a voltage source at a first voltage level; applying a second voltage level to the electrolyte above the membrane; and disconnecting the working electrode from the voltage source.

4. The method of claim 3, further comprising: measuring a plurality of hold voltage levels on the working electrode at a plurality of second time instants while the second voltage level is applied to the electrolyte above the membrane; and determining a baseline level based on the plurality of hold voltage levels, wherein determining the decay time of the voltage levels is further based on the baseline level.

5. The method of claim 1, wherein the step voltage signal is a part of an AC rectangular wave signal.

6. The method of claim 1, wherein the decay time include at least one of a 75% decay time, a 50% decay time, or a 37% decay time.

7. The method of claim 1, wherein determining the capacitance of the double-layer capacitor based on the decay time of the voltage levels on the working electrode further comprises: determining the capacitance of the double-layer capacitor based on a decay time constant or a correlation between double-layer capacitance and the decay time.

8. The method of claim 7, wherein the decay time constant is proportional to the capacitance of the double-layer capacitor and a resistance of the nanopore.

9. A method for measuring a capacitance of a double-layer capacitor in a sequencing cell, the method comprising: receiving an electrolyte in a well of the sequencing cell such that the electrolyte is in contact with a working electrode of the sequencing cell located in the well, the double-layer capacitor formed at an interface between the electrolyte and the working electrode; applying a first voltage level to the electrolyte to pre-charge the double-layer capacitor to the first voltage level; performing a plurality of charging cycles, wherein each charging cycle includes: setting a switching capacitor to a second voltage level that is different from the first voltage level; and charging or discharging the double-layer capacitor using the switching capacitor; measuring a third voltage level on the switching capacitor using a measurement circuit connected to the switching capacitor; and determining the capacitance of the double-layer capacitor based on a capacitance of the switching capacitor, a number of charging cycles performed before measuring the third voltage level, and a difference between the first voltage level and the third voltage level.

10. The method of claim 9, wherein setting the switching capacitor to the second voltage level includes: connecting the switching capacitor to a voltage source at the second voltage level to set the switching capacitor to the second voltage level; and disconnecting the switching capacitor from the voltage source before charging or discharging the double-layer capacitor using the switching capacitor.

11. The method of claim 9, wherein charging or discharging the double-layer capacitor using the switching capacitor includes: connecting the switching capacitor to the working electrode, thereby causing a redistribution of charges stored in the switching capacitor and the double-layer capacitor.

12. The method of claim 9, wherein the switching capacitor includes a capacitor associated with an integrating circuit for voltage measurements.

13. The method of claim 9, wherein a capacitance of the switching capacitor is less than 1/100 of the capacitance of the double-layer capacitor.

14. The method of claim 9, wherein the number of charging cycles performed before measuring the third voltage level is greater than 100.

15. The method of claim 9, wherein determining the capacitance of the double-layer capacitor includes: determining a ratio between the capacitance of the double-layer capacitor and the capacitance of the switching capacitor based on the number of charging cycles performed before measuring the third voltage level and the difference between the first voltage level and the third voltage level; and determining the capacitance of the double-layer capacitor based on the capacitance of the switching capacitor and the ratio between the capacitance of the double-layer capacitor and the capacitance of the switching capacitor.

16. The method of claim 9, further comprising: performing, for a plurality of iterations, operations including: performing the plurality of charging cycles; and connecting the switching capacitor to the measurement circuit to measure the third voltage level on the switching capacitor; and determining the capacitance of the double-layer capacitor based on the third voltage levels measured during the plurality of iterations.

17. A computer product comprising a computer readable medium storing a plurality of instructions for controlling a sequencing system to perform operations of any of the methods above.

18. A sequencing system or instrument comprising: the computer product of claim 17; and one or more circuits for executing instructions stored on the computer readable medium.