EP3663988A1 - Artificial neuron for neuromorphic chip with resistive synapses - Google Patents

Abstract

The invention relates to an artificial neuron for a neuromorphic chip comprising a synapse with resistive memory representative of a synaptic weight. The artificial neuron comprises a reading circuit, an integration circuit and a logic circuit interposed between the reading circuit and the integration circuit.The reading circuit (CL3) is configured to impose on the synapse an independent reading voltage of the membrane voltage and to provide an analog quantity representative of the synaptic weight. The logic circuit (LOG) is configured to generate from said analog quantity a pulse (Cmd_exci, Cmd_inhi) exhibiting said duration The integration circuit comprises an accumulator of synaptic weights at the terminals of which a membrane voltage is established (V _mem) and a comparator configured to emit a postsynaptic pulse in the event of a threshold being crossed by the membrane voltage. It also includes a current source (SI _exc, SI _inhi) controlled by said pulse to inject current into the synaptic weight accumulator during said duration.

Description

TECHNICAL AREA

The field of the invention is that of neuromorphic chips with artificial neural networks exploiting synapses with resistive memory.

PRIOR TECHNIQUE

• Les dendrites qui sont les entrées du neurone via lesquelles il reçoit des signaux d'excitation ou d'inhibition ;
• Le corps du neurone qui est le théâtre d'échanges ioniques à travers la membrane cellulaire ;
• L'axone, une longue extension du corps cellulaire, qui est l'unique sortie du corps.

A nerve cell, or neuron, can be broken down into several parts:

• The dendrites which are the inputs of the neuron via which it receives signals of excitation or inhibition;
• The body of the neuron which is the scene of ionic exchanges across the cell membrane;
• The axon, a long extension of the cell body, which is the only exit from the body.

Depending on the excitation or inhibition signals received at the dendrites, ions pass through the cell membrane. The imbalance of charges between the inside and the outside of the cell induces a voltage difference on either side of the membrane. We then speak of membrane voltage across a membrane capacity. When this membrane tension exceeds a certain level, that is to say when the cell is sufficiently excited, the neuron experiences a brutal exchange of ions. This results in a significant variation in the membrane tension. This variation, called action potential (“action potential” or “spike” in English), propagates along the axon, towards the synaptic buttons which constitute the outputs of the neuron. Seen from outside the cell, these "spikes" constitute the electrical activity of the neuron.

In a network of biological neurons, each neuron is connected to several thousand others via as many synapses. The term synapse designates the connection between the axon termination of a so-called presynaptic neuron and a dendrite of a so-called postsynaptic neuron. The influence of the presynaptic neuron on the postsynaptic neuron is balanced by the weight of the synapse which can be excitatory or inhibitory. In the first case, a presynaptic spike charges the membrane tension of the postsynaptic neuron and precipitates the generation of a postsynaptic action potential. In the second case, a Presynaptic "spike" has the effect of depolarizing the postsynaptic membrane and delaying the onset of a postsynaptic action potential.

Artificial neural networks are used in different fields of signal processing, such as data classification, image recognition or decision-making. They are inspired by the biological neural networks of which they imitate the functioning and are essentially composed of artificial neurons interconnected by synapses which can be implemented by resistive components whose conductance varies according to the voltage applied to their terminals.

Due to their high density and their non-volatile nature, these resistive components (memristors or RRAM) are ideal candidates for the implementation of synapses. The variable resistance of these components can be increased (so-called Reset operation) or decreased ( Set operation) if relatively high electrical quantities (voltage and / or current) are applied. If you simply want to read the value of their resistance without modifying it ( Read operation), you must apply relatively small electrical quantities.

The integration of resistive synapses often takes the form of a memory plane, which is called "synaptic plane", in which the synapses are arranged in a network with transverse lines and columns which makes it possible to connect a layer of input neurons. (presynaptic neurons) and a layer of output neurons (postsynaptic neurons). Each synapse has a synapse activation terminal and a propagation terminal for a synaptic signal. The terminals for activating synapses on the same line are linked together via a word line (or “Word-Line”), and the terminals for propagating synapses in the same column are connected between and connected to an artificial neuron via a bit line (or "Bit-Line"). A word line is used to inject a voltage pulse into the synapses of the corresponding line and the bit lines are the outputs of these synapses. In the presence of a presynaptic activation on a word line from a presynaptic neuron, each bit line propagates a current weighted by the value of the corresponding resistive memory towards a postynaptic neuron.

As shown in figure 1 (in the following figure x denotes the appended figure Fig. x), a resistive memory synapse generally takes the form of a 1T1R cell composed of a variable resistor M and an access transistor T used to regulate the writing currents and whose grid forms the synapse activation terminal. We have represented on the figure 1 an example of a synaptic plan with 1T1R cells comprising three word lines WL1-WL3, eight bit lines BL1-BL8 each intended to be connected to an output neuron and a source line (or “Source-Line”) SL connected to all synapses. The presence of a synapse transistor nevertheless limits the density of such a synaptic plane.

As shown in figure 2 , one can alternatively use cells 1S1R composed of a variable resistor M and a selector S having a behavior similar to a diode, or even to two diodes upside down. Each 1S1R cell is a dipole, the terminals of which constitute the activation and propagation terminals, and the synaptic plane is organized as shown in figure 2 where we took the example of a plan comprising three word lines WL1-WL3 and four bit lines BL1-BL4, and where each synapse is taken between a voltage on the corresponding word line and a voltage on its corresponding bit line.

A certain number of constraints weigh on the effective implementation of such an artificial neural network.

For example, if the organization of the synaptic plan has advantages (parallel calculations, density, pooling of pilots), it nevertheless has limitations. First of all, this organization offers an “all-to-all” connection according to which all the presynaptic neurons are connected via a synapse to all the postsynaptic neurons. However in certain cases, this “all-to-all” connection can lead to a mainly zero synaptic matrix and therefore to low energy efficiency. This organization also requires having to process zero weights at the risk of having a network composed mainly of parasitic synapses, making the analog integration of synaptic weights even more complex.

Another constraint is related to the classic implementation of an artificial neuron in the form of an integrative threshold neuron ("Integrate and Fire" in English). The principle of such an implementation is represented on the figure 3 . The contribution V _{spike_pre} of a presynaptic neuron is weighted by the value of the corresponding synaptic resistance R _synb and thus provides an excitation current I _synb . This current is injected into a capacitor C _mem which integrates the various stimulations over time. Membrane tension, modeled by the voltage V _mem at the terminals of the capacitance C _mem , is compared to a threshold V _threshold . When this threshold is exceeded by the membrane tension, a spike V _spike is emitted and the capacitor C _mem is discharged to reset the membrane tension, typically by resetting it to zero.

However according to Ohm's law, and as represented in figure 4 , the current I _synb which should depend only on the value of the resistor R _synb of the synapse actually depends on the value of the membrane voltage ${\mathrm{V}}_{\mathrm{same}}:{\mathrm{I}}_{\mathrm{synb}}=\frac{{\mathrm{V}}_{\mathrm{spike}-\mathrm{pre}}-{\mathrm{V}}_{\mathrm{same}}}{{\mathrm{R}}_{\mathrm{synb}}}\mathrm{.}$

This implies that the higher the voltage V _mem , the more the neuron is excited and likely to emit a spike, the less its afferent synapses have an effect on it. Such a phenomenon is problematic. Thus, in a classification layer for example, the neuron supposed to emit the most spikes sees its activity reduced in a greater proportion than that of the less active neurons. Consequently, the difference between this “winning” neuron and the other neurons is reduced.

Other constraints are linked to the characteristics of RRAM memories. An example of such an RRAM memory is the OxRAM memory which is composed of an insulator wedged between two layers of conductors. During a first stage of formation, a conductive wire grows from one of the conductors towards the other, thus reducing the total resistance of the dipole. Once this wire is formed, the writing actions act on its length to vary the resistance. A Set operation lengthens the wire and reduces the resistance, while a Reset operation has the opposite effect. Reading an OxRAM memory presents a difficulty, that of parasitic writing by gradually changing the value of the resistance over successive readings. To limit this risk, it is advisable to apply a maximum reading voltage of 100 mV. The smallness of this voltage greatly complicates the implementation of an integrative analog reading of these memories. Indeed, the reading voltage V _{spike_pre} limits the membrane voltage V _mem , because the membrane capacity C _mem is charged through the resistor R _synb on which V _{spike_pre} is applied. In other words, the membrane tension is worth at most the tension V _{spike_pre} . However, V _mem being an analog calculation element therefore subject in particular to problems of noise, technological variations, capacitive coupling, its voltage range cannot be reduced to a value as low as 100 mV without greatly increasing the sources of errors. Calculation.

It will also be noted that RRAMs devices often have a low resistance range (with low values of the order of kΩ) and that we can therefore be confronted with time constants of the cut R _syn - C _mem of l nanosecond order or less. However, it is not easy to generate reading pulses of less than 1 ns, except when using a specific circuit. The reading impulse must also be propagated over the entire width of the synaptic plane. The shorter this impulse, the less “clean” it is in the end. Finally, such a pulse is difficult to propagate in active analog circuits responsible for integrating the read current without being confronted with problems of bandwidth and / or distortion.

STATEMENT OF THE INVENTION

The invention aims to provide a solution to meet one and / or the other of the above constraints. To do this, it proposes an artificial neuron for a neuromorphic chip comprising a synapse with resistive memory representative of a synaptic weight, the artificial neuron comprising an integration circuit which comprises an accumulator of synaptic weights at the terminals of which a membrane tension is established. and a comparator configured to emit a postsynaptic pulse in the event of a threshold being crossed by the membrane voltage.

• un circuit de lecture configuré pour imposer à la synapse une tension de lecture indépendante de la tension de membrane et pour fournir une grandeur analogique représentative du poids synaptique, ladite grandeur analogique étant une durée ; et
• un circuit logique interposé entre le circuit de lecture et le circuit d'intégration, le circuit logique étant configuré pour générer à partir de ladite grandeur analogique une impulsion présentant ladite durée.

The neuron also includes:

• a reading circuit configured to impose on the synapse a reading voltage independent of the membrane voltage and to provide an analog quantity representative of the synaptic weight, said analog quantity being a duration; and
• a logic circuit interposed between the read circuit and the integration circuit, the logic circuit being configured to generate from said analog quantity a pulse having said duration.

• le circuit de lecture comprend un accumulateur de courant synaptique, au moins un comparateur de la tension aux bornes de l'accumulateur de courant synaptique avec un seuil pour fournir un résultat de comparaison et le circuit logique est configuré pour générer ladite impulsion à partir du résultat de la comparaison ;
• l'au moins un comparateur du circuit de lecture comprend un premier comparateur à un premier seuil et un deuxième comparateur à un deuxième seuil et le circuit logique est configuré pour déterminer un signe d'intégration en exploitant un signal représentatif d'un signe d'impulsion présynaptique et une information de signe de poids synaptique déterminée par celui des premier et deuxième comparateurs qui commute ;
• l'au moins un comparateur du circuit de lecture comprend un premier comparateur à un premier seuil et un deuxième comparateur à un deuxième seuil et le circuit logique est configuré de telle manière que la durée de ladite impulsion corresponde à une durée séparant le franchissement de l'un des seuils puis le franchissement de l'autre des seuils ;
• la synapse comprenant une mémoire de valeur absolue de poids synaptique et une mémoire de signe de poids synaptique, le circuit de lecture comprend un circuit de lecture binaire de la mémoire de signe de poids synaptique et un circuit de lecture analogique de la mémoire de valeur absolue de poids synaptique piloté par le circuit de lecture binaire.

The integration circuit comprises a current source controlled by said pulse to inject a current into the accumulator of synaptic weights during said duration. Some preferred but non-limiting aspects of this artificial neuron are as follows:

• the reading circuit comprises a synaptic current accumulator, at least one comparator of the voltage across the terminals of the synaptic current accumulator with a threshold to provide a comparison result and the logic circuit is configured to generate said pulse from the result of the comparison;
• the at least one comparator of the reading circuit comprises a first comparator at a first threshold and a second comparator at a second threshold and the logic circuit is configured to determine an integration sign by exploiting a signal representative of a sign of presynaptic pulse and synaptic weight sign information determined by which of the first and second comparators switches;
• the at least one comparator of the reading circuit comprises a first comparator at a first threshold and a second comparator at a second threshold and the logic circuit is configured in such a way that the duration of said pulse corresponds to a duration separating the crossing of the 'one of the thresholds then crossing the other of the thresholds;
• the synapse comprising a synaptic weight absolute value memory and a synaptic weight sign memory, the reading circuit comprises a binary reading circuit of the synaptic weight sign memory and an analog reading circuit of the absolute value memory of synaptic weight controlled by the binary reading circuit.

BRIEF DESCRIPTION OF THE DRAWINGS

• la figure 5 est un schéma de principe d'un neurone artificiel selon l'invention ;
• la figure 6 illustre une synapse excitatrice ou inhibitrice pouvant être utilisée dans le cadre de l'invention ;
• la figure 7 représente la réponse impulsionnelle de la synapse de la figure 6 ;
• les figures 8 et 9 fournissent des exemples d'intégration de la synapse de la figure 6 dans un plan synaptique ;
• les figures 10 et 11 fournissent un autre exemple de synapse excitatrice ou inhibitrice pouvant être utilisée dans le cadre de l'invention ;
• les figures 12 et 13 sont des schémas de neurones artificiels disposant d'un accumulateur de courant synaptique dans le circuit de lecture et d'un accumulateur de poids synaptiques dans le circuit d'intégration et pour lesquels la grandeur analogique représentative du poids synaptique fournie par le circuit de lecture au circuit d'intégration est une tension ;
• la figure 14 représente un autre exemple de neurone pour lequel la grandeur analogique est également une tension ;
• la figure 15 représente un neurone selon l'invention pour lequel la grandeur analogique est également une durée ;
• la figure 16 illustre un autre mode opératoire du neurone de la figure 15 ;
• les figures 17, 18 et 20 représentent des circuits de lecture d'un exemple de neurone pour lequel la grandeur analogique est un courant ;
• la figure 19 illustre une variante de réalisation des circuits de lectures des figures 17 et 18.

Other aspects, aims, advantages and characteristics of the invention will appear better on reading the following detailed description of preferred embodiments thereof, given by way of nonlimiting example, and made with reference to the following drawings on which, in addition to figures 1 to 4 already discussed previously:

• the figure 5 is a block diagram of an artificial neuron according to the invention;
• the figure 6 illustrates an excitatory or inhibitory synapse which can be used within the framework of the invention;
• the figure 7 represents the impulse response of the synapse of the figure 6 ;
• the figures 8 and 9 provide examples of integration of the synapse of the figure 6 in a synaptic plane;
• the figures 10 and 11 provide another example of an excitatory or inhibitory synapse which can be used in the context of the invention;
• the figures 12 and 13 are diagrams of artificial neurons with a synaptic current accumulator in the reading circuit and an accumulator synaptic weights in the integration circuit and for which the analog quantity representative of the synaptic weight supplied by the read circuit to the integration circuit is a voltage;
• the figure 14 represents another example of a neuron for which the analog quantity is also a voltage;
• the figure 15 represents a neuron according to the invention for which the analog quantity is also a duration;
• the figure 16 illustrates another operating mode of the neuron of the figure 15 ;
• the figures 17, 18 and 20 represent read circuits of an example of a neuron for which the analog quantity is a current;
• the figure 19 illustrates an alternative embodiment of the reading circuits of the Figures 17 and 18 .

DETAILED DESCRIPTION

With reference to the figure 5 , the invention relates to an artificial neuron NA for neuromorphic chip comprising a synapse with resistive memory representative of a synaptic weight.

The synapse has a terminal for activating the synapse and a terminal for propagating a synaptic signal. In the presence of a presynaptic activation applied to the activation terminal, the propagation terminal propagates a synaptic signal representative of the value of the resistive memory (ie the synaptic weight) towards the artificial neuron NA via a BL bit line.

The artificial neuron includes an integration circuit CI which includes an accumulator of synaptic weights ACC at the terminals of which a membrane voltage V _{mem is established} and a comparator COMP configured to emit a postsynaptic pulse SO in the event of crossing a threshold V _threshold by the membrane voltage V _mem .

The invention proposes to decouple the reading of the synaptic weight from its integration while avoiding digitizing the reading of the synaptic weight. The different constraints can thus be distributed according to whether they are inherited from resistive memory technology or from the functioning of the analog neuron. To do this, the invention proposes more particularly that the artificial neuron NA furthermore comprises a reading circuit CL configured to impose on the synapse a reading voltage independent of the membrane voltage V _mem and to supply to the integration circuit CI an analog quantity representative of the synaptic weight PSa.

The reading circuit CL thus makes it possible to impose on the synapse a reading voltage having an identical polarization for each reading regardless of the state of the membrane voltage V _mem . This reading circuit also makes it possible to impose a sufficiently low reading voltage on the synapse to avoid any risk of parasitic writing. The result of the reading, namely the analog quantity representative of the synaptic weight PSa, is transmitted to the integration circuit. As will be seen below, this quantity can take different forms, such as a voltage, a current, a charge or a duration for example. The integration circuit Cl, thus decoupled from the reading, can thus propose a wide range of voltage for the membrane voltage, independent of the specifications of the synapse.

We detail in the following implementations of resistive synapses which advantageously find application in the context of the invention. It will however be understood that the invention is not limited to these specific implementations.

We can indeed seek to have synapses which can be both excitatory and inhibitory, and which must therefore be capable of both injecting and drawing current from the neuron. Since the synapses are resistive here and the current they control depends on their resistance, two levels of synapse supply voltage are provided, a positive and a negative. The figure 6 provides an example of such an excitatory and inhibitory synapse, called synapse 2R1C. The synapse comprises an excitatory component CE and an inhibitory component CI arranged in series, with the propagation terminal Bp of the synapse as the midpoint, between a positive supply voltage V _read and a negative supply voltage -V _read . Each of these components can consist of n≥1 cells 1T1R or 1S1R depending on the encoding chosen (in the figure, the reference Select. Thus designates the access transistor or the selector of such cells 1T1R or 1S1R). If we use multivalued RRAMs, we can have n = 1. If on the other hand we use binary RRAMs, we predict as many cells as desired weight levels. We can also use synapses equal to -1, 0 or +1, in which case we can use binary RRAMs and n = 1. Anyway, reference is made in the following to the total resistance of the cells in parallel by writing R _exci and R _inhi to denote respectively the total resistance of the excitatory component CE and the total resistance of the inhibitory component CI. On the figure 6 , the capacity C _load is part of the reading circuit of a neuron according to a possible embodiment of the invention and is therefore shared by all the synapses of the same column.

The weight of the synapse is encoded as follows. If we want an exciting synapse, the resistance R _inhi is adjusted to its maximum resistance level, while the resistance R _exci (<R _inhi ) modulates the positive weight of the synapse. The lower the resistance R _exci , the greater the synaptic weight, since this results in a higher synaptic current. Conversely, if we want an inhibitory synapse, the resistance R _exci is adjusted to its maximum resistance level, while the resistance R _inhi (<R _exci ) modulates the negative weight of the synapse
By neglecting the effects of the access selectors or transistors, the diagram composed of the capacitance C _load and two resistors R _inhi and R _{exci is} similar to a damped resistive bridge. By applying the supply voltages V _read and -V _read , the potential V _load at the propagation terminal Bp is then gradually loaded as shown in the figure 7 . This figure 7 illustrates that the integration of the synaptic weight can only be effective over a period of integration PI corresponding to a reading pulse duration less than the time constant of the couple R _syn - C _load . In the contrary case indeed, with for example R _exci << R _inhi , one risks obtaining V _load = V _read whatever the value of R _exci .

This time constant is also even shorter when binary RRAMs are used to obtain multivalued synapses, the paralleling of these binary RRAMs leading in effect to a lower overall resistance. This problem can be circumvented by using a static reading of the synapse, that is to say reading a quantity depending on the weight of the synapse which is stabilized in the sense that it is independent of the duration. of a read pulse. The figure 7 shows indeed that in the static state reached with a sufficiently long reading pulse, the value of V _load can actually be modulated by the ratio between R _exci and R _inhi and therefore by playing with the number of devices in high resistance ( "High Resistive State" (HRS) or in low resistance ("Low Resistive State", LRS) on the excitatory and inhibitory component side.

Taking the example of a synapse composed of 8 OxRAM devices, 4 for the excitatory component and 4 for the inhibitory component. With LRS = 3kΩ, HRS = 800kΩ and C _load = 50 fF, coding on 9 weights (including zero weight) associated with time constants ranging from 1 ns to 250 ps can be obtained. A static reading offers more combinations (13 possible weights) and avoids having to generate short reading pulses. On the other hand, this static reading is more energy-consuming because of the “prolonged” access to the RRAM.

We have represented on figures 8 and 9 a possible organization of the synaptic plan with 2R1C synapses consistent with that of the figure 6 in the case where the components CE, CI are respectively based on 1T1R or 1S1R cells.

In the case 1T1R ( figure 8 ), the excitatory and inhibitory components participating in the same synapse have their activation terminals WL _i , WL _j pooled. Indeed, during the reading phase, the two components are read at the same time. This pooling is welcome because the synaptic plan is complicated by the need to have two distinct source line networks SL _a , SL _b which are used to distinguish cells with common BL and WL during the writing phase and to polarize the synapses in V _read or -V _read depending on which encode the excitatory or inhibitory component of their synapse during the read phase. In this configuration, the grids SL _a , SL _b are intended to remain polarized at ± V _read and the write pulses between the ground and V _DD are sent to the activation terminals WL _i , WL _j . It is noted that the access transistors of the inhibitory cells are reverse biased.

In the case of 1S1R ( figure 9 ), the exciting component of a synapse is taken between a word line WL _{i_exci} , WL _{j_exci} and a bit line Bl _u -Bl _x while the inhibiting component of the same synapse is taken between a word line WL _{i_inhi} , WL _{j_inhi} and the bit line Bl _u -Bl _x . Read pulses are sent simultaneously on the word lines WL _{i_exci} and WL _{i_inhi} corresponding to a presynaptic spike pertaining to line i. The word line WL _{i_exci} undergoes a pulse of the mass at V _read and the word line WL _{i_inhi} undergoes a pulse of the mass at -V _read .

One can also seek to implement negative spikes, namely presynaptic impulses which reverse the weight of the synapse which they trigger.

Using the example of the figure 9 , instead of sending positive slots on WL _{i_exci} , WL _{j_exci} and negative _slots on WL _{i_inhi} , WL _{j_inhi} , it is enough to reverse these polarizations. Thus, an inhibitory synapse injects a current into C _load and conversely an excitatory synapse withdraws it.

Using the example of the figure 8 , in case of negative spike it is also possible to reverse the polarization of two source lines SL _a , SL _b . This solution is not necessarily favorable, because it is long and costly in energy because these lines are common to the entire synaptic plane. As a variant, it is possible to use one pilot per source line and the polarization of which is switched from V _read to -V _read as a function of the sign of the presynaptic pulse to be processed. Consequently, it is no longer necessary to load and unload two complete planes but only the two source lines SL _a and SL _b which correspond to the synapses excited by the same presynaptic pulse. In this context, it is possible to move the voltage of these source lines only during playback and leave them to ground otherwise. Alternatively, these source lines SL _a and SL _b can change polarization (from V _read to -V _read and vice versa) only when necessary by coming to exploit for this purpose a memory in each source line pilot.

The figures 10 and 11 illustrate another exemplary embodiment for integrating an analog signed weight in a synaptic plane according to which an analog absolute value is associated with a binary sign by means of a synapse called in the following synapse absolute value + sign. The synaptic plane is then more classic, equipped with a single read voltage and having unidirectional read currents. According to this example, a certain number of binary RRAMs, a multivalued RRAM or a single binary RRAM in the event of binary synapse implements (s) the absolute value R _abs of synaptic weight while another RRAM, modeled by a resistance R _sign , is used binary to encode the sign of synaptic weight. This sign RRAM can advantageously be constituted by a triplet or a quintuplet of devices whose sign of the synapse is extracted by majority. The artificial neuron reading circuit then includes a binary reading circuit Cb of the synaptic weight sign memory M _sign and an analog reading circuit Ca of the synaptic weight absolute value memory M _abs , said analog reading circuit Ca being controlled by the binary read circuit Cb. The binary reading circuit Cb uses the sign of the presynaptic spike Sp and the sign of the synaptic weight M _sign to provide the analog reading circuit Ca with an integration sign Si indicating in which direction to integrate the analog current I _abs from the absolute value memory of synaptic weight M _abs . The direction of the analog current I _abs being always the same, its reversal in the event of a negative integration sign can be carried out with a simple current mirror as shown in figure 11 . On this figure 11 , if the sign of integration Si is 1, the current I _abs is injected into C _load . On the other hand, if the sign of integration Si is 0, the current I _abs is removed from C _load .

We have represented on figures 12 , 13 and 14 exemplary embodiments of an artificial neuron for which the analog quantity representative of the synaptic weight supplied by the read circuit to the integration circuit is a voltage. In certain embodiments, the analog magnitude representative of the synaptic weight can be a voltage independent of the duration of a reading pulse, the neurons performing a static reading of the synapse.

On the figures 12 and 13 , the reading circuit CL1 comprises a synaptic current accumulator C _load at the terminals of which a voltage V _{load is established} , this voltage corresponding to the analog quantity representative of the synaptic weight. The artificial neuron also comprises a bidirectional voltage follower circuit ST1, ST2 interposed between the read circuit CL1 and the integration circuit CI1.

The neuron works as follows. During a synapse read operation, the lower pole of C _load is connected to the virtual ground Gnd by a rst_bot switch. In a first phase of the read operation, C _load is first discharged by connecting its upper pole to the virtual ground using an rst_top switch, the read circuit being thus configured to discharge the accumulator from synaptic current C _load before imposing the reading voltage on the synapse. The reading of the synapse is then triggered by the opening of the rst_top switch. The current from the bit line BL is then accumulated in C _load , generating the read voltage V _load . Opening rst_bot provides a floating V _load voltage. The voltage follower ST1, ST2 is then configured to copy the membrane voltage V _mem to the lower terminal of C _load . Thus the voltage at the upper limit of C _{load is} worth the addition of V _mem and V _load . Then the voltage follower ST1, ST2 is configured to copy this addition of voltage to the upper limit of the membrane capacity C _mem thus providing the new membrane voltage which is compared to the spike emission threshold (s). (s).

The analog voltage addition proposed in the exemplary embodiments of Figures 11 and 12 allows a static reading of the 2R1C synapse. Dynamic reading is also possible provided that a sufficiently short reading pulse is generated. In these examples, moreover, the maximum stimulation is limited by the reading voltage of the RRAMs. We can then choose that such maximum stimulation alone can trigger a postsynaptic spike by a neuron whose membrane tension is at its resting potential. In which case, the voltage range of the membrane voltage V _mem is limited by the read voltage V _read . Alternatively, such a stimulation characteristic is not provided, and the membrane tension V _mem can be spread over a wider voltage range.

On the figure 12 , the voltage follower ST1 includes two operational amplifiers, one intended via the mem2bot switch to copy the membrane voltage to the lower terminal of C _load and the other intended via the top2mem switch to copy the voltage addition at the upper bound of C _mem .

On the figure 13 , the voltage follower ST2 includes a single operational amplifier in place of the two operational amplifiers used alternately on the figure 12 . In order to counteract the influence of the parasitic capacities of the switches during load transfers at the level of the input of the operational amplifier, an additional capacity C _{load_bis is provided} in parallel with the switch rst_bot.

It will be noted that the synapse absolute value + sign is adapted to the neurons of figures 12 and 13 .

On the figure 14 which also offers an analog quantity representative of the synaptic weight in the form of a voltage, the reading circuit CL2 comprises a switch R _ON / R _OFF having a first terminal B1 intended to be connected to the synapse via the bit line BL and a second terminal B2 connected to the integration circuit CI2. The integration circuit CI2 includes an integrator assembly connected to the second terminal and within which is mounted the synaptic weight accumulator C _mem .

The synapse is read as follows. Initially, the switch is left open (it has a resistance R _OFF in its blocked state), the voltage on the bit line V _BL stabilizes according to the weight of the synapse (we must therefore have R _OFF >> HRS ). In a second step, the switch is closed (it has a resistance R _ON in its passing state), the voltage V _BL is integrated by the integrator circuit, the time constant of which depends on R _ON and C _mem and not on the LRS of RRAMs. So we have R _ON > LRS. The neuron of the figure 14 thus performs a static reading of the synapse by means of the switch R _ON / R _OFF and integration of the voltage V _BL .

We have represented on figures 15 and 16 exemplary embodiments of an artificial neuron according to the invention for which the analog quantity representative of the synaptic weight supplied by the read circuit to the integration circuit is a duration. In these examples, the neuron comprises a logic circuit LOG interposed between the read circuit CL3 and the integration circuit Cl3, the logic circuit being configured to generate from said analog quantity a pulse Cmd_exci, Cmd_inhi having said duration. The integration circuit Cl3 for its part comprises a current source SI _exc , SI _inhi piloted by said pulse to inject a current into the accumulator of synaptic weights during said duration.

As for the neurons of figures 12 and 13 , the reading circuit CL3 of the neuron represented in figure 15 comprises a synaptic current accumulator C _load at the terminals of which a voltage V _{load is established} and an rst_load switch making it possible to discharge this accumulator before a reading operation of the synaptic weight. During a read operation, the C _load accumulator is charged by the synaptic current, more or less quickly depending on the synaptic weight. The duration of this loading can be estimated very simply using an analog comparator. On the figure 15 , we consider both excitatory and inhibitory synapses and we therefore provide two comparators Cp and Cn responsible for comparing the voltage across the synaptic current accumulator terminals C _load respectively to a first threshold Sp (for example positive) and to a second threshold Sn (for example negative). On the chronograms on the left on the figure 15 , the synapse is exciting and the voltage V _load at the terminals of the synaptic current accumulator C _load , after it has been discharged, gradually increases until it exceeds the first threshold Sp and toggle the output Comp_exci of the comparator Cp which thus provides loading time information which is representative of the synaptic weight.

The output Comp_exci of the comparator Cp is supplied to the logic circuit LOG interposed between the read circuit CL3 and the integration circuit CI3. This logic circuit is configured to generate, from the result of the comparison, a voltage pulse having said duration, in this case the Cmd_exci pulse in the example of the figure 15 .

The integration circuit CI2 for its part comprises a current source SI _exc controlled by said pulse Cmd_exci to inject a current into the accumulator of synaptic weights C _mem during said duration. The duration of this current injection therefore depends on the value of the synaptic weight, so that the final value of the membrane tension V _mem also depends on the value of the synaptic weight.

In the example shown with excitatory and inhibitory synapses, the integration circuit CI2 includes another current source SI _inhi piloted by a voltage pulse Cmd_inhi to draw current from the synaptic weight accumulator C _mem for a period representative of the synaptic weight.

The neuron of the figure 15 can also take into account the sign of the presynaptic pulse, this Signe_spike being supplied to the logic circuit LOG which is then configured to determine the integration sign from the spike sign and weight sign information synaptic synapse determined by which of the comparators Cp and Cn which switches. This logical and economical treatment of the spike sign allows, particularly in the case of 1T1R cells, to lighten the synaptic plane and its management. It will be noted that the synapse absolute value + sign is particularly suitable for this neuron.

An advantage of this embodiment is the reliability of zero weights. In the case of zero weight, all RRAMs devices in the synapse are at HRS. So, on the one hand, the time constant associated with a zero weight synapse is much more important than the others and, on the other hand, we will have Rexci ≈ Rinhi. It is therefore unlikely that the voltage V _load exceeds one of the two thresholds Sp, Sn not only because it will not have time but also because its final value risks being between the two thresholds. Consequently, the logic circuit LOG sees no switching at the output of the comparators Cp, Cn and does not trigger any charge injection on C _mem . A true zero weight which does not in any way modify the state of the neuron is thus implemented.

We have represented on the figure 16 chronograms illustrating another mode of operation of the neuron of the figure 15 according to which a double reading is operated so as to be insensitive to the switching times of the comparators Cp, Cn. In fact, according to the RRAM and transistor technologies used and the consumption of the comparators, it is possible that the switching time T _comp of the latter is not negligible compared to the charging time of the accumulator C _load . In this case, the duration of the pulse transmitted to the integration circuit may vary little with the value of R _syn , which may prove to be detrimental. In this other operating mode, the pulse is generated from two comparator switches, its duration corresponding to a duration separating the crossing of the threshold associated with one of the comparators then the crossing of the threshold associated with the other of the comparators . The switching times are thus applied to the start and end of the pulse and therefore do not affect its duration.

Thus, at first, the synapse is read in a direction long enough for V _load to start abutting on V _read or -V _read according to the sign of the synapse. Then, the polarization of the reading is reversed, the voltage V _load will therefore cross the potential difference from one polarization of V _read to the other and cross the two thresholds Sp, Sn in a time relative to the weight of the synapse. The logic circuit LOG is then configured to generate a voltage pulse between these two comparator switching operations.

We have represented on Figures 17 to 20 exemplary embodiments of an artificial neuron for which the analog quantity representative of the synaptic weight supplied by the read circuit to the integration circuit is a current. In the examples of Figures 17 and 18 , the reading circuit CL4, CL5 comprises a current conveyor which comprises an input port X intended to be connected to the synapse via the bit line, an input port Y intended to be subjected to a fixed voltage (by example ground) for the duration of access to the synapse and an output port Z connected to the integration circuit.

Such a current conveyor, based on an operational amplifier and two current mirrors, is such that the fixed voltage imposed on the input port Y is copied over the input port X and the current injected into the input port X is reproduced on the output port Z (with a sign inversion for the circuit of the figure 17 , without inversion of sign for the circuit of the figure 18 ). A fixed voltage being imposed on the Y port, we just slave the bit line voltage to this fixed voltage (it is thus independent of the membrane voltage of the neuron) and debit the synaptic current on the output port Z. This synaptic current is supplied to the integration circuit which will then carry out an analog integration.

avec K un facteur supérieur à 1 qui permet d'utiliser des impulsions de lecture de durée plus longues et donc plus adaptées au fonctionnement des éléments actifs sans pour autant faire saturer la capacité de membrane.The time constant R _syn -C _mem may however be too short for the operational amplifier and the current mirrors making up the current conveyor working properly. Thus, in an alternative embodiment, the current conveyor comprises, as shown in figure 19 , a current mirror configured to achieve a lowering of the current between the input port X and the output port Z. in this figure, we actually $I_{\mathit{OUT}}=\frac{-I_{\mathit{IN}}}{K},$

with K a factor greater than 1 which makes it possible to use reading pulses of longer duration and therefore more suited to the operation of the active elements without thereby saturating the membrane capacity.

In an alternative embodiment shown in the figure 20 , the neuron comprises a transmission gate T between the read circuit and the integration circuit. This gate makes it possible to dissociate the access time to the RRAMs and the integration time, which makes it possible to wait for the voltage on the input port X to stabilize before integrating the reading current and to play with a brief integration pulse without requiring a particularly reactive operational amplifier.

By the way, on this figure 20 the reading circuit CL6 advantageously comprises both the reversing current mirror of the reading circuit CL4 and the non-reversing current mirror of the reading circuit CL5 (these mirrors being able to effect a lowering of the current in accordance with the figure 19 ) and a selector S controlled by a signal Signe_spike representative of the sign of the presynaptic spike to select the output of one or other of these current mirrors.

The invention is not limited to the above-described artificial neuron, but extends to a neuromorphic chip comprising a plurality of synapses with resistive memory arranged in a network with transverse lines and columns. Each synapse has a propagation terminal, the propagation terminals of the synapses of the same column being linked together and connected to an artificial neuron according to the invention. The synapses can be excitatory or inhibitory synapses such as those presented above in connection with the figures 6 to 11 .

Claims (7)

Artificial neuron (NA) for a neuromorphic chip comprising a synapse with resistive memory representative of a synaptic weight,
the artificial neuron comprising an integration circuit (CI3) which comprises an accumulator of synaptic weights (C _mem ) at the terminals of which a membrane tension is established (V _mem ) and a comparator (COMP) configured to emit a postsynaptic pulse in membrane threshold crossing,
the artificial neuron being characterized in that it further comprises: a reading circuit (CL3) configured to impose on the synapse a reading voltage independent of the membrane voltage and to provide an analog quantity representative of the synaptic weight (PSa), said analog quantity being a duration; a logic circuit (LOG) interposed between the read circuit (CL3) and the integration circuit (CI3), the logic circuit being configured to generate from said analog quantity a pulse (Cmd_exci, Cmd_inhi) having said duration; and in that the integration circuit (CI3) comprises a current source (SI _exc , SI _inhi ) controlled by said pulse to inject a current into the synaptic weight accumulator during said duration. Artificial neuron according to claim 1, in which the reading circuit (CL3) comprises a synaptic current accumulator (C _load ), at least one comparator (Cp, Cn) of the voltage across the synaptic current accumulator with a threshold (Sp, Sn) for providing a comparison result and in which the logic circuit is configured to generate said pulse from the result of the comparison. Artificial neuron according to either of Claims 1 and 2, in which the at least one comparator of the reading circuit (CL3) comprises a first comparator at a first threshold and a second comparator at a second threshold and in which the logic circuit is configured to determine a sign of integration by exploiting a signal (Signe_spike) representative of a presynaptic pulse sign and a synaptic weight sign information determined by that of the first and second comparators which switches. Artificial neuron according to either of Claims 1 and 2, in which the at least one comparator of the reading circuit (CL3) comprises a first comparator at a first threshold and a second comparator at a second threshold and the logic circuit is configured such that the duration of said pulse corresponds to a duration separating the crossing of one of the thresholds then the crossing of the other of the thresholds. Artificial neuron according to one of claims 1 to 4, in which, the synapse comprising an absolute value memory of synaptic weight (M _abs ) and a synaptic weight sign memory (M _sign ), the reading circuit comprises a circuit of binary reading (Cb) of the synaptic weight sign memory and an analog reading circuit (Ca) of the synaptic weight absolute value memory M _abs controlled by the binary reading circuit. Neuromorphic chip comprising a plurality of resistive memory synapses arranged in a network with transverse lines and columns, each synapse having a propagation terminal of a synaptic signal, the propagation terminals of synapses of the same column being interconnected and connected to an artificial neuron according to one of claims 1 to 5. The neuromorphic chip of claim 6, wherein each synapse comprises an excitatory component and an inhibitory component connected in series by the propagation terminal of the synapse.

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