EP3550725B1

EP3550725B1 - Pipelined analog-to-digital converter

Info

Publication number: EP3550725B1
Application number: EP19166592.6A
Authority: EP
Inventors: Tzu-Chien Wu
Original assignee: MediaTek Inc
Current assignee: MediaTek Inc
Priority date: 2018-04-03
Filing date: 2019-04-01
Publication date: 2022-01-05
Anticipated expiration: 2039-04-01
Also published as: EP3550725A1; TW202005288A; TWI685209B; US20190305793A1; CN110350919A; CN110350919B; US10541704B2

Description

BACKGROUND OF THE INVENTION

Field of the Invention

The present invention relates to pipelined analog-to-digital converters comprising a multiplying digital-to-analog converter (MDAC).

Description of the Related Art

In electronics, an analog-to-digital converter (ADC) converts an analog input to generate digital representation of the analog input. To achieve high-speed conversion, a pipelined ADC architecture is proposed.
FIG. 1 depicts an example of a pipelined ADC 100, which includes an MDAC (multiplying digital-to-analog converter) 102, an M-bit ADC 104 and a Z-bit ADC 106. In phase Φ1, the analog input Vj is sampled by the MDAC 102 and the M-bit ADC 104. The M-bit ADC 104 outputs a digital signal Dj that includes control bits (b1, b0) to the MDAC 102. In phase Φ2, the MDAC 102 that receives the control bits (b1, b0) performs multiplication on the sampled analog input Vj based on the control bits (b1, b0) and thereby generates a multiplied signal Vj+1. The Z-bit ADC 106 is coupled to the MDAC 102 for conversion of the multiplied signal Vj+1. By converting the multiplied signal Vj+1, digital representation (including Z bits) of the analog input Vj is estimated by the Z-bit ADC 106. When the Z-bit ADC 106 is performing the conversion, the MDAC 102 and the M-bit ADC 104 proceeds to process the next sample of the analog input Vj. A pipelined architecture, therefore, is established. A high-speed ADC is provided.
The pipelined ADC 100, however, may result in low resolution.
FIG. 2 depicts the timing diagram of the pipelined ADC 100. After using phase Φ1 as the sampling phase for the analog input Vj, the digital signal Dj (including control bits b1 and b0) is generated by the M-bit ADC 104 and transferred to the MDAC 102. In phase Φ2, the MDAC 102 operates according to the control bits and, accordingly, performs multiplication on the analog input Vj sampled in phase Φ1. Considering the settling time required for the multiplied signal Vj+1 output by the MDAC 102, the Z-bit ADC 106 takes Ts/2 (phase Φ2) as a sampling phase. The Z-bit ADC 106 does not start the analog-to-digital conversion until the sampling phase (Φ2) for the multiplied signal Vj+1 is completed. The generation of all of the Z bits has to be finished in the following Ts/2. The resolution of the pipelined ADC 100 may be limited.
Considering a high-resolution requirement, a multi-stage architecture may be adopted. The Z bits generated by the Z-ADC 106 may be supplied to another MDAC (in the next stage) and, accordingly, the next stage outputs the lower bits to precisely represent the analog input Vj. However, the multi-stage architecture is complex.
A high-speed and high-resolution ADC with simple design is called for. There are trade-offs in ADC design.
The bit number of the MDAC 102 affecting the closed-loop bandwidth is limited in order to guarantee high-speed operation. Furthermore, mismatch between the sampling circuit of the MDAC 102 and the sampling circuit of the M-bit ADC 104 induces systemic redundancy errors. Thus, the high-resolution requirement has to be satisfied by other components except the MDAC 102, and the significant bit redundancy calibration is more important. The circuit size is large, and more power is consumed. A successive approximation register (SAR) ADC may be a solution for improving power efficiency. However, a SAR ADC with high resolution will slow down the conversion speed of the whole ADC structure.
US 8,643,529 and CHUN C LEE ET AL: "A SAR-Assisted Two-Stage Pipeline ADC" relate to an SAR assisted pipelined ADC with a current stage circuit (an SAR ADC and an MDAC) and a next stage circuit (an SAR ADC). TAI HUNG-YEN ET AL: "11.2 A 0.85fJ/conversion-step 10b 200kS/s subranging SAR ADC in 40nm CMOS" discloses a subranging SAR ADC wherein a small coarse ADC resolves the MSB bits and a detect-and-skip algorithm and an aligned switching technique are used to reduce the big fine DAC switching energy.

BRIEF SUMMARY OF THE INVENTION

A sub-range ADC assisted pipelined ADC is introduced.
A pipelined analog-to-digital converter in accordance with the invention is defined by claim 1.
In an exemplary embodiment, the first sub-range ADC generates the pre-estimated bits when the MDAC performs the multiplication. When the second sub-range ADC operates based on the pre-estimated bits, the MDAC and the first sub-range ADC may proceed to the next sample of the analog input.
In another exemplary embodiment, the first sub-range ADC comprises flash comparators, the control bits are generated by the flash comparators. The control bits generated by the flash comparators may be further used in the first sub-range ADC to shorten front-end successive approximation of the first sub-range ADC.
In an exemplary embodiment, the back-end successive approximation of the first sub-range ADC is performed when the MDAC performs the multiplication. When the second sub-range ADC performs back-end successive approximation to generate the first section of digital bits, the MDAC and the first sub-range ADC proceeds to the next sample of the analog input.
After generating the control bits, the first sub-range ADC may use the front-end successive approximation to calibrate errors due to the flash comparators. The first sub-range ADC may further use the back-end successive approximation to calibrate errors due to over-range redundancy. The second sub-range ADC may further use the back-end successive approximation to calibrate errors due to the pre-estimated bits. The second sub-range ADC may further use back-end redundant bit successive approximation to calibrate incomplete settling of successive approximation.
A detailed description is given in the following embodiments with reference to the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention can be more fully understood by reading the subsequent detailed description and examples with references made to the accompanying drawings, wherein:

FIG. 1 depicts an example of a pipelined ADC 100, which includes an MDAC (Multiplying digital-to-analog converter) 102, an M-bit ADC 104 and a Z-bit ADC 106;
FIG. 2 depicts the timing diagram of the pipelined ADC 100;
FIG. 3 depicts a pipelined ADC 300 in accordance with an exemplary embodiment of the disclosure, which uses sub-range SAR ADCs and is also named a sub-range SAR ADC assisted pipelined ADC;
FIG. 4 depicts the timing diagram of the pipelined ADC 300;
FIG. 5 depicts a pipelined ADC 500 in accordance with another exemplary embodiment of the disclosure; and
FIG. 6 depicts the capacitive data acquisition architecture of the SAR ADCs 504 and 506 in accordance with an exemplary embodiment of the disclosure.

DETAILED DESCRIPTION OF THE INVENTION

The following description shows exemplary embodiments carrying out the invention. This description is made for the purpose of illustrating the general principles of the invention and should not be taken in a limiting sense. The scope of the invention is best determined by reference to the appended claims.
FIG. 3 depicts a pipelined ADC 300 in accordance with an exemplary embodiment of the disclosure, which uses sub-range SAR ADCs and is also named a sub-range SAR ADC assisted pipelined ADC.
A SAR ADC (i.e. a successive approximation register analog-to-digital converter) may be implemented by a charge-redistribution technique. A capacitive data acquisition converter (C-DAC) may be used in a SAR ADC. A C-DAC comprises a weighted capacitor array for successive approximation (controlled according to a SAR logic) of a sampled analog input. During the successive approximation, the C-DAC feeds a residual signal to a comparator and the compared results are transferred to the SAR logic to arrange the successive approximation that the C-DAC performs. Through the successive approximation, digital representation of the analog input sampled by the C-DAC is obtained from the series of compared results. SAR ADCs are power efficient but may be time-consuming. The pipelined ADC 300 uses sub-range SAR ADCs as a solution.
As shown, the pipelined ADC 300 includes an MDAC (multiplying digital-to-analog converter) 302, an (M+Zl)-bit SAR ADC 304 and a Z-bit SAR ADC 306. The digital representation of an analog input Vj of the pipelined ADC 300 is formed by the output (the bits forming Dj plus Z1 bits) from the (M+Zl)-bit SAR ADC 304 and the output (Z2 bits) from the Z-bit SAR ADC 306. The two SAR ADCs 304 and 306 each responsible for partial conversion are sub-range SAR ADCs. Specifically, the Z1 bits estimated by the (M+Zl)-bit SAR ADC 304 is further transferred to and adopted by the Z-bit SAR ADC 306. The Z-bit SAR ADC 306 only needs to estimate the remaining (Z-Z1) bits. Not only benefiting from the low power consumption of SAR ADCs, the pre-estimated Z1 bits effectively speeds up the operation of the Z-bit SAR ADC 306.
The details of the operations of the pipelined ADC 300 are described in this paragraph. An analog input Vj is sampled by the MDAC 302 and the (M+Zl)-bit SAR ADC 304. The (M+Zl)-bit SAR ADC 304 outputs a digital signal Dj to the MDAC 302 as control bits. Based on the control bits, the MDAC 302 performs multiplication on the sampled analog input Vj and thereby generates a multiplied signal Vj+1 to be transferred to the Z-bit SAR ADC 306. When the MDAC 302 performs the multiplication to generate the multiplied signal Vj+1, the (M+Zl)-bit SAR ADC 304 proceeds to the estimation of the Z1 bits. The Z1 bits are regarded as pre-estimated bits and are transferred to the Z-bit SAR ADC 306. When the multiplied signal Vj+1 settles and is sampled by the Z-bit SAR ADC 306, the Z-bit SAR ADC 306 skips the estimation of the Z1 bits and directly starts the estimation of the remaining Z2 bits. In the Z-bit SAR ADC 306, only the successive approximation for obtaining the least significant Z2 bits is required. The higher Z1 bits are pre-estimated by the (M+Zl)-bit SAR ADC 304. When the Z-bit SAR ADC 306 is generating the least significant Z2 bits, the MDAC 302 and the (M+Zl)-bit SAR ADC 304 proceeds to the next sample of the analog input Vj. A pipelined architecture is established.
FIG. 4 depicts the timing diagram of the pipelined ADC 300. During the sampling phase (that samples the analog input Vj) of the MDAC 302, the (M+Zl)-bit SAR ADC 304 also samples the analog input Vj and, accordingly, generates the control bits (Dj, which may include M bits) for the MDAC 302. Then, the MDAC 102 performs multiplication on the sampled analog input Vj based on the control bits (Dj) and generates a multiplied signal Vj+1 to be sampled by the Z-bit SAR ADC 306. Specifically, in the phase for the MDAC 302 to perform the multiplication and for the Z-bit SAR ADC 306 to sample the multiplied signal Vj+1, the (M+Zl)-bit SAR ADC 304 is utilized to estimate the Z1 bits which are pre-estimated for the Z-bit SAR ADC 306. The pre-estimated Z1 bits are fed to the Z-bit SAR ADC 306. The Z-bit SAR ADC 306, therefore, skips the estimation of the Z1 bits and only needs to estimate the least significant Z2 bits. A high-resolution ADC is achieved without slowing down the conversion speed.
To further speed up the conversion, flash comparators may be adopted in the (M+Zl)-bit SAR ADC 304 for estimation of the most significant M bits. The high-speed flash comparators make the MDAC 300 getting the control bits (Dj) in time. However, to suppress the power consumption of flash comparators, the remaining Z1 bits are still estimated by successive approximation. Because the entire settling time of the multiplied signal Vj+1 can be utilized by the (M+Zl)-bit SAR ADC 304 to estimate the pre-estimated Z1 bits, the successive approximation of the Z1 bits does not drag the conversion speed down.
FIG. 5 depicts a pipelined ADC 500 in accordance with another exemplary embodiment of the disclosure. The pipelined ADC 500 includes an MDAC 502 and two SAR ADCs 504 and 506. An analog input Vj is converted to a digital representation of 10 bits. The SAR ADCs 504 and 506 each estimate 5 bits. As shown, the SAR ADC 506 is in a resolution of 8 (=3+5) bits, greater than 5 bits. The most significant 3 bits are pre-estimated by the SAR ADC 504. Referring to the SAR ADC 504, estimation of 5 bits are required. Flash comparators 508 are provided to rapidly estimate 2 MSBs (most significant bits) to be transferred to the MDAC 502 as control bits. As for the remaining 3 bits which are transferred to the SAR ADC 506 as the pre-estimated 3 bits, the estimation is performed by successive approximation based on the compared results of the flash comparators 508. Because of the high speed of the flash comparators 508, the MDAC 502 gets the required control bits in time. Because the successive approximation of the remaining 3 bits overlaps the operations of the MDAC 302, no additional phase is required for pre-estimating the MSBs of the SAR ADC 506. A high-speed 10-bit ADC is provided.
The SAR ADCs 504 and 506 may further include calibration design. The errors due to the flash comparators 508, over-range redundancy, pre-estimation of digital bits, and incomplete settling of successive approximation may be calibrated by designing the successive approximation structure.
FIG. 6 depicts the capacitive data acquisition architecture of the SAR ADCs 504 and 506 in accordance with an exemplary embodiment of the disclosure. The capacitors 602 are controlled by the flash comparators 508. The capacitors 604 are provided for calibration of the errors due to the flash comparators 508. Within the capacitors 606 for 3-bit pre-estimation, the capacitors 608 are provided for calibration of errors due to over-range redundancy. The SAR ADC 504 uses front-end successive approximation to estimate the bit controlling the capacitors 604, and uses back-end successive approximation to estimate the bits controlling the capacitors 606. The pre-estimated 3 bits are adopted in the control of the capacitors 610 of the SAR ADC 506. Thus, the front-end successive approximation of the SAR ADC 506 can be skipped. The SAR ADC 506 only needs to perform back-end successive approximation to estimate the bits controlling the capacitors 612. Within the capacitors 612 corresponding to the estimation of the least significant 5 bits of ADC conversion, the capacitors 614 are provided for calibration of errors due to the pre-estimated 3 bits, and the capacitors 616 are provided for calibration of errors due to the incomplete settling of the multiplied signal Vj+1 transferred from an MDAC. The redundancy error may be also suppressed by the incomplete settling calibration. The significant bit regarding redundancy calibration can be lowered. In some exemplary embodiments, some capacitors are provided to form the capacitors 612 for back-end redundant bit successive approximation to calibrate incomplete settling of successive approximation.
The pipelined ADCs of the disclosure further ease the offset errors from the SAR ADCs and the sampling time skew between the MDAC and the SAR ADC controlling the MDAC. Instead of digital timing calibration, the errors are compensated by SAR compensation.
In an example not covered by the claimed invention, the sampling circuit within the SAR ADC controlling the MDAC may be a replica of the sampling circuit within the MDAC, which also effectively reduces the timing skew due to the signal sampling.
In FIG. 6, the capacitive network formed by the capacitors 610 and the capacitive network formed by the capacitors 606 are similar. The difference is the size of the capacitors. The size of the capacitors 610 is 32 times the capacitors 606.
In other examples not covered by the claimed invention, the SAR ADCs adopted in the disclosed pipelined ADC may be changed to other type of sub-range ADC.
While the invention has been described by way of example and in terms of the preferred embodiments, it should be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements (as would be apparent to those skilled in the art). Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.

Claims

A pipelined analog-to-digital converter (300/500), comprising:
a multiplying digital-to-analog converter (302/502), configured to sample an analog input (Vj) and perform multiplication on the sampled analog input based on control bits (Dj);

a first sub-range analog-to-digital converter (304/504), configured to provide the multiplying digital-to-analog converter with the control bits (Dj); and

a second sub-range analog-to-digital converter (306/506), coupled to the multiplying digital-to-analog converter configured to convert a multiplied signal output (Vj+1) from the multiplying digital-to-analog converter,

wherein:
the first sub-range analog-to-digital converter (304/504) is configured to sample the analog input to generate the control bits (Dj) for the multiplying digital-to-analog converter (302/502) as well as pre-estimated bits (Z1) for the second sub-range analog-to-digital converter (306/506);

the second sub-range analog-to-digital converter (306/506) is configured to operate based on the pre-estimated bits (Z1) and thereby a first section (Z2) of digital bits are generated by the second sub-range analog-to-digital converter (306/506), wherein the second sub-range analog-to-digital converter (306/506) is configured to receive the pre-estimated bits (Z1) as most significant bits and, in response, to generate the first section (Z2) of digital bits as least significant bits;

a second section (Dj+Z1) of digital bits are provided by the first sub-range analog-to-digital converter (304/504); and

the first (Z2) and second (Dj+Z1) section of digital bits form digital bits representing the analog input, wherein:

the first section (Z2) of digital bits are least significant bits of the digital bits representing the analog input (Vj);

the second section (Dj+Z1) of digital bits are most significant bits of the digital bits representing the analog input (Vj);

the most significant bits of the digital bits are formed by the control bits (Dj) and the pre-estimated bits (Z1); and

the first sub-range analog-to-digital converter (304/504) and the second sub-range analog-to-digital converter (306/506) comprise successive approximation register analog-to-digital converters; and

the pre-estimated bits (Z1) are adopted in the second sub-range analog-to-digital converter (306/506) to skip successive approximation of the second sub-range analog-to-digital converter.
The pipelined analog-to-digital converter as claimed in claim 1, wherein:
the pipelined analog-to-digital converter is configured such that the generation of the pre-estimated bits (Z1) by the first sub-range analog-to-digital converter (304, 504) overlaps with the multiplication performed by the multiplying digital-to-analog converter (302/502).
The pipelined analog-to-digital converter as claimed in claim 2, configured such that:
when the second sub-range analog-to-digital converter (306/506) operates based on the pre-estimated bits (Z1), the multiplying digital-to-analog converter (302/502) and the first sub-range analog-to-digital converter (304/504) proceeds to the next sample of the analog input.
The pipelined analog-to-digital converter as claimed in claim 1, wherein:
the first sub-range analog-to-digital converter (304/504) is configured to use successive approximation to generate the pre-estimated bits (Z1).
The pipelined analog-to-digital converter as claimed in claim 4, wherein: the first sub-range analog-to-digital converter (304/504) is configured to use successive approximation to generate the control bits (Dj).
The pipelined analog-to-digital converter as claimed in claim 4, wherein:
the first sub-range analog-to-digital converter (304/504) comprises flash comparators (508); and

the flash comparators (508) are configured to generate the control bits (Dj).
The pipelined analog-to-digital converter as claimed in claim 6, wherein:
the control bits (Dj) are further used in the first sub-range analog-to-digital converter (304/504) to shorten successive approximation of the first sub-range analog-to-digital converter (304/504).
The pipelined analog-to-digital converter as claimed in any one of claims 4 to 7, wherein:
the successive approximation of the first sub-range analog-to-digital converter (304/504) is performed when the multiplying digital-to-analog converter (302/502) performs the multiplication.
The pipelined analog-to-digital converter as claimed in claim 8, configured such that:
when the second sub-range analog-to-digital converter (306/506) performs successive approximation to generate the first section of digital bits, the multiplying digital-to-analog converter (302/502) and the first sub-range analog-to-digital converter (304/504) proceeds to the next sample of the analog input.
The pipelined analog-to-digital converter as claimed in claim 7, wherein:
after generating the control bits (Dj), the first sub-range analog-to-digital converter is configured to use

the successive approximation to calibrate errors due to the flash comparators (508).
The pipelined analog-to-digital converter as claimed in any one of claims 4 to 10, wherein:
the first sub-range analog-to-digital converter is configured to further use the successive approximation to calibrate errors due to over-range redundancy.
The pipelined analog-to-digital converter as claimed in any one of claims 4 to 11, wherein:
the second sub-range analog-to-digital converter (306/506) is configured to further use the successive approximation to calibrate errors due to the pre-estimated bits (Z1).
The pipelined analog-to-digital converter as claimed in any one of claims 4 to 11, wherein:
the second sub-range analog-to-digital converter (306/506) is configured to further use redundant bit successive approximation to calibrate incomplete settling of successive approximation.