CN114553230A - Pipeline type analog-digital converter and analog-digital conversion method - Google Patents

Abstract

The pipelined analog-to-digital converter includes a plurality of converter circuitry. The plurality of converter circuitry is configured to convert an input signal into a plurality of digital codes in sequence. The plurality of converter circuitry includes first converter circuitry and second converter circuitry. The first converter circuitry is configured to convert the first signal into a first digital code of the plurality of digital codes and to generate a first residual signal based on the first signal and the first digital code. The second converter circuitry is configured to receive the first signal and the first digital code, quantize the first signal according to the first digital code to generate a second digital code of the plurality of digital codes, and generate a second residual signal according to the first residual signal and the second digital code.

Description

Pipeline type analog-digital converter and analog-digital conversion method

Technical Field

The present disclosure relates to a pipeline adc, and more particularly, to a pipeline adc with an extended amplification period and an adc method.

Background

The pipeline analog-digital converter can convert the input signal into corresponding digital codes in turn through multi-stage conversion. In the prior art, the operating period of each stage of conversion is fixed. As the clock frequency becomes higher, the time of one cycle becomes shorter. In order for the pipeline adc to correctly process the conversion result in a short period, some circuits (such as the residue amplifier) in the pipeline adc need to have high current. This leads to high overall power consumption and large overall circuit area.

Disclosure of Invention

In some embodiments, the pipelined analog-to-digital converter includes a plurality of converter circuitry. The plurality of converter circuitry is configured to convert an input signal into a plurality of digital codes in sequence. The plurality of converter circuitry includes first converter circuitry and second converter circuitry. The first converter circuitry is configured to convert the first signal into a first digital code of the plurality of digital codes and to generate a first residual signal based on the first signal and the first digital code. The second converter circuitry is configured to receive the first signal and the first digital code, quantize the first signal according to the first digital code to generate a second digital code of the plurality of digital codes, and generate a second residual signal according to the first residual signal and the second digital code.

In some embodiments, the analog-to-digital conversion method includes the following operations: converting the first signal into a first digital code, and generating a first residual signal according to the first signal and the first digital code; and quantizing the first signal according to the first digital code to generate a second digital code, and generating a second residual signal according to the first residual signal and the second digital code.

The features, implementations and functions of the present invention will now be described in detail with reference to the drawings.

Drawings

Fig. 1A is a schematic diagram of a pipeline analog-to-digital converter according to some embodiments of the disclosure;

FIG. 1B is a timing diagram illustrating the operation of the converter circuitry of FIG. 1A according to some embodiments of the disclosure;

FIG. 2 is a circuit schematic of the converter circuitry of FIG. 1A according to some embodiments of the present disclosure;

FIG. 3 is a schematic diagram of a sub-analog-to-digital converter circuit of FIG. 2 according to some embodiments of the disclosure;

FIG. 4 is a schematic diagram of a pipeline ADC according to some embodiments of the present disclosure; and

fig. 5 is a flow chart of an analog-to-digital conversion method according to some embodiments of the disclosure.

Detailed Description

All words used herein have their ordinary meaning. The definitions of the above-mentioned words in commonly used dictionaries are provided, and any use of the words discussed herein in this document is by way of illustration only and should not be construed as limiting the scope and meaning of the present disclosure. Likewise, the disclosure is not limited to the various embodiments shown in this specification.

As used herein, the term "couple" or "connect" refers to two or more elements being in direct physical or electrical contact with each other, or in indirect physical or electrical contact with each other, or the two or more elements operating or acting together. As used herein, the term "circuitry" may be a single system formed by at least one circuit (circuit), and the term "circuit" may be a device connected by at least one transistor and/or at least one active/passive component in a manner to process a signal.

As used herein, the term "and/or" includes any combination of one or more of the associated listed items. The terms first, second, third and the like are used herein to describe and distinguish between various components. Thus, a first component may also be referred to herein as a second component without departing from the spirit of the disclosure. For ease of understanding, similar components in the various figures will be designated by the same reference numerals.

Fig. 1A is a schematic diagram of a pipeline analog-to-digital converter 100 according to some embodiments of the disclosure, and fig. 1B is a timing diagram of operations of the converter circuitry 120[1] and the converter circuitry 120[2] of fig. 1A according to some embodiments of the disclosure.

The pipelined ADC 100 includes a sample-and-hold circuit 110, a plurality of converter circuitry 120[1] to 120[3], a clock generator circuit 130, and a digital correction circuit 140. The sample-and-hold circuit 110 samples the input signal VIN and outputs the sampled input signal VIN as a signal S1. In some embodiments, the sample-and-hold circuit 110 may be implemented by a switched capacitor circuit or a switched capacitor circuit.

The plurality of converter circuitry 120[1] -120 [3] sequentially converts the sampled input signal VIN (i.e., signal S1) into a plurality of digital codes D1[1] -D1 [3 ]. In detail, the converter circuitry 120[1] converts the signal S1 to generate a digital code D1[1], and generates a residual signal S2[1] according to the digital code D1[1] and the signal S1. Converter circuitry 120[2] receives signal S1, residual signal S2[1], and digital code D1[1 ]. Converter circuitry 120[2] quantizes signal S1 according to digital code D1[1] to produce digital code D1[2 ]. The converter circuitry 120[2] also generates a residual signal S2[2] from the digital code D1[2] and the residual signal S2[1 ]. The operation of converter circuitry 120[1] and associated converter circuitry 120[2] will be described later with reference to FIGS. 2 and 3. In some embodiments, the converter circuitry 120[3] may be, but is not limited to, a flash analog-to-digital converter circuit configured to generate a digital code D1[3] from the residue signal S2[2 ].

The clock generator circuit 130 is configured to generate a plurality of clock signals (not shown) to the sample-and-hold circuit 110 and the plurality of converter circuitry 120[1] 120[3 ]. Thus, the sample-and-hold circuit 110 and the converter circuitry 120[1] to 120[3] can perform the above operations in sequence according to the clock signals. The digital correction circuit 140 is used for combining a plurality of digital codes D1[1] -D1 [3] to generate a digital code DOUT. In some implementations, the digital correction circuit 140 may be used to correct offset errors (offset error) and/or gain errors (gain error) for each of the plurality of converter circuitry 120[1] -120 [3 ]. In some embodiments, the digital correction circuit 140 may be implemented by a plurality of digital logic circuits.

In some related technologies, a stage converter in a pipeline adc is configured to convert a previous stage residue signal to generate a corresponding digital code, and the digital code is only used to generate a corresponding residue signal in the stage converter. In these techniques, the converter needs to wait for the residue signal generated by the previous converter before performing the analog-to-digital conversion. Thus, the operational period of the analog-to-digital conversion of each stage of the converter is limited. In contrast to the above-described techniques, in some embodiments, the converter circuitry 120[2] is configured to convert the sampled input signal VIN (i.e., the conversion signal S1 instead of the residual signal S2[1]), and the converter circuitry 120[2] is further configured to directly receive the digital code D1[1 ]. With this arrangement, the converter circuitry 120[2] can advance into the amplification period to start generating the residual signal S2[2 ].

For example, as shown in FIG. 1B, when the converter circuitry 120[1] generates the residual signal S2[1] during the amplification period T1, the converter circuitry 120[2] may perform analog-to-digital conversion (i.e., generate the digital code D1[2]) and sample the residual signal S2[1] simultaneously during the sampling and decoding period T2. The converter circuitry 120[1] performs analog-to-digital conversion during the non-overlap period t 1. Compared to the converter circuitry 120[1], the analog-to-digital conversion by the converter circuitry 120[2] is performed within the sampling and decoding period T2 (rather than the non-overlap time between the sampling and decoding period T2 and the amplification period T3). Thus, the period of time for the converter circuitry 120[2] to perform the analog-to-digital conversion (i.e., generate the digital code D1[2]) can be relaxed, and the amplification period T3 can be advanced to generate the residual signal S2[2 ]. With this arrangement, the amplification period T3 can be longer than the amplification period T1. Thus, the current of the converter circuitry 120[2] can be reduced, thereby reducing the overall power and circuit area.

FIG. 2 is a circuit diagram of converter circuitry 120[1] and converter circuitry 120[2] of FIG. 1A according to some embodiments of the disclosure. The converter circuitry 120[1] includes a sub-analog-to-digital converter circuit 210 and a multiplying digital-to-analog converter (multiplying digital-to-analog converter) circuit 220. The sub analog-to-digital converter circuit 210 is used to convert the signal S1 to generate a digital code D1[1 ]. In some embodiments, the sub adc circuit 210 may be, but is not limited to, a flash adc circuit. The DAC circuit 220 processes the digital code D1[1] and the signal S1 to generate a residual signal S2[1 ].

In detail, the multiplying digital-to-analog converter circuit 220 includes a sub-digital-to-analog converter circuit 220-1, a subtractor circuit 220-2, and a residual amplifier circuit 220-3. The sub-DAC circuit 220-1 may convert the digital code D1[1] into the signal S21. The subtractor circuit 220-2 subtracts the signal S21 from the signal S1 to generate a signal S31. The residual amplifier circuit 220-3 may amplify the signal S31 to output a residual signal S2[1 ]. In some embodiments, the sub-DAC circuit 220-1, the subtractor circuit 220-2, and the residual amplifier circuit 220-3 may be implemented by switched capacitor circuits or switched capacitor circuits (not shown). Some switches of the switched capacitor circuit or the switched capacitor circuit are turned on during the sampling period to sample the input signal VIN to obtain the signal S1. The other switches of the switched capacitor circuit or switched capacitor circuit are turned on during the amplification period T1 to generate the residual signal S2[1 ].

Converter circuitry 120[2] includes sub-analog-to-digital converter circuit 230 and multiplying digital-to-analog converter circuit 240. The sub analog-to-digital converter circuit 230 receives the digital code D1[1] and the signal S1, and quantizes the signal S1 according to the digital code D1[1] to generate a digital code D1[2 ]. In some embodiments, the sub-adc circuit 230 may be, but is not limited to, a Successive Approximation Register (SAR) adc circuit. The DAC circuit 240 processes the digital code D1[2] and the residual signal S2[1] to generate a residual signal S2[2 ].

The multiplying digital-to-analog converter circuit 240 includes a sub-digital-to-analog converter circuit 240-1, a subtractor circuit 240-2, and a residual amplifier circuit 240-3. The sub-DAC circuit 240-1 may convert the digital code D1[2] into the signal S22. Subtractor circuit 240-2 is configured to subtract signal S22 from residual signal S2[1] to generate signal S32. The residual amplifier circuit 240-3 may amplify the signal S32 to output a residual signal S2[2 ]. In some embodiments, the sub-DAC circuit 240-1, the subtractor circuit 240-2, and the residual amplifier circuit 240-3 may be implemented by switched capacitor circuits or switched capacitor circuits (not shown). Some switches of the switched capacitor circuit or switched capacitor circuit are turned on during the sampling and decoding period T2 to sample the residual signal S2[1 ]. The other switches of the switched capacitor circuit or switched capacitor circuit are turned on during the amplification period T3 to generate the residual signal S2[2 ].

Fig. 3 is a schematic diagram of the sub-adc circuit 230 of fig. 2 according to some embodiments of the disclosure. In this example, the sub adc circuit 230 is a SAR adc circuit, which includes a comparator circuit 310, a control logic circuit 320, and a capacitor array circuit 330.

One end of the capacitor array circuit 330 receives a predetermined voltage VCM (or common mode voltage) through the switch SW during the sampling and decoding period T2, and the other end of the capacitor array circuit 330 samples the signal S1 to generate the signal ST. The comparator circuit 310 is used to compare the predetermined voltage VCM with the signal ST to generate the decision signal SD. The control logic circuit 320 performs a binary search algorithm based on the decision signal SD to control the capacitor array circuit 330 to sequentially switch to generate the bits of the digital code D1[2 ]. Before the control logic circuit 320 starts to switch the capacitor array circuit 330 (i.e., before the digital code D1[2] starts to be output), the capacitor array circuit 330 is further used to switch a portion of the capacitors (e.g., capacitors C3-C6) according to the digital code D1[1] to adjust the signal ST.

In detail, the capacitor array circuit 330 includes a switching circuit 331, a switching circuit 332, and a plurality of capacitors C1 to C6. The capacitance values of the capacitors C1-C6 are C, 2C, 4C, 8C, 16C and 32C in sequence. In other words, the capacitor C1 has a weight of 1, the capacitor C2 has a weight of 2, …, and the capacitor C6 has a weight of 32. In some embodiments, the plurality of capacitors C3-C6 with higher weight values correspond to Most Significant Bits (MSBs), and the plurality of capacitors C1-C2 with lower weight values correspond to Least Significant Bits (LSBs).

The switching circuit 331 includes a plurality of switches for selectively transmitting a signal S1, a reference voltage VREF1 or a reference voltage VREF2 (e.g., a ground voltage or a negative reference voltage) to a plurality of capacitors C3-C6 according to a plurality of bits of the digital code D1[1 ]. The switching circuit 332 includes a plurality of switches for selectively transmitting the signal S1, the reference voltage VREF1 or the reference voltage VREF2 to the plurality of capacitors C1-C2 according to the control of the control logic circuit 320 (i.e., according to the bits of the digital code D1[2 ]). In other words, the plurality of capacitors C3-C6 are controlled by digital code D1[1] (which is from the previous stage of converter circuitry), the plurality of capacitors C1-C2 are controlled by digital code D1[2] (which is from the present stage of converter circuitry), and the weight value corresponding to each of the plurality of capacitors C3-C6 is higher than the weight value corresponding to each of the plurality of capacitors C1-C2. Thus, before the control logic circuit 320 starts to switch the capacitor array circuit 330, the level of the signal ST can be adjusted in advance according to a plurality of bits (in this case, 4 bits) of the digital code D1[1 ].

In the above-mentioned fig. 1A to 3, 3 converter circuit systems 120[1] to 120[3] are taken as examples, but the present disclosure is not limited thereto. In other embodiments, the pipeline ADC 100 may include more converter circuitry, and the arrangement of the converter circuitry is similar to that of the converter circuitry 120[2 ]. Fig. 3 illustrates an example of a SAR adc circuit, but the disclosure is not limited thereto. Various sub-ADC circuits 230 capable of pre-adjusting signal levels according to the digital code D1[1] are all covered by the present application.

Fig. 4 is a diagram of a pipeline adc 400 according to some embodiments of the disclosure. For example, the pipelined ADC 400 further includes converter circuitry 120[4] coupled between the converter circuitry 120[2] and the converter circuitry 120[3 ]. The converter circuitry 120[4] generates a digital code D1[4] from the residue signal S2[1], and a residue signal S2[3] from the digital code D1[4] and the residue signal S2[2 ]. It should be appreciated that converter circuitry 120[4] is arranged in a manner similar to converter circuitry 120[2 ]. For example, in converter circuitry 120[4], a sub-analog-to-digital converter circuit (e.g., sub-analog-to-digital converter circuit 230) quantizes the previous residual signal S2[1] from the first two converter circuitry 120[1] according to the digital code D1[2] to produce digital code D1[4 ]. Similarly, in converter circuitry 120[4], a multiplying digital-to-analog converter circuit (e.g., multiplying digital-to-analog converter circuit 240) processes digital code D1[2] and residual signal S2[2] to produce residual signal S2[3 ].

For easy understanding, the operations of the above embodiments are described by taking a single-ended circuit as an example, but the present disclosure is not limited thereto. It should be understood that the above embodiments may also be implemented by differential circuits. In other words, the pipeline adc 100 (or the pipeline adc 400) implemented by a single-ended circuit or a differential circuit is also within the scope of the present disclosure.

Fig. 5 is a flow chart of an analog-to-digital conversion method 500 according to some embodiments of the disclosure. In some embodiments, the analog-to-digital conversion method 500 may be performed by, but is not limited to, the pipelined analog-to-digital converter 100 of FIG. 1A or the pipelined analog-to-digital converter 400 of FIG. 4.

In operation S510, the first signal is converted into a first digital code, and a first residual signal is generated according to the first signal and the first digital code. For example, the first signal may be the sampled input signal VIN (i.e., the signal S1) in fig. 1A and 4 or the residual signal S2[1] of fig. 4.

In operation S520, the first signal is quantized according to the first digital code to generate a second digital code, and a second residual signal is generated according to the first residual signal and the second digital code.

The above descriptions of the operations S510 and S520 can refer to the above embodiments, and thus are not repeated. The operations of the analog-to-digital conversion method 500 are merely examples and need not be performed in the order of the examples. The various operations of the analog-to-digital conversion method 500 may be added, replaced, omitted, or performed in a different order as appropriate without departing from the scope and manner of operation of the embodiments herein. Alternatively, one or more of the operations under the analog-to-digital conversion method 500 may be performed simultaneously or partially simultaneously.

In summary, the pipeline adc and the adc method in some embodiments of the disclosure can relax the operation time limit of the adc and extend the amplification time period for generating the residual signal. Therefore, certain power and circuit area can be saved.

Although the embodiments of the present invention have been described above, these embodiments are not intended to limit the present invention, and those skilled in the art can apply variations to the technical features of the present invention according to the contents of the present invention, which may fall within the scope of the patent protection sought by the present invention.

Description of reference numerals:

100. 400: pipeline type analog-digital converter

110: sample-and-hold circuit

120 < 1 >, 120 < 2 >, 120 < 3 >, 120 < 4 >: converter circuit system

130: clock pulse generator circuit

140: digital correction circuit

210. 230: sub-analog-to-digital converter circuit

220. 240: multiplying digital-to-analog converter circuit

220-1, 240-1: sub-digital-to-analog converter circuit

220-2, 240-2: subtractor circuit

220-3, 240-3: residual amplifier circuit

310: comparator circuit

320: control logic circuit

330: capacitor array circuit

331. 332: switching circuit

500: analog-to-digital conversion method

C1-C6: capacitor with a capacitor element

C. 2C, 4C, 8C, 16C, 32C: capacitance value

D1[1] -D1 [4], DOUT: digital code

S1, S2, S3, S21, S22, S31, S32, ST: signal

S2[1], S2[2], S1[3 ]: residual signal

S510, S520: operation of

SD: decision signal

ST: signal

SW: switch with a switch body

T1, T3: amplification period

T2: sampling and decoding period

t 1: non-overlapping time period

VCM: predetermined voltage

VIN: input signal

VREF1, VREF 2: reference voltage

Claims (10)

1. A pipelined analog-to-digital converter comprising:

a plurality of converter circuitry to convert an input signal into a plurality of digital codes in sequence, wherein the plurality of converter circuitry comprises:

first converter circuitry to convert a first signal to a first one of the plurality of digital codes and to generate a first residual signal based on the first signal and the first digital code; and

second converter circuitry to receive the first signal and the first digital code, to quantize the first signal according to the first digital code to generate a second digital code of the plurality of digital codes, and to generate a second residual signal according to the first residual signal and the second digital code.

2. The pipelined adc of claim 1, wherein the first signal is a corresponding one of the input signal or a previous residual signal, and the previous residual signal is a residual signal generated by the first two of the plurality of converter circuitry at the second converter circuitry.

3. The pipelined ADC of claim 1, wherein the second converter circuitry comprises a successive-approximation register ADC circuit configured to quantize the first signal according to the first digital code to generate the second digital code.

4. The pipelined analog-to-digital converter of claim 1, wherein the second converter circuitry comprises:

a sub analog-to-digital converter circuit for quantizing the first signal according to the first digital code to generate the second digital code; and

the multiplying digital-to-analog converter circuit is used for generating the second residual signal according to the second digital code and the first residual signal.

5. The pipelined ADC of claim 4, wherein the sub-ADC circuit comprises:

a comparator circuit for comparing the second signal with a predetermined voltage to generate a decision signal;

a control logic circuit for generating the second digital code according to the decision signal; and

the capacitor array circuit is used for generating the second signal according to the first digital code and the second digital code.

6. The pipelined ADC of claim 5, wherein the capacitor array circuit comprises a first plurality of capacitors controlled by the first digital code and a second plurality of capacitors controlled by the second digital code, and wherein each of the first plurality of capacitors has a higher weight value than each of the second plurality of capacitors.

7. The pipelined ADC of claim 5, wherein the capacitor array circuit is configured to adjust a level of the second signal according to the first digital code before the control logic circuit generates the second digital code.

8. The pipelined adc of claim 1, wherein the first converter circuitry generates the first residual signal during a first amplification period, the second converter circuitry generates the second residual signal during a second amplification period, and the second amplification period is longer than the first amplification period.

9. The pipelined adc of claim 1, wherein the second converter circuitry generates the second digital code and samples the first residual signal during a same time period.

10. An analog-to-digital conversion method comprising:

converting the first signal into a first digital code, and generating a first residual signal according to the first signal and the first digital code; and

the first signal is quantized according to the first digital code to generate a second digital code, and a second residual signal is generated according to the first residual signal and the second digital code.

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