EP3510720A1 - Récupération d'horloge et de données dans des systèmes de transmission pam-4 - Google Patents

Récupération d'horloge et de données dans des systèmes de transmission pam-4

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Publication number
EP3510720A1
EP3510720A1 EP16775635.2A EP16775635A EP3510720A1 EP 3510720 A1 EP3510720 A1 EP 3510720A1 EP 16775635 A EP16775635 A EP 16775635A EP 3510720 A1 EP3510720 A1 EP 3510720A1
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EP
European Patent Office
Prior art keywords
amplitude
polarity
bit
amplitude difference
analog data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP16775635.2A
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German (de)
English (en)
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EP3510720B1 (fr
Inventor
Nebojsa Stojanovic
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Huawei Technologies Co Ltd
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Huawei Technologies Co Ltd
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Publication of EP3510720A1 publication Critical patent/EP3510720A1/fr
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Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0334—Processing of samples having at least three levels, e.g. soft decisions
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/06—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/06—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
    • H04L25/061—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset
    • H04L25/063—Setting decision thresholds using feedback techniques only
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/06—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection
    • H04L25/061—Dc level restoring means; Bias distortion correction ; Decision circuits providing symbol by symbol detection providing hard decisions only; arrangements for tracking or suppressing unwanted low frequency components, e.g. removal of dc offset
    • H04L25/066—Multilevel decisions, not including self-organising maps

Definitions

  • the present invention relates to an apparatus and method for recovering clock and data from an M-level signal of a receiver in a transmission system such as - but not limited to - a fiber optical transmission system with direct detection optical receivers.
  • intensity modulation is a form of modulation, in which the optical power output of a source is varied in accordance with some characteristic of the modulation signal.
  • the envelope of the modulated optical signal corresponds to the modulating signal in the sense that the instantaneous power of the envelope is an envelope of the characteristic of interest in the modulation signal.
  • Recovery of the modulating signal is usually achieved by direct detection (DD) through a photo-detector.
  • Next-generation ultra-high-speed short-reach optical fiber links will utilize small, cheap and low power consumption transceivers. All those requirements are mainly imposed due to the limited space of data center equipment.
  • the transceivers shall support intra- and inter-data center connections from a few hundred meters up to several tens of kilometers, respectively.
  • Data centers are facilities that store and distribute the data on the Internet. With an estimated number of more than 100 billion of web pages on over 100 million websites, it is clear that those data centers shall be adapted to contain a huge amount of data. With almost two billion users accessing all these websites, including a growing amount of high bandwidth video, it is hard to comprehend how much data is being uploaded and downloaded every second on the Internet.
  • a data center as defined in the ANSI/TIA EIA-942 standard "Telecommunications Infrastructure Standard for Data Centers", is a building or portion of a building whose primary function is to house a computer room and its support areas.
  • the main functions of a data center are to centralize and consolidate information technology (IT) resources, house network operations, facilitate e-business and to provide uninterrupted service to mission- critical data processing operations.
  • Data centers can be part of an enterprise network, a commercial venture that offers to host services for others or a co-location facility where users can place their own equipment and connect to the service providers over the building's connections.
  • Data centers may serve local area networks (LANs) or wide area networks (WAN) and may be comprised of switches connecting user devices to server devices and other switches connecting server devices to storage devices.
  • LANs local area networks
  • WAN wide area networks
  • a preferred solution may be to transmit 100 Gbit/s per wavelength, which is very challenging when a very cheap solution is required.
  • a coherent approach is out of scope as it requires high power and expensive devices. Therefore, IM and DD schemes are preferred.
  • the mature on-off keying modulation format, widely used in non-coherent systems, has been also investigated for so-called 100-G applications at 100 Gbit/s per wavelength speed. However, such a solution would require expensive high-bandwidth optics and electronics.
  • DSP digital signal processing
  • DB-PAM-4 duo-binary 4-level pulse amplitude modulation
  • DMT discrete multi-tone modulation
  • CAP carrier-less amplitude and phase modulation
  • DMT and CAP require transmitter and receiver DSP blocks and are not considered seriously for cheap transceivers.
  • PAM-4 format is remaining as one option since a transmitter (Tx) does not require a digital-to-analog converter (DAC).
  • ADC analog-to-digital converter
  • BER bit error rate
  • FEC forward error correction
  • Fig. 1 shows a schematic block diagram of a conventional IM/DD-based PAM-4 transmission system 100.
  • a transmission PAM-4 signal (Tx PAM-4) is FEC encoded by an encoder (Tx FEC) and equalized by an equalizer (Tx EQ) at the transmitter side, for example, by using a simple analog equalizer (pre-emphases), amplified by a modulator driver (MD) and converted in the optical domain by a modulator (MOD) and a local oscillator laser (LO).
  • MD modulator driver
  • MOD modulator
  • LO local oscillator laser
  • the obtained optical signal is transmitted over a multimode fiber (MMF) or a single mode fiber (SMF) and detected by using a photo-diode (PD).
  • MMF multimode fiber
  • SMF single mode fiber
  • the obtained electrical signal is equalized (Rx EQ), for example, by a continuous-time linear equalizer (CTLE) or a multi-tap finite impulse response filter (FIR).
  • a subsequent clock recovery (CR) block uses signals before and after a 2-bit ADC to extract clock from the received signal.
  • Rx FEC FEC decoder
  • the BER of an obtained PAM-4 signal (Rx PAM-4) at the receiver output should be below some predefined threshold.
  • the architecture of Fig. 1 is a simple and cheap solution for an optical transmission system. All blocks can operate at high speed and the clock recovery (CR) block can be kept simple. However, due to bandwidth limitations of electrical circuits, it is not a preferred solution to work with analog values and at frequencies higher than the symbol rate.
  • CR block based on two samples per symbols is implemented.
  • OLK on-off keying
  • a preferable CR block was based on an Alexander nonlinear phase detector using two samples per symbol and a specific logic to derive clock.
  • Phase detector outputs can be expressed as "0", and "+” (which can mean “early”, “ambiguous”, and "late”,
  • Linear and nonlinear phase detectors using two samples per symbol are known, which are often used in practical PAM-4 systems.
  • the linear variant deals with analog and digital signals, selects "good transitions” and has very good jitter performance, but the main problem comes from oversampling and handling analog values.
  • the nonlinear variant is based on selective transitions of an Alexander phase detector. This variant introduces more jitter, but the implementation is not difficult at medium symbol rates.
  • a disadvantage of those two variants is oversampling, which presents a big problem at high data speeds, for example, at 56G, for which a 1 12G clock is required.
  • TDC timing error detector characteristic
  • An eye diagram is a common indicator of the quality of signals in high-speed digital transmissions.
  • An oscilloscope generates an eye diagram by overlaying sweeps of different segments of a long data stream driven by a master clock. Overlaying many bits produces an eye diagram, so called because the resulting image looks like the opening of an eye. In an ideal world, eye diagrams would look like rectangular boxes. In reality, communications are imperfect, so that the transitions do not line perfectly on top of each other, which results in an eye-shaped pattern. Differences in timing and amplitude from bit to bit cause the eye opening to shrink.
  • Fig. 2 shows a time diagram with a schematic eye diagram of a received signal with different sampling phases in the case of an early sampling. More specifically, Fig.
  • FIG. 2 depicts an example of an early sampling phase with samples A, B, and C and a best sampling phase (BSP) at the highest opening of an eye diagram, where the sample C is shortly before the best sampling phase.
  • the Alexander phase detector uses only the signs of three samples and drives an oscillator.
  • a truth table is a mathematical table used in logic - specifically in connection with Boolean algebra, Boolean functions, and propositional calculus - to compute the functional values of logical expressions on each of their functional arguments, that is, on each combination of values taken by their logical variables.
  • a truth table is composed of one column for each input variable, and one final column for all of the possible results of the logical operation that the table is meant to represent.
  • Each row of the truth table therefore contains one possible configuration of the input variables and the result of the operation for those values.
  • Fig. 3 shows a truth table of an Alexander phase detector, wherein the respective signs: Sign(A), Sign(B) and Sign(C) of the samples A, B and C of Fig.
  • the invention relates to an apparatus for recovering clock and data from an M-level signal of a receiver in a transmission system, where M is a positive integer and a power of two, and wherein two consecutive analog data of the M-level signal are sampled at a distance of one symbol period with respect to each other.
  • the apparatus comprises an M-level log2(M)-bit analog-to-digital converter (ADC) connected at an input of the apparatus, the M-level log2(M)-bit ADC being adapted to output an outer level bit corresponding to a polarity of an amplitude difference between an analog data of the M-level signal and a closest voltage threshold amongst 2-M and M-2 and adapted to output the most significant bit corresponding to a polarity of an amplitude difference between the analog data of the M-level signal and a voltage threshold equal to zero; a first voltage comparator connected at the input of the apparatus, the first voltage comparator being adapted to compare a first amplitude difference corresponding to an amplitude difference between the analog data and a first controllable threshold value; a second voltage comparator connected at the input of the apparatus, the second comparator being adapted to compare a second amplitude difference corresponding to an amplitude difference between the analog data and a second controllable threshold value; and a three-valued logic unit adapted to output,
  • the proposed clock and data recovery (CDR) apparatus can be advantageously used in transmission systems with M-level signals (e.g., PAM-4 or PAM-8 or other multi-level transmission systems). Indeed, clock extraction at very high baud (Bd) rates can be carried out since the proposed CDR apparatus uses only one sample per symbol.
  • the proposed CDR apparatus is also easy to implement as it requires only digital circuits and does not deal with analog values.
  • the proposed CDR apparatus can control the sampling phase by adjusting the phase detector thresholds.
  • the M-level signal has M equidistant levels, the M levels being odd integers starting from ⁇ 1 , and the analog data has an amplitude outside the range from 2-M to M-2.
  • the first and second controllable threshold values are controlled in order to minimize a bit error rate.
  • the first controllable threshold value has an amplitude equal to a sum of M- 1 and a first quantization value and wherein the second controllable threshold value has an amplitude equal to a sum of 1 -M and a second quantization value, the first and second controllable threshold values being controlled by adjusting the first and second quantization values.
  • the first and second quantization values are adjusted so as to have the first and second controllable threshold values varying in a reverse direction or in a same direction.
  • the selected amplitude difference is the smallest amplitude absolute difference amongst the first amplitude absolute difference and the second amplitude absolute difference.
  • the amplitude difference selection is performed by the most significant bit.
  • an output signal of the three-valued logic unit is given by the following truth table provided that the absolute values of Xi and X2 are strictly greater than M-2, i.e., abs(Xi )>M-2 and abs(X 2 )>M-2:
  • the M-level signal is an M-pulse amplitude modulation signal
  • the outer level bit is a least significant bit when M equals four.
  • the apparatus further comprises a filter adapted to filter the truth value output from the three-valued logic unit, and an oscillator adapted to receive the filtered truth value and generate a clock signal to be provided to the M-level log 2 (M)-bit ADC.
  • the invention relates to a method for recovering clock and data from an M-level signal of a receiver in a transmission system, where M is a positive integer and a power of two, and wherein two consecutive analog data of the M-level signal are sampled at a distance of one symbol period with respect to each other.
  • the method comprises the steps of outputting an outer level bit corresponding to a polarity of an amplitude difference between an analog data of the M-level signal and a closest voltage threshold amongst 2-M and M-2, outputting the most significant bit corresponding to a polarity of an amplitude difference between the analog data of the M-level signal and a voltage threshold equal to zero, comparing a first amplitude difference between the analog data and a first controllable threshold value, comparing a second amplitude difference between the analog data and a second controllable threshold value, and outputting, through a truth table, a truth value amongst -1 , 0 and +1 , based on a polarity of the most significant bit, a polarity of the outer level bit and a polarity of an amplitude difference to be selected amongst the first and second amplitude differences.
  • the method comprises the steps of filtering the truth value, receiving the filtered truth value, and generating a clock signal based on the received filtered truth value.
  • the invention relates to a computer program comprising a program code for performing the method according to the second aspect or any one of the implementations of the second aspect when executed on a computer. Thereby, the method can be performed in an automatic and repeatable manner.
  • the computer program can be performed by the above apparatus.
  • the apparatus can be programmably arranged to perform the computer program.
  • the above apparatus may be implemented based on a discrete hardware circuitry with discrete hardware components, integrated chips or arrangements of chip modules, or based on a signal processing device or chip controlled by a software routine or program stored in a memory, written on a computer-readable medium, or downloaded from a network, such as the internet.
  • the above apparatus may be implemented without signal transmission or receiving capability for simply controlling the transmission or reception function of a corresponding transmitter device or receiver device.
  • FIG. 1 shows a schematic block diagram of a simple conventional IM/DD-based PAM-4 transmission system 100, in which the present invention can be implemented;
  • Fig. 2 shows a time diagram with a schematic eye diagram of a received signal with different sampling phases in the case of an early sampling
  • Fig. 3 shows a truth table of a conventional Alexander phase detector
  • Fig. 4 shows a signal amplitude versus a normalized time (t/U I ) depicting an eye
  • Fig. 5 shows a truth table of a phase detector according to an embodiment of the
  • Fig. 6 shows TEDC versus a normalized time (t/UI) at two Rx input powers (OdBm and - l OdBm) according to an embodiment of the present invention
  • Fig. 7 shows the corresponding eye diagram of Fig. 6 at a Rx input power of OdBm
  • Fig. 8 shows the corresponding eye diagram of Fig. 6 at a Rx input power of -1 OdBm according to an embodiment of the present invention
  • Fig. 9 shows a signal amplitude versus a normalized time (t/UI) depicting an eye
  • Fig. 10 shows TEDC versus a normalized time (t/UI) for the respective 28GBd
  • Fig. 1 1 shows TEDC versus a normalized time (t/UI) for different pairs of thresholds according to an embodiment of the present invention
  • Fig. 12 shows a comparison of the PD performance between a conventional linear phase detector (LPD) and a proposed phase detector (NPD) using (a): an estimated root mean square Jitter (Jrms) versus the input power (Pin) and (b): BER versus Pin, according to an embodiment of the present invention;
  • Fig. 13 shows an assessment of the NPD performance using (a): an eye diagram at a
  • Fig. 14 shows a comparative BER performance between the default and optimized NPD thresholds with respect to the LPD thresholds, according to an embodiment of the present invention.
  • Fig. 15 shows a schematic block diagram of a proposed clock and data recovery device
  • a new phase detection approach for use in connection with clock and data recovery in multi-level signal transmission systems (e.g., PAM-4, PAM-8 or other PAM-M where M is a number of levels that is a positive integer and a power of two) is provided.
  • the new phase detection approach uses only one sample per symbol, which enables the clock extraction at very high baud (Bd) rates, and can be implemented based on a pure digital architecture with lowest sampling speed to recover the transmitted multi-level signal. Circuit schemes are thus easy to implement as they require only digital circuits and do not have to cope with analog values.
  • the proposed phase detection approach can control sampling phase by adjusting the thresholds of the phase detector (PD) and further enable timing in high-speed systems where the multi-level signal is already available before clock and data recovery. It can be achieved by using high bandwidth components and systems that do not require an enhanced DSP after the ADC block, so that it is suitable for small-size and low-power consumption transceivers.
  • PD phase detector
  • Various embodiments of the present invention will now be described based on a PAM-4 transmission system with an optical fiber.
  • the new algorithm of the proposed new phase detection approach works with a single sample per symbol.
  • the PAM-4 signal levels are equal to -3, -1 , +1 , and +3.
  • Fig. 4 shows a signal amplitude versus a normalized time (t/U I ) depicting an eye diagram after equalization of a received PAM-4 signal according to a first embodiment of the present invention.
  • the PAM-4 signal is equalized through a CTLE whose parameters are optimized based on a multi-modulus algorithm with a single sample per symbol.
  • the best sampling position is indicated by the dashed arrow "BSP".
  • BSP dashed arrow
  • a rule of the proposed phase detection (PD) scheme is to discard all samples that are in the range of amplitude level from "-2" to "+2" in Fig. 4. This is a so-called bad region. Only two consecutive samples Xi and X2 that are at a distance of 1 Ul and out of said range of amplitude level will be considered for clock and data recovery.
  • the PD outer levels need not to be equal to the ADC output levels -3 and +3 in order to allow the sampling phase to be adjusted.
  • Fig. 5 shows a truth table of a phase detector according to a second embodiment of the present invention.
  • the signal output from the output "OUT" of the phase detector which corresponds to a truth value amongst -1 , 0 and +1 , may then be filtered through a filter such as a low pass filter (LPF) and used to drive a clock oscillator such as a voltage-controlled oscillator (VCO).
  • LPF low pass filter
  • VCO voltage-controlled oscillator
  • the PD outer levels controlling the sampling phase are optimized in a dithering mode and the best sampling phase (BSP) corresponding to the minimum number of corrected bits output from a FEC block is found.
  • the PD outer levels can also be controlled in order to optimize the PD performance in terms of gain and jitter.
  • a 28GBd PAM-4 system (as shown in Fig. 1 ) with an externally modulated laser (EML) has been simulated.
  • TEDC has been tested in links without chromatic dispersion, with enough bandwidth, and with equalization. Only the receiver (Rx) input power has been varied. As can be seen in the diagram of Fig.
  • the curve is symmetric and without the hang-up region (only at 180° phase).
  • Figs. 7 and 8 show the corresponding eye diagrams at the respective Rx input powers of OdBm and -l OdBm.
  • the system with EML shown in Fig. 1 is experimentally verified at 28GBd and 56GBd at the received powers corresponding to a BER of 0.004.
  • the received PAM-4 signal is equalized by a FIR filter before the CDR block in order to get a PAM-4 signal with less inter-symbol interference (ISI).
  • Eye diagrams after equalization are shown in Fig. 9 for a Pin of -10 and - 4dBm in 28GBd and 56GBd systems, respectively.
  • the TEDC of those two systems are presented in Fig. 10.
  • the 56GBd system has a better TEDC (i.e., a higher PD gain) and also less jitter, although not presented herein, because of the existence of stronger signals above the level +3 and below the level -3.
  • Fig. 1 1 shows TEDC versus a normalized time (t/UI) for different pairs of thresholds, i.e., for (+3; -3), (+3.3; -2.7) and (+2.7; -3.3).
  • the optimum sampling phase is equal to 0 and TEDC with the thresholds +3 and -3 provides a sampling phase that is slightly shifted towards the right with respect to said optimum sampling phase.
  • the thresholds +3.3 and -2.7 also shift the TEDC towards the right with respect to said optimum sampling phase. Indeed, a better sampling phase is achieved by the thresholds +2.7 and -3.3.
  • the thresholds +2.9 and -2.9 do not change the sampling phase but improve the clock performance by providing a higher PD gain and less self-jitter.
  • the performance of the proposed phase detector (hereafter denoted by NPD) according to an embodiment of the present invention has been compared to a conventional linear phase detector (hereafter denoted by LPD) using an estimated root mean square jitter (Jrms) and a BER.
  • Jrms root mean square jitter
  • Fig. 12(a) showing the characteristics of Jrms versus the input power (Pin)
  • the NPD introduces more jitter than the LPD.
  • the NPD is more susceptible to BER degradation than the LPD.
  • the jitter degradation is not so serious and cannot cause such a BER degradation, so that it likely comes from the sampling phase.
  • the performance of the NPD according to an embodiment of the present invention has been assessed using (a): an eye diagram at a Pin of 2dBm and (b): TEDC versus a normalized time (t/UI) for two pairs of PD thresholds.
  • the eye diagram is skewed since the upper eye is slightly shifted towards the left whereas the lower eye is moved towards the right.
  • the TEDC diagram shown in Fig. 13(b) for the default PD thresholds +3 and -3 indicates that the sampling phase will be shifted by about 0.02UI, thereby causing a BER degradation.
  • Fig. 13(b) also shows that the TEDC is getting shifted towards the left at the exact position corresponding to the best BER by setting the two PD thresholds to optimized thresholds +2.8 and -3.2.
  • Fig. 14 shows a comparative BER performance between the default and optimized NPD thresholds with respect to the LPD thresholds.
  • the BER performance of the NPD with optimized thresholds (i.e., +2.8 and -3.2) and LPD is almost the same. No performance degradation with the NPD, which works only with a single sample per symbol and uses
  • MSBs and the signs of quantization errors with the optimum PD thresholds can be observed.
  • Fig. 15 shows a schematic block diagram of the proposed clock and data recovery (CDR) device 200 according to an embodiment of the present invention.
  • the proposed CDR device 200 according to the embodiment comprises a PAM-4 2-bit ADC 210 and a phase detector (PD) 220.
  • PD phase detector
  • the input of the CDR device 200 receives a PAM-4 signal (Rx PAM-4), which is identically provided to three voltage comparators 21 1 -213 of the PAM-4 2-bit ADC 210 and two voltage comparators 221 -222 of the PD 220.
  • Rx PAM-4 a PAM-4 signal
  • the first voltage comparator 21 1 compares a first amplitude difference corresponding to an amplitude difference between an analog data (X) of the PAM-4 signal and a voltage threshold equal to +2 as to output the least significant bit (LSB+, ⁇ 1 ) corresponding to the polarity ( ⁇ ) or sign ( ⁇ ) of the first amplitude difference.
  • the second voltage comparator 212 compares a second amplitude difference corresponding to an amplitude difference between the analog data (X) of the PAM-4 signal and a voltage threshold equal to -2 as to output the least significant bit (LSB-, ⁇ 1 ) corresponding to the polarity ( ⁇ ) or sign ( ⁇ ) of second amplitude difference.
  • the third voltage comparator 213 compares a third amplitude difference corresponding to an amplitude difference between the analog data (X) of the PAM-4 signal and a voltage threshold equal to 0 as to output the most significant bit (MSB, ⁇ 1 ) corresponding to the polarity ( ⁇ ) or sign ( ⁇ ) of the third amplitude difference.
  • the output (LSB+, LSB-, MSB) of each of these voltage comparators 21 1 -213 is temporarily stored in respective D-type flip-flops 214-216, to which they are connected. Afterwards, the output (MSB) of the third voltage comparator 213 selects, through a first selector 217, the correct outer level bit (OLB, ⁇ 1 ), which specifically corresponds to a least significant bit (LSB, ⁇ 1 ) in the case of a 2-bit ADC, amongst LSB+ and LSB-, namely the outer level bit (OLB, ⁇ 1 ) corresponding to the polarity ( ⁇ ) or sign ( ⁇ ) of the amplitude difference between the analog data (X) of the PAM-4 signal and the closest voltage threshold amongst -2 and +2.
  • the correct outer level bit OLB, ⁇ 1
  • the PAM-4 2-bit ADC 210 can output a 2-bit data (DATA: MSB, LSB/OLB) according to the truth table depicted above the D-type flip-flop 226.
  • DATA 2-bit data
  • the first voltage comparator 21 1 is connected in an inverting mode as to invert its output and thus generate a Gray encoded signal.
  • the first and second controllable threshold values (X u , Xdown) are controlled by using, for example, an outer decoder such as a FEC 240 or some known training sequence during the calibration phase, in order to minimize the BER, and adjusted accordingly as to obtain optimized threshold values.
  • the optimization process of the thresholds can be performed through a PD optimization and/or a sampling phase optimization.
  • the first and second controllable threshold values (X u , Xdown) are firstly varied in opposite directions until reaching the optimum PD performance (i.e., minimum BER after FEC 240). In this way, the sampling phase does not vary while the PD gain and jitter are controlled.
  • the optimized threshold values can then be -2.9, which is obtained by increasing -3, and +2.9, which is obtained by decreasing +3.
  • the first and second controllable threshold values (X u , Xdown) are firstly varied in same directions until reaching the optimum PD performance (i.e., minimum BER after FEC 240). In this way, the sampling phase varies together with the PD gain and jitter.
  • the optimized threshold values can then be -2.7, which is obtained by increasing -3, and +3.3, which is obtained by increasing +3.
  • each of these fourth and fifth voltage comparators 221 , 222 is temporarily stored in respective D-type flip-flops 223, 224, to which they are connected. Afterwards, the output (MSB) of the third voltage comparator 213 selects, through a second selector 225, a polarity ( ⁇ ) or sign ( ⁇ ) of the smallest amplitude absolute difference amongst the fourth amplitude difference and the fifth amplitude difference.
  • D-type flip-flops 226-228 and logical blocks 229-233 are added to generate the PD output (OUT) through a three-value logic unit 234, which outputs a truth value amongst -1 , 0 and +1 according to the truth table of Fig. 5.
  • the three-value logic unit 234 provides the digital output " ⁇ 1 " of the XOR gate 229 if the output of the AND gate 233 is in an active state corresponding to "1 ", and provides the digital output "0" of the XOR gate 229 if the output of the AND gate 233 is in an inactive state corresponding to "0".
  • the logical output "0" of the AND gate 233 reflects the last row denoted "otherwise” in the truth table of Fig. 5.
  • the XOR gate 229 with its two input signals corresponding to MSB and the selected amplitude difference amongst the first and second amplitude differences, reflects the remaining upper eight rows of the truth table in Fig. 5.
  • all blocks after the five voltage comparators 21 1 -213 and 221 -222 are digital.
  • the PD output (OUT) is then filtered through a filter such as a low-pass filter (LPF) 241 and used for driving a voltage-controlled oscillator (VCO) 242.
  • a filter such as a low-pass filter (LPF) 241 and used for driving a voltage-controlled oscillator (VCO) 242.
  • LPF low-pass filter
  • VCO voltage-controlled oscillator
  • the present invention has been specifically described in connection with a PAM-4 transmission system, it should be noted that the present invention can be used in any multilevel transmission systems with M levels, where M is a positive integer and a power of two.
  • the clock and data recovery (CDR) apparatus would comprise an M-level log2(M)-bit ADC consisting of (2 i052 ( ) - 1) voltage comparators.
  • M 8 levels denoted -7,-5,-3, -1 , +1 , +3, +5, and +7, wherein all samples that would be in the range of amplitude level from "- 6" to "+6" would be discarded.
  • the PAM-4 2-bit ADC 210 would be replaced by a PAM-8 3-bit ADC consisting of seven comparators, and the outer levels +2 and -2 of the corresponding comparators 21 1 and 212 would be respectively replaced by the outer levels +6 and -6.
  • the PAM-8 3-bit ADC would output a 3-bit data (DATA) according to the following truth table:
  • one comparator output in Fig. 15 can be inverted due to Gray mapping of the PAM-4 signal, and this is efficiently used for the Gray decoding and the logic enabling the detection of signals below the level -2 and above the level +2.
  • more comparator outputs should be inverted when the Gray decoding is performed.
  • the corresponding Gray codes would be then: "000”, “001 “, “01 1 ", “010”, “1 10", 1 1 1 ", “101 " and "100”.
  • the first controllable threshold value X u would have an amplitude equal to a sum of +7 and a first quantization value ( ⁇ 1 ), and the second controllable threshold value Xdown would have an amplitude equal to a sum of -7 and a second quantization value ( ⁇ 2).
  • the present invention relates to an apparatus and method for recovering clock and data from an M-level signal of a receiver in a transmission system, M being a positive integer and a power of two, wherein an outer level bit (OLB) corresponding to a polarity ( ⁇ ) or sign ( ⁇ ) of an amplitude difference between an analog data (X) of the M-level signal and a closest voltage threshold amongst 2-M and M-2 is output, the most significant bit (MSB) corresponding to a polarity ( ⁇ ) or sign ( ⁇ ) of an amplitude difference between the analog data (X) of the M-level signal and a voltage threshold equal to zero is output, a first amplitude difference between the analog data (X) and a first controllable threshold value (X u ) is compared, a second amplitude difference between the analog data (X) and a second controllable threshold
  • the present invention can be applied to any multilevel transmission system. More specifically, the transmission system is not restricted to an optical transmission system. Rather, the present invention can be applied to any wired or wireless coherent or non-coherent transmission system.
  • the transmitter and receiver device of the proposed system can be implemented in discrete hardware or based on software routines for controlling signal processors at the transmission and reception side.

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  • Computer Networks & Wireless Communication (AREA)
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Abstract

La présente invention concerne un appareil et un procédé de récupération d'horloge et de données dans un signal de niveau M d'un récepteur dans un système de transmission, M étant un nombre entier positif et une puissance de deux, un convertisseur analogique-numérique log2(M)-bit de niveau M (M) fournit, à partir d'une donnée analogique du signal de niveau M, un bit de niveau externe et le bit le plus significatif, une première différence d'amplitude entre les données analogiques et une première valeur de seuil réglable est comparée, une seconde différence d'amplitude entre les données analogiques et une seconde valeur de seuil réglable est comparée, une valeur de vérité sur la base de chaque polarité du bit le plus significatif, le bit de niveau externe et une différence d'amplitude à sélectionner parmi les première et seconde différences d'amplitude sont fournis par l'intermédiaire d'une table de vérité, et deux données analogiques consécutives sont échantillonnées à une distance d'une période de symbole l'une par rapport à l'autre.
EP16775635.2A 2016-09-28 2016-09-28 Recupératino d'horloge et de données dans de systèmes de transmission à pam-4 Active EP3510720B1 (fr)

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US10720995B1 (en) * 2019-08-21 2020-07-21 Cisco Technology, Inc. Unequal spacing on multilevel signals

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WO1988005235A1 (fr) * 1987-01-12 1988-07-14 Fujitsu Limited Circuit de commande de la temporisation de discrimination
EP1191735A1 (fr) * 2000-09-25 2002-03-27 Lucent Technologies Inc. Arrangement de circuit pour la récuperation de données et d' horloge
US6917658B2 (en) * 2002-09-16 2005-07-12 Silicon Labs Cp, Inc. Clock recovery method for bursty communications
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EP2405577B1 (fr) * 2010-07-06 2019-04-24 Cisco Technology, Inc. Procédé de détection de phase et circuit
JP5948195B2 (ja) * 2012-09-14 2016-07-06 ザインエレクトロニクス株式会社 クロック生成装置およびクロックデータ復元装置
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