EP3479422A1

EP3479422A1 - Poling of a piezoelectric thin film element in a preferred electric field driving direction

Info

Publication number: EP3479422A1
Application number: EP17737023.6A
Authority: EP
Inventors: Michael Hook; Silvia Marson; Peter Mardilovich; Susan Trolier-Mckinstry; Charalampos FRAGKIADAKIS; Song-Won Ko
Original assignee: Xaar Technology Ltd
Current assignee: Xaar Technology Ltd
Priority date: 2016-06-30
Filing date: 2017-06-30
Publication date: 2019-05-08
Also published as: JP2019522902A; GB201611430D0; GB2551803A; WO2018002648A1; GB2551803B

Abstract

A piezoelectric thin film element (220) is provided comprising a first electrode (260), a piezoelectric layer (240) formed on said first electrode; and a second electrode (280) formed on said piezoelectric layer; wherein said piezoelectric layer is poled, by applying a poling electric field across said piezoelectric layer from said first electrode to said second electrode, wherein said second electrode is at a lower potential relative to said first electrode, to orient dipoles of said piezoelectric layer in a dipole direction from said first electrode to said second electrode, and wherein said first and second electrodes are configured such that said second electrode is at a lower potential relative to said first electrode when said piezoelectric thin film element is deformed in a deformation direction predominantly opposite to said dipole direction.

Description

POLING OF A PIEZOELECTRIC THIN FILM ELEMENT IN A PREFERRED ELECTRIC FIELD DRIVING DIRECTION

The present techniques relate to methods of forming piezoelectric thin film elements having increased performance and stability. The piezoelectric elements may find particularly beneficial application in thin film actuators in a droplet deposition head, such as an inkjet printhead, in a sensor or in an energy harvesting device.

Known piezoelectric thin film elements use piezoceramic materials such as, for example, lead zirconate titanate (PZT), barium titanate (BT), potassium sodium niobate (KNN), doped PZT such as PLZT (doped by La³⁺), or PNZT (doped by Nb⁵⁺) as the piezoelectric material. However, piezoceramic lifetime decreases strongly with increases in the applied electric field, resulting in reduction in performance of the piezoelectric thin film element. To maximise the performance and stability in the piezoceramic, some treatment is necessary after deposition. It is known that to improve the stability of the performance of piezoelectric thin film elements the following solutions can be used :

• the applied electric field can be increased to compensate for performance degradation; or

• new piezoceramic materials with lower rates of degradation (and fatigue) can be developed; or

• a "burn in" approach can be used to cycle the piezoelectric thin film element before shipping to remove early (fast) degradation.

Aspects of the invention are set out in the appended claims.

Examples will now be described with reference to the accompanying Figures of which :

Figure 1A illustrates schematically a piezoelectric thin film element driven in a "field up" configuration;

Figures lB(i) to lB(iii) illustrate schematically the effect of applying a poling electric field to the piezoelectric thin film element;

Figure 2 illustrates schematically a membrane and a first electrode;

Figures 3A to 3F illustrate schematically different stages in the forming of a piezoelectric layer; Figure 4 illustrates a schematic layout of a row of piezoelectric elements;

Figure 5 illustrates a schematic layout of a row of piezoelectric elements with one option of connecting the electrodes;

Figure 6 illustrates a schematic layout of a row of piezoelectric elements with another option of connecting the electrodes;

Figure 7 illustrates a schematic layout of a row of piezoelectric elements for applying a poling treatment;

Figure 8 illustrates schematically a method of forming piezoelectric elements;

Figure 9 illustrates the breakdown field of PLZT vs temperature;

Figure 10 illustrates a measured change in performance of a "field up" driving scheme v's a "field down" driving scheme in the case where the piezoelectric element of Figure 9 is incorporated in an inkjet printhead;

Figure 11 illustrates membrane displacement of a poled v's unpoled piezoelectric actuator element having a "field up" driving scheme in the case of an inkjet actuator;

Figure 12 illustrates membrane displacement of a piezoelectric actuator element poled in the "field up" direction v's a piezoelectric actuator element poled in the "field down" direction in the case of an inkjet actuator;

Figure 13 illustrates schematically a cross-section view of a portion of a droplet deposition head die of a droplet deposition head;

Figure 14 illustrates schematically a printer;

Figure 15 illustrates the change in large signal displacement measurements as a function of the poling field;

Figure 16 is a graph illustrating the effect of poling on the displacement of partially released piezoelectric actuator membranes; and

Figure 17 illustrates a hysteresis loop showing imprint for a piezoelectric element.

The following disclosure describes a method of forming a piezoelectric thin film element. The method comprises: depositing a layer of first electrode material on a substrate; depositing a layer of piezoelectric material on said first electrode material; depositing a layer of second electrode material on said piezoelectric material; patterning said second electrode material and said piezoelectric material to form a second electrode and a piezoelectric layer; patterning said first electrode material to form a first electrode; patterning said substrate to form cavities below said first electrode of said piezoelectric thin film element, such that said piezoelectric thin film element is partially released; and poling said piezoelectric layer, by heating said piezoelectric layer to a temperature in a range from 100°C to 200°C and applying a poling electric field across said piezoelectric layer from said first electrode to said second electrode, wherein said second electrode is at a lower potential relative to said first electrode, to orient dipoles of said piezoelectric layer in a dipole direction from said first electrode to said second electrode.

The following disclosure additionally describes a method of forming a plurality of piezoelectric thin film elements on a wafer. The method comprises: depositing a layer of first electrode material on said wafer; depositing a layer of piezoelectric material on said first electrode material; depositing a layer of second electrode material on said piezoelectric material; patterning said second electrode material and said piezoelectric material to form a plurality of second electrodes and a plurality of piezoelectric layers; patterning said first electrode material to form a plurality of first electrodes; patterning said wafer to form cavities below said plurality of first electrodes of said plurality of piezoelectric thin film elements, such that said plurality piezoelectric thin film elements are partially released; and poling said plurality of piezoelectric layers, by heating said plurality of piezoelectric layers to a temperature in a range from 100°C to 200°C and applying a poling electric field across said plurality of piezoelectric layers from said plurality of first electrodes to said plurality of second electrodes, wherein said plurality of second electrodes are at a lower potential relative to said plurality of first electrodes, to orient dipoles of said plurality of piezoelectric layers in a dipole direction from said plurality of first electrodes to said plurality of second electrodes.

The following disclosure additionally describes a method of forming a piezoelectric thin film element. The method comprising : depositing a layer of first electrode material on a substrate; depositing a layer of piezoelectric material on said first electrode material; depositing a layer of second electrode material on said piezoelectric material; patterning said second electrode material and said piezoelectric material to form a second electrode and a piezoelectric layer; patterning said first electrode material to form a first electrode; patterning said substrate to reduce a thickness of said substrate, such that said piezoelectric thin film element is partially released; and poling said piezoelectric layer, by heating said piezoelectric layer to a temperature in a range from 100°C to 200°C and applying a poling electric field across said piezoelectric layer from said first electrode to said second electrode, wherein said second electrode is at a lower potential relative to said first electrode, to orient dipoles of said piezoelectric layer in a dipole direction from said first electrode to said second electrode.

The following disclosure additionally describes a method of forming a plurality of piezoelectric thin film elements on a wafer, the method comprising : depositing a layer of first electrode material on said wafer; depositing a layer of piezoelectric material on said first electrode material; depositing a layer of second electrode material on said piezoelectric material; patterning said second electrode material and said piezoelectric material to form a plurality of second electrodes and a plurality of piezoelectric layers; patterning said first electrode material to form a plurality of first electrodes; patterning said wafer to reduce a thickness of said wafer, such that said piezoelectric thin film element is partially released; and poling said plurality of piezoelectric layers, by heating said piezoelectric layer to a temperature in a range from 100°C to 200°C and applying a poling electric field across said plurality of piezoelectric layers from said plurality of first electrodes to said plurality of second electrodes, wherein said plurality of second electrodes are at a lower potential relative to said plurality of first electrodes, to orient dipoles of said plurality of piezoelectric layers in a dipole direction from said plurality of first electrodes to said plurality of second electrodes.

The following disclosure additionally describes a piezoelectric actuator comprising a piezoelectric thin film element formed by the method described above.

The following disclosure additionally describes a sensor comprising said piezoelectric thin film element described above.

The following disclosure additionally describes a piezoelectric thin film element. The piezoelectric thin film element comprising : a first electrode formed on a substrate; a piezoelectric layer formed on said first electrode by a sol-gel method; and a second electrode formed on said piezoelectric layer; wherein said substrate is patterned to form cavities below said first electrode of said piezoelectric thin film element, such that said piezoelectric thin film element is partially released, wherein said piezoelectric layer is poled, such that said piezoelectric layer comprises a positive imprint, and wherein said first and second electrodes are configured such that said second electrode is at a lower potential relative to said first electrode when said piezoelectric thin film element is deformed in a deformation direction from said second electrode to said first electrode.

Figure 1A illustrates a simplified piezoelectric element 220 comprising a first electrode 260, a piezoelectric layer 240 and a second electrode 280. The piezoelectric element 220 is formed on a substrate (not illustrated). In one embodiment, the first electrode 260 comprises Pt (platinum), the second electrode 280 comprises Ir0₂ (iridium oxide) and the piezoelectric layer 240 comprises PZT. In another embodiment, the piezoelectric layer 240 comprises PXZT (lead zirconate titanate, where X is a dopant). Figure 1 illustrates the first and second electrodes as being provided on different faces of the piezoelectric layer; however, a structure with both electrodes on the same face of the piezoelectric layer (e.g. interdigitated) is possible. In addition, a structure having piezoelectric layers alternated with electrodes is possible.

In one embodiment, the piezoelectric layer 240 is formed by chemical solution deposition (CSD), for example sol-gel method. However, other methods of forming the piezoelectric layer 240 may be used.

There is no pronounced spontaneous dipole polarisation of the piezoelectric layer following deposition, drying, pyrolysis and annealing, such that most of the dipoles of the piezoelectric layer are overall randomly oriented, This is illustrated in Figure lB(i) which illustrates the dipoles (arrows 210) in a random distribution of orientation. In order to create an initial alignment state in the piezoelectric layer such that most of the dipoles are oriented in substantially the same dipole direction, the piezoelectric layer is poled.

The piezoelectric layer is poled in the "field up" direction, resulting in the dipoles of the piezoelectric layer being oriented in a dipole direction from the first electrode 260 towards the second electrode 280, as indicated by the arrow E in Figure 1A.

In order to pole the piezoelectric layer, a poling electric field Ep_f as illustrated in Figure IB(ii), is applied across the piezoelectric layer, from the first electrode to the second electrode (in a "field up" configuration). In order to apply a poling electric field Ep in a "field up" configuration, the second electrode is provided at a lower potential V2 relative to the first electrode, which is provided at potential VI, i .e. V2<V1. The dipoles align along the direction of the poling electric field Ep, when the poling electric field exceeds the coercive field of the material of the piezoelectric layer. The poling electric field is greater than or equal to a coercive field of the material of said piezoelectric layer and less than the field strength at which breakdown occurs in the material of the piezoelectric layer. In addition, a predetermined temperature is applied to the piezoelectric layer whilst it is held at the poling electric field Ep for a predetermined period of time, Once the poling electric field Ep is removed, the dipoles relax slightly but still point along a net dipole orientation that is aligned to the previous poling electric field Ep direction, as illustrated in Figure IB(iii), giving rise to a remanent polarization of the piezoelectric layer after poling that exceeds the level of remanent polarisation before poling.

The poling process described herein comprises the application of an external field within a predefined range, at a temperature within a predefined range, for a period of time within a predefined range. A smaller field can be applied when a higher temperature and/or longer period of time is applied; or a lower temperature can be applied when a larger field and/or a longer period of time is applied; or a shorter period of time can be applied when a larger field and/or a higher temperature is applied. The field, temperature and period of time required in order to achieve the desired results are a balance of timescales, performance, and manufacturing practicality.

The external field applied in a "field up" configuration for poling can range from an amplitude value greater than the coercive field of the material of the piezoelectric layer to a field strength just below the field strength at which breakdown occurs in the material of the piezoelectric layer. The temperature at which the field is applied can range from room temperature to the temperature at which breakdown of the material of the piezoelectric layer occurs and/or the temperature at which breakdown of the other materials of the piezoelectric element occurs. When a low temperature, such as room temperature_f is applied, then the period of time for which the temperature and field are applied is increased,

The period of time for which the field is applied is at least a minimum period of time required to orient the dipoles of the piezoelectric layer in a "field up" direction, and depends on the temperature and field strength applied,

Thin film piezoelectric elements have much higher coercive fields, by a factor of about 5 or more, than bulk piezoelectric elements, and can withstand much higher electric fields. Therefore, it is possible to pole a thin film piezoelectric element at high fields, for example, using a poling electric field equal to or greater than 3 times the coercive field of the material of the piezoelectric element in the poling direction. According to one embodiment, a thin film piezoelectric element has a negative coercive field of -34 kV/cm (-3.4 V/pm), According to another embodiment, a thin film piezoelectric element has a positive coercive field of 14 kV/cm (1.4 V/pm), According to one embodiment, it is possible to pole a thin film piezoelectric element, using a poling electric field in a range from 1 to 20 times the coercive field of the material of said piezoelectric element. According to another embodiment, it is possible to pole a thin film piezoelectric element using a poling electric field in a range from 1 to 10 times the coercive field of the material of said piezoelectric element.

According to one embodiment, the poling electric field is greater than or equal to a coercive field of a material of the piezoelectric layer, and the poling electric field is applied for a predetermined period of time and at a predetermined temperature such that electrical breakdown of the material of the piezoelectric layer is avoided.

A net orientation of the dipoles of the piezoelectric layer in a "field up" direction is achieved when the applied poling electric field is at least as high as the coercive field of the material of the piezoelectric layer, the applied temperature is greater than or equal to 100°C, and the period of time of application is between I to 60 minutes, as this provides improved performance in acceptable manufacturing timescales. According to one embodiment, the poling electric field is applied at a temperature in a range from 100°C to 200°C, and for a period of time in a range from 1 to 60 minutes. According to another embodiment, the poling electric field is applied at a temperature in a range from 100°C to 200°C, and for a period of time in a range from 1 to 30 minutes.

However, for some applications, temperatures lower than 100°C down to room temperature and longer periods of time are acceptable.

In one embodiment, a poling field in the range of 10 V/pm to 60 V/pm is applied at a temperature in the range of 100°C to 180°C for between 5 to 60 minutes to pole the piezoelectric layer. In another embodiment, a poling field in the range of 20 V/pm to 30 V/pm is applied at a temperature in the range of 120°C to 150°C for between 20 to 30 minutes to pole the piezoelectric layer.

The poling field is maintained whilst the piezoelectric layer is cooled down to a temperature less than 40°C and preferably cooled down to room temperature.

In one embodiment, the piezoelectric layer is heated up to the desired temperature, the poling field is applied in a "field up" configuration for the required period of time, and then the poling field is maintained until the piezoelectric layer has cooled down to a temperature less than 40°C. In another embodiment, the poling field is applied in a "field up" configuration to the piezoelectric layer, the piezoelectric layer is heated up to the desired temperature, the poling field is maintained for the required period of time, then the poling field is further maintained until the piezoelectric layer has cooled down to a temperature less than 40°C.

In order to obtain an electric field in the "field up" direction, the second electrode 280 is provided at a lower potential relative to the first electrode 260. This is achieved through, for example, grounding the first electrode 260 and driving the second electrode 280 with a negative drive signal, or by grounding the second electrode 280 and driving the first electrode 260 with a positive drive signal, Alternatively, any configuration which results in a negative voltage with reference to the first electrode 260 can be used.

A piezoelectric element which has been poled in the "field up" direction has improved performance and stability when also driven in the "field up" direction. In order to drive a piezoelectric element which has been poled in the "field up" direction with a "field up" drive signal, the second electrode 280 is configured to be driven at a lower potential relative to the first electrode 260. As with the poling, this is achieved through, for example, grounding the first electrode 260 and driving the second electrode 280 with a negative drive signal, or by grounding the second electrode 280 and driving the first electrode 260 with a positive drive signal . Alternatively, any configuration which results in a negative voltage with reference to the first electrode 260 can be used.

When a piezoelectric element is driven in the "field up" direction, where the second electrode is driven at a lower potential relative to the first electrode, the piezoelectric element is deformed in a deformation direction which is predominantly opposite to the dipole direction. For example, with reference to Figures 1A and lB(iii), the dipole direction extends from the first electrode 260 towards the second electrode 280. Consequently, when the piezoelectric element 220 is driven in the "field up" direction, the deformation direction extends from the second electrode 280 towards the first electrode 260. In some circumstance, when a piezoelectric element is driven in the "field up" direction, the piezoelectric element may deform slightly in the dipole direction first before deforming, with a larger deformation, in the deformation direction. However, in these circumstances, the piezoelectric element is still considered to be deformed in the deformation direction. It has been found that piezoelectric elements, which have been poled in the

"field up" direction and driven in the "field up" direction, deform in the deformation direction by more than or equal to 20% of the deformation of unpoled piezoelectric elements driven in the "field up" direction.

A piezoelectric element having a piezoelectric layer poled to have a "field up" polarisation and driven in the "field up" direction has a significantly improved performance and stability when compared to the same piezoelectric element having a piezoelectric layer poled to have a "field down" polarisation and driven in the "field down" direction, and when compared to a piezoelectric element having an unpoled piezoelectric layer driven in the "field down" direction or an unpoled piezoelectric layer driven in the "field up" direction. In addition, high temperature poling results in a reduction in the hysteresis energy loss over a cycle, which results in a higher efficiency and a reduction in self-heating of the piezoelectric material. Self-heating of the piezoelectric material can be detrimental to the piezoelectric elements performance during operation.

Figure 2 illustrates schematically a membrane 200 and a first electrode 260 of a piezoelectric thin film element. The membrane 200 is deposited on a silicon (Si) substrate (100). In one embodiment, the membrane 200 comprises a silicon oxide (S1O2) layer 200A, a silicon nitride (Si₃N₄) layer 200B and an aluminium oxide (Al₂0₃) layer 200C. Once the silicon substrate 100 has been etched to create a cavity under the membrane 200 such that the membrane 200 is defined with a suitable thickness, the membrane 200 becomes flexible enough to be bent by a deformation of the piezoelectric thin film element.

The silicon oxide layer 200A is formed on a surface of the Si substrate 100 through thermal oxidation. In one embodiment, the S1O2 layer 200A is formed to a thickness of 690 nm . The silicon nitride layer 200B is deposited on a surface of the silicon oxide layer 200A via plasma-enhanced chemical vapour deposition (PECVD). In one embodiment, the silicon nitride layer 200B is deposited via PECVD to a thickness of 690 nm . In one embodiment, an arithmetic average roughness (Ra) of 4 nm or less can be obtained as described in US Patent Publication No: 2014/0267509 Al for the surface of the silicon nitride layer 200B. In addition, the surface roughness of the silicon nitride layer 200B can be further reduced by polishing the silicon nitride layer 200B using chemical mechanical polishing (CMP). CMP can achieve a root mean square roughness value to several Angstroms, as described in US Patent No: 8,981,427 B2.

An aluminium oxide (Al₂0₃) layer 200C is deposited on the surface of the silicon nitride layer 200B via atomic layer deposition (ALD) or a sputtering technique to a thickness of 80 nm.

The silicon oxide layer 200A, silicon nitride layer 200B and aluminium oxide layer 200C together form the membrane 200. In one embodiment, the mean square roughness (RMS) of the membrane is 0.8 nm .

A titanium (Ti) adhesion layer 260A is deposited onto the surface of the aluminium oxide layer 200C. In one embodiment, the Ti layer 260A is 20 nm thick. In one embodiment, the Ti layer 260A is deposited via sputtering in an argon (Ar) environment. A platinum (Pt) layer 260B is deposited onto the surface of the Ti layer 260A. In one embodiment, the platinum (Pt) layer 260B is 200 nm thick. In one embodiment, the platinum (Pt) layer 260B is deposited by sputtering in an argon (Ar) environment, at room temperature. The Ti layer 260A and Pt layer 260B form the first electrode 260. Ti ion from layer 260A will diffuse into the Pt layer along the grain boundaries and will oxidise into TiOx after subsequent thermal processing, described below.

A piezoelectric layer is then formed on the Pt layer. The piezoelectric layer can be formed using chemical solution deposition, chemical vapour deposition or any other thin film formation methods.

In one embodiment, the piezoelectric layer comprises lead titanate zirconate (PZT) as the main component.

In another embodiment, the piezoelectric layer comprises doped PZT as a main component, including one or more dopant species chosen among donor, acceptor and isovalent dopant species.

Figures 3A to 3F illustrate schematically different stages in the forming of a piezoelectric layer. The following description refers to using a chemical solution deposition (CSD) process to form the piezoelectric layer. However, as stated above, other methods of forming the piezoelectric layer can be used, such as, chemical vapour deposition or any other thin film formation methods. Examples of CSD processes are a sol-gel process and a metal organic deposition process. When a CSD process is used, the method comprises depositing precursor layers by applying a chemical solution onto a first electrode provided on a membrane or thin film layer, followed by drying and pyrolysis. The number of precursor layers in any one step can, in particular, be one, two, three or four precursor layers.

The chemical solution can be applied by spin-coating or dip-coating or by any of the coating techniques known to the art. In one embodiment, the drying comprises heating to a temperature of between 100°C and 250°C and the pyrolysis comprises heating to a temperature of between 200°C and 500°C. The method comprises further annealing the precursor layers to form a thin film layer comprising a crystalline or polycrystalline structure based on metal oxides and having a perovskite crystal structure (ABO3). The crystal or the crystallites can, in particular, comprise PZT and/or doped PZT.

In one embodiment, the method comprises annealing the precursor layers by heating from below the membrane to a temperature between 450°C and 800°C, for example between 450°C and 700°C. This heating, which can be accomplished by rapid thermal processing (RTP), results in very good columnar growth of crystallites and well-defined grain boundaries between grains.

The dopants can be selected from the group of dopant types consisting of acceptor dopants, donor dopants and isovalent dopants. In one embodiment, the first and further steps form thin film layers in which the dopants notionally occupy the same or different co-ordination sites (A or B) in the perovskite crystal structure (ABO3).

The first and further steps can provide a laminate comprising further thin film layers which are undoped. They can alternatively or additionally provide a laminate comprising further thin film layers which are doped by one or more dopants which are the same as or different to the dopant or dopants of the first thin film layer and/or the dopant or dopants of the second thin film layer.

Figures 3A to 3F illustrate schematically a method for manufacturing a piezoelectric layer 240 according to one embodiment of the present invention. A seed layer comprising appropriate amounts of lead titanate (PT), PZT or doped PZT is deposited, for example using CSD, on a surface of a first electrode 260. In one embodiment, the precursor seed layer is deposited by spin-coating, dip-coating or by any of the coating techniques known to the art. The precursor seed layer is dried by heating the membrane and seed layer to a temperature of between 100°C to 250°C for between 30 seconds to 10 minutes, preferably from between 1 minute to 5 minutes. The dried layer is pyrolysed by heating the membrane and dried layer to a temperature of between 200°C to 500°C for between 30 seconds to 10 minutes and annealed by heating at a temperature of between 450°C and 800°C, preferable 600°C to 700°C, for between 30 seconds to 5 minutes to provide a seed layer 240A (as illustrated in Figure 3A). In one embodiment, the thickness of the seed layer is in the range of 50-75 nm . In another embodiment, the thickness of the seed layer is 65 nm . When the seed layer comprises PT, then the seed layer can have a thickness in the range of 5 - 75 nm . It will be appreciated that the composition and thickness of the seed layer may be adjusted suitably to achieve the desired performance and is not limited to the use of PT.

A first layer comprising appropriate amounts of PZT and dopant precursor is then deposited on a surface of the seed layer 240A. In one embodiment, the seed layer 240A is not required, in which case the first layer is deposited on a surface of the first electrode 260. In one embodiment, the first layer is deposited by spin-coating, dip-coating or by any of the coating techniques known to the art onto the surface of the seed layer 240A/surface of the first electrode, as appropriate. The first layer is dried by heating to a temperature of between 100°C to 250°C for between 30 seconds to 10 minutes, preferably from between 1 minute to 5 minutes. The dried first layer is pyrolysed by heating the dried first layer to a temperature of between 200°C to 500°C for between 30 seconds to 10 minutes to provide a first amorphous precursor layer 24A. A second layer comprising appropriate amounts of PZT and a dopant precursor is then deposited on a surface of the first amorphous precursor layer 24A. In one embodiment, the second layer is deposited by spin-coating, dip-coating or by any of the coating techniques known to the art onto the surface of the first amorphous precursor layer 24A. The second layer is dried by heating to a temperature of between 100°C to 250°C for between 30 seconds to 10 minutes, preferably from between 1 minute to 5 minutes. The dried second layer is pyrolysed by heating the dried second layer to a temperature of between 200°C to 500°C for between 30 seconds to 10 minutes to provide a second amorphous precursor layer 24B (as illustrated in Figure 3B). In one embodiment, the thickness of the first amorphous precursor layer 24A is between about 70-75 nm and the thickness of the second amorphous precursor layer 24B is between about 70-75 nm, forming a double layer having a thickness of between about 140-150 nm . The first and second precursor layer 24A, 24B are then annealed together to form a crystalline layer. In one embodiment, the first and second amorphous precursor layers 24A, 24B are heated rapidly to a temperature of between 450°C and 800°C, preferable 600°C to 700°C, for between 30 seconds to 5 minutes by rapid thermal processing (RTP) of the layers. The heating anneals the two precursor layers together to form a first crystallised thin film layer 240B (as illustrated in Figure 3C) comprising PZT doped by a dopant.

A third layer comprising appropriate amounts of PZT and dopant precursor is then deposited on a surface of the first thin film layer 240B and dried and pyrolised as described above to provide a third amorphous precursor layer 24C on the thin film layer 240B (as illustrated in Figure 3D). The deposition, drying and pyrolysis are then repeated so as to provide a fourth amorphous precursor layer 24D on the third amorphous precursor layer 24C (as illustrated in Figure 3D). In one embodiment, the thickness of the third amorphous precursor layer 24C is between about 70-75 nm and the thickness of the fourth amorphous precursor layer 24D is between about 70-75 nm, forming a double layer having a thickness of between about 140-150 nm .

The layers 24C, 24D are rapidly heated to a temperature of between 450°C and 800°C, preferable 600°C to 700°C, for between 30 seconds to 5 minutes to anneal the precursor layers 24C and 24D together to form a second crystallised thin film layer 240C comprising PZT doped by a dopant (as illustrated in Figure 3E).

The cycle of depositing, drying and pyrolysis to form two amorphous precursor layers which are then annealed together to form a crystallised thin film layer, such as described above with reference to layers 240B and 240C, is then repeated so as to provide a laminate of desired thickness comprising doped PZT thin film layers (as illustrated in Figure 3F).

In another embodiment, the piezoelectric layer 240 comprises a laminate of single layers, double layers, triple layers and/or quadruple layers. A triple layer comprises depositing, drying and pyrolysing three amorphous precursor layers which are then annealed together to form a crystalline thin film layer, and a quadruple layer comprises depositing, drying and pyrolysing four amorphous precursor layers which are then annealed together to form a crystalline thin film layer.

In one embodiment, there is a total of 27 coating steps, forming 1 seed layer 240A, and 13 double layers 240B, 240C, 240n, to achieve a total thickness of the piezoelectric layer 240 of approximately 1.9 μιτι.

In another embodiment, a total thickness of the piezoelectric layer 240 is in the range of 1.0 μηη to 3.0 μηι.

In one embodiment, the doped PZT comprises PLZT having 1.1 mol% lanthanum (La).

A donor dopant can be selected from the group of dopants consisting of La³⁺, Ta⁵⁺, V⁵⁺, U⁵⁺, Nb⁵⁺ and W⁶⁺ as well as trivalent ions of the rare earth elements.

An acceptor dopant can be selected from the group of dopants consisting of Na⁺, K⁺, Cs⁺, Rb⁺, Cu⁺, Mn⁺, Li⁺, Cu²⁺, Co²⁺, Mn²⁺, Nb²⁺, Ni²⁺, Mn³⁺, Y³⁺, as well as divalent and trivalent ions of the alkaline earth and rare earth elements.

An isovalent dopant can be selected from the group of dopants consisting of Mn⁴⁺, Hf⁴⁺, Sn⁴⁺, Mg²⁺, Ca²⁺, Sr²⁺ and Ba²⁺ as well as other divalent ions of the alkaline earth and rare earth metals. In one embodiment, the process can use a sol-gel solution with a dopant precursor, or a sol-gel solution without a dopant precursor so that the laminate includes one or more undoped thin film layers of PZT.

A second electrode (not shown in Figures 3A to 3F) is then formed on to the top thin film layer 240n. In one embodiment, the second electrode is an iridium oxide (Ir0₂) based electrode. In one embodiment, in order to form the second electrode, a layer of Ir0₂ is deposited via reactive sputtering from an iridium target to a thickness of 50 nm, followed by depositing a 50 nm thick Ir layer on top of the layer of Ir0₂ by sputtering. The second electrode and the piezoelectric layers are etched with the required pattern. The first electrode is then etched.

In one embodiment, a continuous layer of the first electrode material is deposited on a substrate, followed by deposition of a continuous layer of piezoelectric material (comprising the piezoelectric layers as described above), followed by deposition of a continuous layer of the second electrode material. The second electrode material and the piezoelectric material are patterned together to form the second electrode and the piezoelectric layer of individual piezoelectric elements. Finally, the first electrode material is patterned to form individual first electrodes having a slightly larger shape than the second electrodes.

A passivation layer is deposited over the electrodes and piezoelectric layers. In one embodiment, the passivation layer comprises aluminium oxide deposited via sputtering or ALD to a thickness of 80 nm . In another embodiment, the passivation layer comprises silicon oxide deposited via PECVD at a temperature of 400°C to a thickness of 80 nm . Following deposition, the passivation layer is etched to, for example, form vias to allow connection to the electrodes.

A metal layer is deposited and etched to form metal tracks that connect to the electrodes. Finally, another layer of passivation is deposited.

In another embodiment, a continuous layer of the first electrode material is deposited on the membrane and patterned to form individual first electrodes. A continuous layer of the piezoelectric material (comprising the piezoelectric layers as described above) is then deposited on top of the first electrodes and patterned. A continuous layer of the second electrode material is then deposited on top of the piezoelectric material (spanning all of them). At one end, the first electrodes protrude from beneath the second electrode.

According to one embodiment, a partially released thin film piezoelectric element is poled in the field up direction and then driven in the field up direction. Figure 13 illustrates an example of a portion of a droplet deposition head. As illustrated in Figure 13, at least one fluidic chamber 10 is formed within the fluidic chamber substrate 2. A membrane 20 is provided at the top surface 19 of the fluidic chamber substrate 2, and arranged to cover the fluidic chamber 10. A piezoelectric actuator element 22, comprising a piezoelectric layer 24 provided with two electrodes 26 and 28, is provided on the membrane 20.

To create a partially released thin film piezoelectric element, the wafer (for example, fluidic chamber substrate 2) supporting the thin film piezoelectric element is patterned from below by, for example, an etch process to form cavities (for example, fluidic chamber 10) underneath the thin film piezoelectric element 22. The thin film piezoelectric element is now 'partially released'. A partially released thin film piezoelectric element, as described in this disclosure is, in other words, an element that is still pinned to the substrate 2, through the membrane 20, the thin film piezoelectric element and the membrane 20 being pinned substantially along the entire perimeter of the feature produced upon patterning (for example, the fluidic chamber 10). Following the substrate patterning process resulting in the cavity 10, the partially released thin film element is now supported on the membrane 20 that is sufficiently thin to be flexible and to allow the piezoelectric element to deform and bend the membrane 20. Consequently, the membrane 20 that the thin film piezoelectric element 22 is supported on, is now able to deform when an electric field is applied across the thin film piezoelectric element 22. The thin film piezoelectric element 22 remains somewhat impeded in its movement by being attached to the membrane 20 which in turn is 'pinned' to substantially the entire perimeter of the underlying walls of the chamber 10 created by etching. However, the partially released thin film piezoelectric element is allowed to strain, in plane, to a high extent.

The piezoelectric element 22, provided on the membrane 20, may have a smaller area than that of the membrane 20 and chamber 10, such that there exists a gap around, part, most or all of the perimeter of the piezoelectric element and the chamber 10 formed in the substrate 2. The membrane 20 being provided between the piezoelectric element 22 and the substrate 2. This configuration allows the piezoelectric element 22 to deform more effectively. However, the piezoelectric element 22 is still considered to be partially released in that it is pinned along its perimeter to the substrate via the membrane 20. The membrane 20 may be formed from the substrate wafer by etching or may be formed from a separately applied layer.

A fully released thin film piezoelectric element, for example, a free standing thin film piezoelectric element not pinned to any substrate or any part thereof, would be free to achieve full deformation. Conversely, a clamped thin film piezoelectric element is pinned to a rigid substrate, through contact with the entire surface and perimeter of the thin film piezoelectric element contacting the substrate. For example, a thin film piezoelectric element is clamped when the fluidic chamber substrate 2 has not yet been etched to form the fluid chamber 10. It will be understood that different actuator geometries may result in different degrees of 'partial' release which may affect the resulting strains achievable in a beneficial or adverse way, for example geometries where the piezoelectric element is not pinned substantially along its entire perimeter. According to one embodiment, the substrate upon which the first electrode material is deposited is patterned to form cavities below the first electrode, creating a partially released piezoelectric element. The piezoelectric layer is then poled, by applying a poling electric field across the piezoelectric layer from the first electrode to the second electrode, in the "field up" direction. The "field up" direction is achieved by the second electrode being provided at a lower potential relative to the first electrode. This results in the dipoles of the piezoelectric layer being substantially oriented in the dipole direction from the first electrode to the second electrode.

According to another embodiment, the substrate upon which the first electrode material is deposited is patterned to form cavities. Etching could be used to pattern the substrate and form the cavities. The piezoelectric layer is then poled, by applying a poling electric field across the piezoelectric layer from the first electrode to the second electrode, in the "field up" direction. The "field up" direction is achieved by the second electrode being provided at a lower potential relative to the first electrode. This results in the dipoles of the piezoelectric layer being substantially oriented in the dipole direction from the first electrode to the second electrode. Following poling, the cavities are filled, either wholly or partially, using a low temperature process, such as sputtering, reactive sputtering etc, the temperature of the process being such that degradation of the piezoelectric element is avoided. Examples of material which could be used to fill the cavities include alumina AI2O3, hafnia Hf0₂, zirconia Zr0₂, silicates e.g. TaSiOx, titanates e.g. AITiOx. The formation of the cavities, improve the efficiency of the poling procedure, when compared to poling performed when no cavities have been formed. According to another embodiment, the substrate upon which the first electrode material is deposited is patterned to reduce the thickness of the substrate. Etching could be used to reduce the thickness of the substrate. The piezoelectric layer is then poled, by applying a poling electric field across the piezoelectric layer from the first electrode to the second electrode, in the "field up" direction. The "field up" direction is achieved by the second electrode being provided at a lower potential relative to the first electrode. This results in the dipoles of the piezoelectric layer being substantially oriented in the dipole direction from the first electrode to the second electrode. Following poling, the thickness of the substrate is increased, using a low temperature process, such as atomic layer deposition (ALD), sputtering, reactive sputtering etc. The temperature of the process being such that degradation of the piezoelectric element is avoided. Examples of material which could be used to increase the thickness of the substrate include alumina AI2O3, hafnia Hf02, zirconia Zr0₂, silicates, e.g. TaSiOx, titanates e.g. AITiOx. Reducing the thickness of the substrate improves the efficiency of the poling procedure when compared to poling performed where the thickness of the substrate has not been reduced.

According to another embodiment, a continuous layer of the first electrode material is deposited on a wafer, followed by deposition of a continuous layer of piezoelectric material and deposition of a continuous layer of the second electrode material. The piezoelectric material may comprise the piezoelectric layers as described above. The second electrode material and the piezoelectric material are patterned together to form a plurality of second electrodes and a plurality of piezoelectric layers, and the first electrode material is patterned to form a plurality of first electrodes. The wafer is then patterned to form cavities below the plurality of first electrodes, creating a plurality of partially released piezoelectric elements. The plurality of piezoelectric layers are then poled, by applying a poling electric field across the piezoelectric layers from the plurality of first electrodes to the plurality of second electrodes, in the "field up" direction. The "field up" direction is achieved by the plurality of second electrodes being provided at a lower potential relative to the plurality of first electrodes. This results in the dipoles of the plurality of piezoelectric layers being substantially oriented in the dipole direction from the plurality of first electrodes to the plurality of second electrodes. This wafer level poling enables more than one piezoelectric elements to be poled at the same time.

According to another embodiment, following formation of the plurality of first electrodes, the wafer upon which the plurality of first electrodes are formed is patterned to form cavities, creating a plurality of partially released piezoelectric elements. Etching could be used to pattern the wafer and form the cavities. The plurality of piezoelectric layers are then poled by applying a poling electric field across the piezoelectric layers from the plurality of first electrodes to the plurality of second electrodes, in the "field up" direction. The "field up" direction is achieved by the plurality of second electrodes being provided at a lower potential relative to the plurality of first electrodes. This results in the dipoles of the plurality of piezoelectric layers being substantially oriented in the dipole direction from the plurality of first electrodes to the plurality of second electrodes. Following poling, the cavities are filled, either wholly or partially, using a low temperature process, such as sputtering, reactive sputtering etc. The temperature of the process being such that degradation of the piezoelectric element is avoided. Examples of materials which could be used to fill the cavities include alumina AI2O3, hafnia Hf02, zirconia Zr0₂, silicates, e.g. TaSiOx, titanates e.g. AITiOx. The formation of the cavities improves the efficiency of the poling procedure when compared to poling performed where no cavities have been formed. In addition, this wafer level poling enables more than one piezoelectric elements to be poled at the same time.

According to another embodiment, following formation of the plurality of first electrodes, the wafer upon which the plurality of first electrodes are formed is patterned to reduce the thickness of the wafer. Etching could be used to reduce the thickness of the wafer. The plurality of piezoelectric layers are then poled, by applying a poling electric field across the piezoelectric layers from the plurality of first electrodes to the plurality of second electrodes, in the "field up" direction. The "field up" direction is achieved by the plurality of second electrodes being provided at a lower potential relative to the plurality of first electrodes. This results in the dipoles of the plurality of piezoelectric layers being substantially oriented in the dipole direction from the plurality of first electrodes to the plurality of second electrodes. Following poling, the thickness of the wafer is increased, using a low temperature process, such as sputtering, reactive sputtering etc. The temperature of the process being such that degradation of the piezoelectric element is avoided. Examples of material which could be used to increase the thickness of the substrate include alumina AI2O3, hafnia Hf0₂, zirconia Zr0₂, silicates, e.g. TaSiOx, titanates e.g. AITiOx. Reducing the thickness of the wafer, improves the efficiency of the poling procedure, when compared to poling performed when the thickness of the wafer has not been reduced. In addition, this wafer level poling enables more than one piezoelectric elements to be poled at the same time. When a partially released piezoelectric element is driven in the "field up" direction, the piezoelectric element is deformed in a deformation direction which extends from the second electrode 28 towards the first electrode 26, opposite to the above described dipole direction. The partially released piezoelectric element deforms inwards with respect to the chamber, towards the nozzle 18. During the poling process, the applied poling electric field acts to substantially align the spontaneous polarization of the piezoelectric film along the applied poling field direction. The degree of alignment depends on a number of factors, including the structure and orientation of the piezoelectric film, as well as any stresses or local electric fields that the material experiences. In particular, many piezoelectric films such as PZTs, which are grown on Si substrates, are under tensile stresses following cooling from the crystallization temperature. This tensile stress acts to pull the polarization into the plane of the film, so that only a fraction of the material can be poled using top and bottom electrodes. In undamped films, where this tensile stress is released, a larger degree of dipole reorientation is possible on poling. Thus, poling on clamped and fully or partially released structures may not be identical. In addition, many piezoelectric thin films have a preferential polarization direction, often due to an internal field. This internal field produces a lateral shift of the polarization - electric field hysteresis loop, often called imprint, which acts to favour one polarization state over another, and can change the effectiveness of the poling process depending on which electrode is driven in which orientation.

Poling is more effective when applied to a partially released thin film piezoelectric element rather than a clamped thin film piezoelectric element. For example, a partially released thin film piezoelectric element (pinned substantially along its entire perimeter) provides 30 vol% domain reorientation whereas a clamped thin film piezoelectric element provides 4 vol% of domain reorientation. A domain is a region in the ferroelectric film exhibiting homogeneous and uniform spontaneous polarisation. Figure 15 illustrates the percentage change of displacement for partially released thin film piezoelectric elements and the percentage change of the effective transverse piezoelectric coefficient, e3i,f, for clamped thin film piezoelectric elements. Four point probe bending measurements (cantilever bending measurements) have been performed to directly measure e₃i,f for clamped thin film piezoelectric elements.

In the case of partially released thin film piezoelectric elements the amount of displacement caused by the application of an electric field across the piezoelectric thin film has been measured. A fully released piezoelectric film would undergo an expansion in the z direction (perpendicular to the substrate surface) and shrinkage in the plane parallel to the substrate. A partially released thin film piezoelectric element is pinned to the chamber walls, as described above. Therefore, deformation of the piezoelectric thin film translates into a displacement in the z direction (perpendicular to the substrate surface). The displacement of the membrane 20 from its position in the absence of an applied electric field (neutral plane) has been measured. Such a displacement is directly dependent from e₃i,f, as described below.

Even though the membrane 20 is clamped in both x and y directions, along the pressure chambers entire perimeter, the bending stiffness is mainly determined by the piezoelectric response, to the applied electric field, in the x direction, the thin film piezoelectric elements width direction. The stress in the x direction (σ_χ) due to an electric field E, applied across the piezoelectric thin film, is e₃i,f*E. The strain in the x direction (ε_χ) is related to the stress by the modulus of the piezoelectric thin film (Y) : this means that ε_χ is directly proportional to e₃i,f. Qualitatively, ε_χ causes the bending of the thin film piezoelectric element and of the membrane and hence the membrane displacement caused by bending is directly proportional to e₃i,f.

Quantitatively, ε_χ is related to the radius of curvature of bending (p) by the following relationship: ε_χ = c/p where c is the distance of the outer surface of the membrane from the neutral plane. On the other hand, 1/ p = d²y/dx² where y is the membrane displacement. d²y/dx², and hence y, are proportional to the strain, which in turn is proportional to e₃i,f . Thus, the membrane displacement y is directly related to e₃i, f.

As can be appreciated from Figure 15, a slight reduction in e₃i,f is observed for all the clamped piezoelectric thin film element configurations and for both poling field directions (filled triangles in Figure 15) with respect to the comparative unpoled samples, as a result of the fact that the in-plane stresses lead to comparatively more modest amounts of domain switching. The total displacement decreases slightly in magnitude but also becomes less hysteretic after poling, as the domain state is better stabilized. It is anticipated that the poled values will be more stable over the lifetime of the actuator.

Displacement data collected for the partially released thin film piezoelectric element show, on the contrary, significant increases after poling in the "field up" configuration (at various field intensities, at 25°C, 120°C or 150°C, for 20 minutes) with respect to the displacement performances obtained with the unpoled thin film piezoelectric elements.

In the case of partially released thin film piezoelectric elements, a positive "poling effect" can be exploited in order to increase the piezoelectric thin film element performance, by poling in the field up direction the piezoelectric thin film element after patterning the supporting substrate. The larger decrease in displacement after poling in the "field down" direction of partially released thin film elements is likely to be a result of a stronger polarization due to poling. The poling stabilizes one polarization state, and eliminates much of the poling strain and the hysteresis in the displacement - field response. The displacement is reduced for one of two reasons: 1) if the sample originally had little net polarization in that direction, so that poling increased the net polarization, or 2) if the new poling state is less stable and more hysteretic. In summary, for the partially released elements the displacement variation is positive (and much larger in modulus) for the "field up" poling configuration and negative (and again much larger in modulus) for the "field down" poling configuration. The overall effect is not due to the fact that the elements are partially released, otherwise the displacement of also the unpoled samples would have had an improvement in both cases. Here the poling direction plays a fundamental role.

The poling treatment when applied to the partially released piezoelectric thin film element in the "field up" direction is able to change the piezoelectric element's coercive fields, positive and negative, and subsequently the value of the imprint, that is calculated through Equation 1 :

+Ec - (-Ec)

Eⁱ = 2

This is shown by the data reported in Table 1 below. Figure 17 illustrates negative and positive Ec values as measured from a hysteresis loop for a piezoelectric element with a positive imprint. The imprint is directly related to the internal field of the piezoelectric element and can be increased by poling in the same direction as the internal field or decreased if poled in the opposite direction. The positive and negative Ec values are shown annotated in Figure 17, and are used to calculate imprint Ei.

Table 1 shows results for imprint values from two sets of samples thin film piezoelectric element, one being unpoled, and the other being pre-poled in the clamped state in the "field down" direction, respectively.

The initial imprint for the two elements is negative and is, as expected, lower for the unpoled element. Both thin film piezoelectric elements were then partially released and poled at 200kV/cm at 150°C for a 20min. It can be seen that poling the pre-poled element after partial release in the "field down" direction produces no significant change in the value of the imprint. For the initially unpoled, partially released element however, poling results in a large increase in imprint.

Surprisingly, when both elements are poled in the "field up" direction, the gain in imprint is very high and results in a similar value in both cases.

For partially released thin film piezoelectric elements, poling at elevated temperature ("active" poling) is beneficial in the "field up" (pointing from membrane to piezoelectric element) direction. The active poling includes heating at a predetermined temperature and applying an electric field for a sufficient time duration at the predetermined temperature. imprint (kV/cm) Initially pre-poled ("field Initially unpoled element

DOWN") element

Initial, after partial -5.6 -3.2

release after partial release and -6.5 -9.7

poling Yield DOWN' after partial release and +6.6 +7.4

poling Yield UP'

Table 1

The values provided in table 1 have an error of ±0.5 kV/cm. Following poling in the field up direction, a partially released piezoelectric element has a positive imprint which is greater than or equal to 5 kV/cm .

Figure 16 is a graph illustrating the effect of such active poling on the displacement of partially released piezoelectric elements. In order to pole the piezoelectric element, a poling field of 200 kV/cm (20 V/ m) is applied for 20 minutes at 150°C. The thin film piezoelectric elements were fabricated with different piezo-stacks, two elements have PLZT piezoelectric thin film and four elements have PNZT piezoelectric thin films. The total piezoelectric thin film thickness was between 1.7 and 1.9 μηη for all the thin film piezoelectric elements.

The poling effect was investigated in both directions, on different samples. Membrane displacement was measured before and after poling in both "field up" (filled triangles) and "field down" (filled squares) poled piezoelectric elements comprising different piezoelectric stacks. New samples were used for each measurement. Figure 16 illustrates the % change in displacement after poling.

For all the piezoelectric elements, both PLZT and PNZT, poling "field up" increased the membrane displacement, while poling "field down" decreased membrane displacement. PLZT elements show a higher increase when poled "field up" (approximately 36%) than PNZT elements (approximately 20%).

A plurality of piezoelectric elements can be formed on a substrate. Figure 4 illustrates a schematic layout of one row of piezoelectric elements 101, 102, 103, 104, ... 10η, formed on a wafer with individual driving pads 201, 202, 203, 204, ... 20n and a common ground rail 300.

Figure 5 illustrates a schematic layout of a row of piezoelectric elements 101, 102, 103, 104, ... 10η showing details of the connection of the first electrodes 260 of each piezoelectric element to common ground 300 and the second electrodes 280 of each piezoelectric element connected to individual driving pads 201, 202, 203, 204, ... 20n.

Figure 6 illustrates a schematic layout of a row of piezoelectric elements 101, 102, 103, 104, ... 10η showing details of the connection of the second electrodes 280 of each piezoelectric element to common ground 300 and the first electrodes 260 of each piezoelectric element connected to individual driving pads 201, 202, 203, 204, ... 20n.

The electrical track layout illustrated in Figures 4 to 6 enables poling to be performed on a die level and on a wafer level . By "die level" is meant a sub unit of the wafer created during manufacturing, such as for example the smallest element comprising at least one row of nozzles that is separated by dicing from the wafer for assembly into a piezoelectric droplet deposition head. In order to pole the piezoelectric layers, electrical tracks are connected to the rows of individual driving pads 201, 202, 203, 204, ... 20n and connected to a power supply. In one embodiment, for a "field up" configuration, the second electrodes 280 are connected to common ground 300 and the first electrodes 260 are connected to the driving pads. According to one embodiment, one or more of the first or second electrodes are connected to pads, and the pads are configured to be connected to form one or more common ground rail.

Figure 7 illustrates a schematic layout of a row of piezoelectric elements 101, 102, 103, 104, ... 10η having their individual driving pads 201, 202, 203, 204, ... 20n connected via a common connector 350, to the power supply, to apply a poling treatment. The electrical track layout illustrated in Figures 4 to 7 enables the poling process to be performed on an unassembled die. In addition, the electrical track layout illustrated in Figures 4 to 7 enables wafer level poling, and/or further it enables parallel poling of multiple dies before dicing at a wafer level . In one embodiment, the poling is performed after the deposition of the second electrode and the patterning of the piezoelectric layer. For wafer level poling, the driving pads are positioned across the dies on the wafer such that each electrical track can be connected to the power supply and address several dies at once. With all pads connected, simultaneous electrical connection can be established. In one embodiment, for a "field up" configuration, the second electrodes are connected to ground and the first electrodes are connected to the power supply.

Figure 8 illustrates a method of forming rows of piezoelectric elements. At step S901, a plurality of piezoelectric elements are formed in rows on a wafer in accordance with the methods described above. At step S902 the plurality of piezoelectric elements are parallel poled in the "field up" direction.

In one embodiment, the piezoelectric elements are poled at a temperature in the range of 100°C to 180°C for between 5 to 60 minutes. In another embodiment, the piezoelectric elements are poled at a temperature in the range of 120°C to 150°C, for between 20 to 30 minutes. In one embodiment, the piezoelectric elements are poled in an oven in order to achieve the desired temperature range. In another embodiment, the piezoelectric elements are poled on a hot plate in order to achieve the desired temperature range. A field is applied in a "field up" configuration at in excess of the coercive field of the material of the piezoelectric layer, but below the breakdown field of the material of the piezoelectric layer. The field may be supplied as DC, pulsed, or AC. In one embodiment, a poling field of between 10 V/ m to 60 V/ m is applied depending on the poling temperature and duration. In another embodiment, a poling field of between 20 V/ m to 30 V/ m is applied depending on the poling temperature and duration.

Figure 9 illustrates the breakdown field of PLZT (1.1% doping with lanthanum, MPB (morphotropic phase boundary) 52 :48 Zr:Ti ratio), an exemplary material of the piezoelectric layer, vs temperature. As can be seen from Figure 9, the breakdown field decreases with increases in the temperature. Therefore, the breakdown field will depend on the temperature at which the piezoelectric element is poled. At step S903, the wafer is diced to create multiple dies.

The piezoelectric element measured in Figure 9 was incorporated into an inkjet printhead to measure its jetting performance.

Figure 10 illustrates the measured change in performance observed when a "field up" driving scheme is applied to an unpoled piezoelectric inkjet actuator element (triangular shaped markers) compared to when a "field down" driving scheme is applied to a piezoelectric actuator element with an unpoled piezoelectric layer (square shaped markers). The change in performance is determined from data showing drop velocity, jetted at 50 kHz, vs time. As can be seen from Figure 10, the change in performance over time is greater when a "field down" driving scheme is applied, reducing actuator element reliability. When a "field up" driving scheme is applied the change in performance over time is reduced - resulting in an increase in actuator element reliability.

Figure 11 illustrates measured membrane displacement caused by a piezoelectric actuator element in which the piezoelectric layer has been poled in the "field up" direction and the element is operating in an applied "field up" driving scheme (filled triangular shaped markers) compared to a piezoelectric actuator element, in which the piezoelectric layer has not been poled (unpoled), and the element is operating with an applied "field up" driving scheme (outline triangular shaped markers). As can be seen from Figure 11, there is larger membrane displacement in the poled "field up" arrangement (filled triangular shaped markers) resulting in improved performance of the actuator element.

Figure 12 illustrates the measured membrane displacement caused by a piezoelectric actuator element in which a piezoelectric layer has been poled in the "field up" direction and the element is operating with an applied "field up" driving scheme (filled triangular shaped markers); a piezoelectric layer is unpoled and the element is operating with an applied "field up" driving scheme (outline triangular shaped markers); a piezoelectric layer has been poled in the "field down" direction and the element is operating with an applied "field down" driving scheme (filled square shaped markers); a piezoelectric layer is unpoled and the element is operating with an applied "field down" driving scheme (outline square shaped markers). As can be seen from Figure 12, there is larger membrane displacement in the poled "field up" and driven "field up" arrangement (filled triangular shaped markers) resulting in improved performance of the actuator element.

Figure 13 illustrates schematically a cross-section view of a portion of a droplet deposition head die 50 of a piezoelectric droplet deposition head having a known circuit configuration . The piezoelectric actuator element described above can be used in a droplet deposition head die 50 such as illustrated in Figure 13, but is not limited to use in such a droplet deposition head.

The die 50 comprises a fluidic chamber substrate 2 and a nozzle layer 4. The die 50 also comprises a droplet generating unit 6. The die 50 can comprise a plurality of droplet units 6 arranged in arrays thereon as will be described below.

As shown in Figure 13, the droplet generating unit 6 comprises a fluidic chamber 10 and a fluidic inlet port 13 in fluidic communication therewith via a fluidic supply channel 12.

The fluidic inlet port 13 is provided at a top surface 19 of the fluidic chamber substrate 2 towards one end of the fluidic chamber 10 along a length thereof.

In one embodiment, fluid is supplied to the fluidic chamber 10 from the fluidic inlet port 13. In one embodiment, the droplet generating unit 6 further comprises a fluidic channel 14 provided within the fluidic chamber substrate 2 in fluidic communication with the fluidic supply channel 12 and fluidic chamber 10, and arranged to provide a path for ink to flow therebetween.

The droplet generating unit 6 can additionally comprise a fluidic outlet port 16 in fluidic communication with the fluidic chamber 10, whereby a fluid can flow from the fluidic chamber 10 to the fluidic outlet port 16 via a fluidic channel 14 and fluidic return channel 15 formed in the fluidic chamber substrate 2. The fluidic outlet port 16 is provided at the top surface 19 of the fluidic chamber substrate 2 towards an end of the fluidic chamber 10 opposite the end towards which the fluidic inlet port 13 is provided.

Alternatively, the fluidic inlet port 13 and/or fluidic outlet port 16 can be provided within the fluidic chamber 10. Alternatively, a fluid can be supplied and/or returned via port(s) provided at the side(s) of the die.

A droplet deposition head comprising droplet units 6 having fluidic inlet ports 13 and fluidic outlet ports 16, whereby a fluid flows continuously from the fluidic inlet port 13 to the fluidic outlet port 16, along the length of the fluidic chamber 10 can be considered to operate in a recirculation mode, hereinafter "through-flow" mode.

In alternative embodiments, a fluid can be supplied to the fluidic chamber 10 from both fluidic ports 13 and 16 or whereby the die 50 is not provided with a fluidic outlet port 16 and/or fluidic return channel 15 such that substantially all of the fluid supplied to the fluidic chamber 10 is ejected from the nozzle 18, whereby the droplet deposition head can be considered to operate in a non through-flow mode.

The fluidic chamber substrate 2 can comprise silicon (Si), and can, for example, be manufactured from a Si wafer, whilst the associated features, such as the fluidic chamber 10, fluidic channels 12/15, fluidic inlet/outlet ports 13/16 and fluidic channels 14 can be formed using any suitable fabrication process, e.g. an etching process, such as deep reactive ion etching (DRIE) or chemical etching.

Additionally, or alternatively, the associated features of the fluidic chamber substrate 2 can be formed from an additive process e.g. a chemical vapour deposition (CVD) technique (for example, plasma enhanced CVD (PECVD)), atomic layer deposition (ALD), or the features can be formed using a combination of removal and/or additive processes.

In the present example, the nozzle layer 4 is provided at a bottom surface 17 of the fluidic chamber substrate 2, whereby "bottom" is taken to be a surface of the fluidic chamber substrate 2 having the nozzle layer 4 thereon. It will be appreciated that the nozzle layer can be provided on a different surface other than the bottom surface.

The surfaces of various features of the die 50 can be coated with protective or functional materials, such as, for example, a suitable coating of passivation material or wetting material. The droplet generating unit 6 further comprises a nozzle 18 in fluidic communication with the fluidic chamber 10, whereby the nozzle 18 is formed in the nozzle layer 4 using any suitable process e.g. chemical etching, DRIE, laser ablation etc. The droplet generating unit 6 further comprises a membrane 20, provided at the top surface 19 of the fluidic chamber substrate 2, and arranged to cover the fluidic chamber 10. The top surface 19 of the fluidic chamber substrate 2 is taken to be the surface of the fluidic chamber substrate 2 opposite the bottom surface 17. The membrane 20 is deformable to generate pressure fluctuations in the fluidic chamber 10, so as to change the volume within the fluidic chamber 10, such that a fluid can be ejected from the fluidic chamber 10 via the nozzle 18, e.g. as a droplet, and/or for drawing a fluid into the fluidic chamber e.g. via the fluidic inlet port 13. The membrane 20 can comprise any suitable material, such as, for example a metal, an alloy, a dielectric material and/or a semiconductor material. Examples of suitable materials include silicon nitride (Si₃N₄), silicon dioxide (S1O2), aluminium oxide (AI2O3), titanium dioxide (T1O2), silicon (Si) or silicon carbide (SiC). The membrane 20 can additionally or alternatively comprise multiple layers, such as the membrane 200 described above, which comprises a silicon oxide (S1O2) layer 200A, a silicon nitride (Si₃N₄) layer 200B and an aluminium oxide (AI2O3) layer 200C.

The membrane 20 can be formed using any suitable processing technique, such as, for example, ALD, sputtering, electrochemical processes and/or a CVD technique. When the membrane 20 is provided on the top surface 19, apertures 21 corresponding to the fluidic ports 13/16 can be provided in the membrane 20, e.g. using a suitable patterning technique for example during the formation of the membrane 20.

The droplet generating unit 6 further comprises an actuator element 22, such as the actuator element described above, provided on the membrane 20, which is arranged to deform the membrane 20, such that the droplet deposition head operates in roof mode. The actuator element 22 is depicted as a piezoelectric actuator element 22 comprising a piezoelectric layer 24 provided with two electrodes 26 and 28. The piezoelectric layer 24 can, for example, comprise lead zirconate titanate (PZT), however any suitable material can be used. An electrode is provided in the form of a first electrode on the membrane

20. The piezoelectric layer 24 is provided on the first electrode 26, and a second electrode 28 is provided on the piezoelectric layer 24 at the opposite side of the piezoelectric layer 24 to the first electrode 26, however any suitable configuration of the electrodes could be used. When an electric field is applied between the electrodes 26/28, a stress is generated in the piezoelectric layer 24, causing the piezoelectric actuator element 22 to deform on the membrane 20. This deformation changes the volume within the fluidic chamber 10 and fluid droplets can be discharged from the nozzle 18 by driving the piezoelectric actuator element 22 with an appropriate signal. The signal can be supplied from a controller (not shown), for example, as a waveform . The controller can comprise a power amplifier or switching circuit connected to a computer running an application which generates signals in response to print data provided thereto e.g. uploaded thereto by a user.

Further material/layers (not shown) can also be provided in addition to the electrodes 26/28 and piezoelectric layers 24 as required.

A wiring layer comprising electrical connections is provided on the membrane 20, whereby the wiring layer can comprise two or more electrical tracks 32a/32b for example, to connect the second electrode 28 and/or first electrode 26 of the piezoelectric actuator element 22 to the controller, directly or via further drive circuitry.

For example, as schematically depicted in Figure 13, the electrical track 32a and the second electrode 28 are in electrical communication with a first electrical connection in the form of a first electrical contact 35 (e.g. a drive contact), whilst the electrical track 32b and the first electrode 26 are in electrical communication with a second electrical connection in the form of a second electrical contact 37 (e.g. a ground contact). The electrical contacts 35/37 are, in turn, in electrical communication with the controller (not shown). In order to drive the actuator element in the "field up" direction, the second electrode 28 is driven with a negative drive signal . Alternatively, when the first electrical contact 35 is the ground contact and the second electrical contact 37 is the drive electrical contact, in order to drive the actuator element in the "field up" direction, the first electrode 26 is driven with a positive drive signal. In another embodiment, any configuration which results in a negative voltage with reference to the first electrode 26 such as +3V on the second electrode 28, +23V on the first electrode 26 can be used.

Using such a configuration, signals (e.g. a waveforms) can be supplied to the piezoelectric actuator element 22 from the controller for controlled driving thereof.

The electrical tracks 32a/32b comprise a conductive material, e.g. copper (Cu), gold (Ag), platinum (Pt), iridium (Ir), aluminium (Al), titanium nitride (TiN). The electrical tracks 32a/32b can, for example, have a thickness of between 0.01 pm to 2 μιη, and, in some embodiments, the thickness can be between 0.1 μηη and 1 pm, and in further embodiments the thickness can be between 0.3 μηη and 0.7 pm .

The wiring layer can comprise further materials (not shown), for example, a passivation material 33 to protect the electrical tracks 32a/32b e.g. from the environment and from contacting the fluid.

Additionally, or alternatively, the passivation material 33 can comprise a dielectric material provided to electrically insulate electrical tracks 32a/32b from each other e.g. when stacked atop one another or provided adjacent each other.

The passivation material can comprise any suitable material, for example:

The wiring layer can further comprise adhesion electrical tracks 32a/32b, the passivation material 33, the electrodes 26/28 and/or the membrane 20.

Figure 13 is a schematic diagram, and the electrical contacts 35/37 can be deposited on the droplet deposition head die 50 using any suitable technique and in any suitable configuration . The electrical contacts 35/37 can take the form of bond pads, tracks or terminal pins formed of a conductive material e.g. copper (Cu), gold (Au), platinum (Pt), aluminium (Al) etc.

Furthermore, the electrical contacts 35/37 can be deposited atop the passivation material 33, whereby electrical vias 39 provide electrical communication between the electrical contacts 35/37 and the electrical tracks 32a/32b. Alternatively, the contacts can, for example, be provided directly atop the electrical tracks. Although not explicitly described, further materials can be provided within the wiring layer to prevent unwanted electrical contact between the electrical tracks 32a/32b and other materials as required. The materials within the wiring layer (e.g. the electrical tracks, passivation material, adhesion material and/or electrical contacts etc.) can be provided using any suitable fabrication technique such as, for example, sputtering, CVD, PECVD, laser ablation etc. Furthermore, any suitable patterning technique can be used as required (e.g. providing a mask during sputtering and/or etching). The droplet deposition head die 50 can comprise a plurality of droplet units

6. Therefore, the fluidic chamber substrate 2 comprises partition walls 31 provided between each of the droplet units 6 along the length direction thereof.

The droplet deposition head die 50 can comprise further features not described herein. For example, a capping substrate (not shown) can be provided atop the fluidic chamber substrate 2, for example at the top surface 19, the membrane 20 and/or the wiring layer to cover the piezoelectric actuator element 22 and to further protect the piezoelectric actuator element 22. The capping substrate can further define fluidic channels for supplying fluid to the fluidic inlet ports 13 e.g. from a fluid reservoir and for receiving fluid from the fluidic outlet port 16, whereby the capping substrate can also function as a fluid manifold.

The droplet deposition head embodiments described above with reference to Figure 13 can be used in various types of printer. Two notable types of printer are :

a) a page-wide printer, where droplet deposition heads in a single pass cover the entire width of the print medium, with the print medium (tiles, paper, fabric, or other example, in one piece or multiple pieces for example) passing in the direction of printing underneath the droplet deposition heads; and b) a scanning printer, where one or more droplet deposition heads pass back and forth on a printbar (or more than one printbar, for example arranged one behind the other in the direction of motion of the print medium), perpendicular to the direction of movement of the print medium, whilst the print medium advances in increments under the droplet deposition heads, and being stationary whilst the droplet deposition head scans across. There can be large numbers of droplet deposition heads moving back and forth in this type of arrangement, for example 16 or 32, or other numbers.

In both scenarios, the droplet deposition heads can be mounted on printbar(s) to print several different fluids, such as but not limited to, different colours, primers, fixatives, functional fluids or other special fluids or materials. Different fluids can be ejected from the same printhead, or separate printbars can be provided for each fluid or each colour for example.

Other types of printer can include 3D printers for printing fluids comprising polymer, metal, ceramic particles or other materials in successive layers to create solid objects, or to build up layers of an ink that has special properties, for example to build up conducting layers on a substrate for printing electronic circuits and the like. Post- processing operations can be provided to cause conductive particles to adhere to the pattern to form such circuits. Figure 14 shows a schematic view of a printer 440 coupled to a source of data for printing, such as a host PC 460. A droplet deposition head circuit board 180 is shown having one or more actuator elements 480, for example a piezoelectric actuator element described above, and a droplet deposition head circuit 470. Printer circuitry 170, is coupled to the droplet deposition head circuit board, and coupled to a processor 430 for interfacing with the host, and for synchronizing drive of actuator elements and location of the print media. This processor is coupled to receive data from the host, and is coupled to the droplet deposition head circuit board to provide synchronizing signals at least. The printer also has a fluid supply system 420 coupled to the droplet deposition head, and a media transport mechanism and control part 400, for locating the print medium 410 relative to the droplet deposition head. This can include any mechanism for moving the droplet deposition head, such as a movable printbar. It will be understood that whilst various concepts are described above with reference to an inkjet printhead, such concepts are not limited to inkjet printheads, but can be applied more broadly in printheads, or more broadly still in droplet deposition heads, for any suitable application. As noted above, droplet deposition heads suitable for such alternative applications can be generally similar in construction to printheads, with some adaptations made to handle the specific fluid in question. The preceding description should therefore be understood as providing non-limiting examples of applications in which such a droplet deposition head can be used. In addition, the same principles apply to benefit sensor devices. Opposite to the piezoelectric effect in an actuator, in a sensor a voltage or charge is created across the piezoelectric thin film element when a force is applied to deform it. Such sensors may be pressure sensors or accelerometers, for example. In a pressure sensor, there is a net bending force on the device that compresses the piezoelectric element due to a pressure difference, while in accelerometers an attached seismic mass amplifies the forces. In a sensor, the same benefits as described in the aforegoing description may be obtained by poling a piezoelectric thin film element such as to orient the dipoles in a net dipole direction. By arranging the sensor such that a force is applied to the piezoelectric thin film element such that the force acts to deform the poled piezoelectric thin film element in a direction opposite to the net dipole direction, an electric field is generated across the film .

It will be clear to one skilled in the art that many improvements and modifications can be made to the foregoing exemplary embodiments without departing from the scope of the present techniques.

According to one embodiment, the poling electric field is greater than or equal to a coercive field of a material of the piezoelectric layer and less than a field strength at which breakdown occurs in said material of the piezoelectric layer.

According to one embodiment, the poling electric field is in a range from 1 to 20 times the coercive field of a material of said piezoelectric layer.

According to one embodiment, the poling electric field is in a range from 1 to 10 times the coercive field of a material of the piezoelectric layer. According to one embodiment, the poling electric field is equal to or greater than 3 times the coercive field of a material of the piezoelectric layer.

According to one embodiment, the poling electric field is greater than 10

According to one embodiment, the poling electric field is applied at a temperature in a range from 100°C to 200°C, and for a period of time in a range from range 1 to 60 minutes.

According to one embodiment, the period of time comprises a range from 1 to 30 minutes. According to one embodiment, the poling electric field is applied whilst the piezoelectric layer is cooled to a temperature less than 40 °C.

According to one embodiment, the piezoelectric thin film element is in a partially released configuration prior to poling the piezoelectric layer.

According to one embodiment, the piezoelectric layer comprises PZT (lead zirconate titanate).

According to one embodiment, the piezoelectric layer is formed by chemical solution deposition.

According to one embodiment, the method further comprises: filling, either wholly or partially, the cavities following poling of the piezoelectric layer. According to one embodiment, the method further comprises: increasing the thickness of the substrate, following poling of the piezoelectric layer.

According to one embodiment, the poling electric field is greater than or equal to a coercive field of said piezoelectric material and less than the field strength at which breakdown occurs in said piezoelectric material . According to one embodiment, the poling electric field is in a range from 1 to 20 times the coercive field of the piezoelectric material.

According to one embodiment, the poling electric field is in a range from 1 to 10 times the coercive field of the piezoelectric material.

According to one embodiment, the poling electric field is equal to or greater than 3 times the coercive field of the piezoelectric material.

According to one embodiment, the poling electric field is greater than 10

According to one embodiment, the period of time comprises a range from 1 to 30 minutes.

According to one embodiment, the poling electric field is applied whilst the piezoelectric material is cooled to a temperature less than 40 °C.

According to one embodiment, one or more of the plurality of first or second electrodes are connected to pads that are configured to be connected to form one or more common rail.

According to one embodiment, the method further comprises dicing said wafer to form a plurality of dies, each die comprising an array of the piezoelectric thin film elements; and coupling the first and second electrodes of each piezoelectric thin film element to a power supply operable to provide drive signals to the first and second electrodes such that the second electrode is at a lower potential relative to the first electrode when the piezoelectric thin film element is deformed.

According to one embodiment, the piezoelectric layer is deposited by chemical solution deposition.

Claims

1. A method of forming a piezoelectric thin film element, the method comprising :

depositing a layer of first electrode material on a substrate;

depositing a layer of piezoelectric material on said first electrode material; depositing a layer of second electrode material on said piezoelectric material;

patterning said second electrode material and said piezoelectric material to form a second electrode and a piezoelectric layer;

patterning said first electrode material to form a first electrode;

patterning said substrate to form a cavity below said first electrode of said piezoelectric thin film element, such that said piezoelectric thin film element is partially released; and

poling said piezoelectric layer, by heating said piezoelectric layer to a temperature in a range from 100°C to 200°C and applying a poling electric field across said piezoelectric layer from said first electrode to said second electrode, wherein said second electrode is at a lower potential relative to said first electrode, to orient dipoies of said piezoelectric layer in a dipole direction from said first electrode to said second electrode.

2. A method of forming a plurality of piezoelectric thin film elements on a wafer, the method comprising :

depositing a layer of first electrode material on said wafer;

patterning said second electrode material and said piezoelectric material to form a plurality of second electrodes and a plurality of piezoelectric layers;

patterning said first electrode material to form a plurality of first electrodes; patterning said wafer to form cavities below said plurality of first electrodes of said plurality of piezoelectric thin film elements, such that said plurality piezoelectric thin film elements are partially released; and

poling said plurality of piezoelectric layers, by heating said plurality of piezoelectric layers to a temperature in a range from 100°C to 200°C and applying a poling electric field across said plurality of piezoelectric layers from said plurality of first electrodes to said plurality of second electrodes, wherein said plurality of second electrodes are at a lower potential relative to said plurality of first electrodes, to orient dipoles of said plurality of piezoelectric layers in a dipole direction from said plurality of first electrodes to said plurality of second electrodes.

3. The method of claim 1 or claim 2, further comprising :

filling, either wholly or partially, said cavity or cavities following poling of said piezoelectric layer or said plurality of piezoelectric layers.

4. The method of any one claims 1 to 3, wherein said poling electric field is greater than or equal to a coercive field of said piezoelectric material and less than a field strength at which breakdown occurs in said piezoelectric material.

5. The method of any one of claim 1 to 4, wherein said poling electric field is in a range from 1 to 20 times said coercive field of said piezoelectric material.

6. The method of any one of claim 1 to 5, wherein said poling electric field is in a range from 1 to 10 times said coercive field of said piezoelectric material.

7. The method of any one of claim 1 to 6, wherein said poling electric field is equal to or greater than 3 times said coercive field of said piezoelectric material.

8. The method of any one of claims 1 to 7, wherein said poling electric field is greater than 10 V/ m .

9. The method of any one of claims 1 to 8, further comprising :

applying said poling electric field for a period of time in a range from 1 to 60 minutes.

10. The method of claim 9, wherein said period of time comprises a range from 1 to 30 minutes.

11. The method of any one of claims 1 to 10, further comprising : maintaining said poling electric field whilst said piezoelectric material is cooled from said temperature in a range from 100°C to 200°C to a temperature less than 40 °C.

12. The method of any one of claims 1 to 11, wherein said piezoelectric layer or said plurality of piezoelectric layers comprise PZT (lead zirconate titanate).

13. The method of any one of claims 1 to 12, wherein said piezoelectric material is deposited by chemical solution deposition.

14. The method of any one of claims 1 to 13, wherein said piezoelectric material is deposited by a sol-gel method.

15. The method of any one of claims 1 to 14, wherein, during poling, said piezoelectric thin film element or said plurality of piezoelectric thin film elements are deformed in a deformation direction predominantly opposite to said dipole direction.

16. The method of any of claims 2 to 15, wherein one or more of said plurality of first or second electrodes are connected to pads that are configured to be connected to form one or more common rail.

17. The method of any one of claims 2 to 16, further comprising :

dicing said wafer to form a plurality of dies, each die comprising an array of said piezoelectric thin film elements; and

coupling said first and second electrodes of each said piezoelectric thin film element to a power supply operable to provide drive signals to said first and second electrodes such that said second electrode is at a lower potential relative to said first electrode when said piezoelectric thin film element is deformed,

18. The method of any one of claims 1 to 17, further comprising :

forming a membrane between said first electrode material and said wafer.

19. The method of claim 18, wherein said membrane is formed from said wafer.

20. The method of any one of claims 1 to 19, wherein said partially released piezoelectric thin film element comprises a piezoelectric thin film element pinned to said cavities perimeter wall.

21. A method of forming a piezoelectric thin film element, the method comprising :

depositing a layer of first electrode material on a substrate;

patterning said first electrode material to form a first electrode;

patterning said substrate to reduce a thickness of said substrate, such that said piezoelectric thin film element is partially released; and

poling said piezoelectric layer, by heating said piezoelectric layer to a temperature in a range from 100°C to 200°C and applying a poling electric field across said piezoelectric layer from said first electrode to said second electrode, wherein said second electrode is at a lower potential relative to said first electrode, to orient dipoles of said piezoelectric layer in a dipole direction from said first electrode to said second electrode.

22. A method of forming a plurality of piezoelectric thin film elements on a wafer, the method comprising :

depositing a layer of first electrode material on said wafer;

patterning said first electrode material to form a plurality of first electrodes; patterning said wafer to reduce a thickness of said wafer, such that said piezoelectric thin film element is partially released; and

poling said plurality of piezoelectric layers, by heating said piezoelectric layer to a temperature in a range from 100°C to 200°C and applying a poling electric field across said plurality of piezoelectric layers from said plurality of first electrodes to said plurality of second electrodes, wherein said plurality of second electrodes are at a lower potential relative to said plurality of first electrodes, to orient dipoles of said plurality of piezoelectric layers in a dipole direction from said plurality of first electrodes to said plurality of second electrodes.

23. A piezoelectric actuator comprising a piezoelectric thin film element formed by the method of any one of claims 1 to 22.

24. A sensor comprising said piezoelectric thin film element of claim 23.

25. A piezoelectric thin film element comprising :

a first electrode formed on a substrate;

a piezoelectric layer formed on said first electrode by a sol-gel method; and a second electrode formed on said piezoelectric layer;

wherein said substrate is patterned to form cavities below said first electrode of said piezoelectric thin film element, such that said piezoelectric thin film element is partially released,

wherein said piezoelectric layer is poled, such that said piezoelectric layer comprises a positive imprint, and

wherein said first and second electrodes are configured such that said second electrode is at a lower potential relative to said first electrode when said piezoelectric thin film element is deformed in a deformation direction from said second electrode to said first electrode.

26. The piezoelectric thin film element of claim 25, wherein said positive imprint is greater than or equal to 5 kV/cm .

27. A piezoelectric actuator comprising a piezoelectric thin film element of claim 25 or 26.

28. A sensor comprising said piezoelectric thin film element of claim 25 or 26.