EP3389095A1 - Herstellungsverfahren für einen finfet, finfet und vorrichtung mit einem finfet - Google Patents

Herstellungsverfahren für einen finfet, finfet und vorrichtung mit einem finfet Download PDF

Info

Publication number
EP3389095A1
EP3389095A1 EP17166307.3A EP17166307A EP3389095A1 EP 3389095 A1 EP3389095 A1 EP 3389095A1 EP 17166307 A EP17166307 A EP 17166307A EP 3389095 A1 EP3389095 A1 EP 3389095A1
Authority
EP
European Patent Office
Prior art keywords
fin
portions
lateral
alternating layers
growing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP17166307.3A
Other languages
English (en)
French (fr)
Inventor
Etienne DE POORTERE
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
ASML Netherlands BV
Original Assignee
ASML Netherlands BV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by ASML Netherlands BV filed Critical ASML Netherlands BV
Priority to EP17166307.3A priority Critical patent/EP3389095A1/de
Publication of EP3389095A1 publication Critical patent/EP3389095A1/de
Withdrawn legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Definitions

  • the present invention relates to a method of manufacturing a finFET, a finFET and a device comprising a finFET.
  • a lithographic apparatus is a machine that applies a desired pattern onto a substrate, usually onto a target portion of the substrate.
  • a lithographic apparatus can be used, for example, in the manufacture of integrated circuits (ICs).
  • a patterning device which is alternatively referred to as a mask or a reticle, may be used to generate a circuit pattern to be formed on an individual layer of the IC.
  • This pattern can be transferred onto a target portion (e.g. comprising part of, one, or several dies) on a substrate (e.g. a silicon wafer). Transfer of the pattern is typically via imaging onto a layer of radiation-sensitive material (resist) provided on the substrate.
  • resist radiation-sensitive material
  • a single substrate will contain a network of adjacent target portions that are successively patterned.
  • lithographic apparatus include so-called steppers, in which each target portion is irradiated by exposing an entire pattern onto the target portion at one time, and so-called scanners, in which each target portion is irradiated by scanning the pattern through a radiation beam in a given direction (the "scanning"-direction) while synchronously scanning the substrate parallel or anti-parallel to this direction. It is also possible to transfer the pattern from the patterning device to the substrate by imprinting the pattern onto the substrate.
  • Lithographical apparatuses as described may e.g. be applied in the manufacturing process of semiconductor components such as finFETs.
  • a finFET is a component having a channel connecting a source and a drain, the channel typically comprising a thin vertical semiconductor structure, referred to as the fin, which may be enclosed on one or more sides by a gate, the gate being configured to modulate the channel.
  • the use of nanowires or nanosheets has been proposed.
  • the nanowire or nanosheet architecture however suffers from the drawback that its manufacturing process is significantly more complex, due to the fact that the nanowires/nanosheets need to be disconnected from each other.
  • the current that can be drawn from a channel having a nanowire/nanosheet architecture will typically be lower than the current that can be drawn from a channel having a fin-shaped cross-section.
  • finFET fin field effect transistor
  • finFET fin field effect transistor
  • a finFET comprising:
  • FIG. 1 schematically depicts a lithographic apparatus according to one embodiment of the invention.
  • the lithographic apparatus comprises an illumination system IL, a support structure MT, a substrate table WT and a projection system PS.
  • the illumination system IL is configured to condition a radiation beam B.
  • the support structure MT is constructed to support a patterning device MA and is connected to a first positioning device PM configured to accurately position the patterning device MA in accordance with certain parameters.
  • the substrate table WT is constructed to hold a substrate W, e.g., a resist-coated wafer, and is connected to a second positioner PW configured to accurately position the substrate W in accordance with certain parameters.
  • the projection system PS is configured to project a pattern imparted to the radiation beam B by patterning device MA onto a target portion C (e.g. comprising one or more dies) of the substrate W.
  • the illumination system IL may include various types of optical components, such as refractive, reflective, magnetic, electromagnetic, electrostatic or other types of optical components, or any combination thereof, for directing, shaping, or controlling radiation.
  • optical components such as refractive, reflective, magnetic, electromagnetic, electrostatic or other types of optical components, or any combination thereof, for directing, shaping, or controlling radiation.
  • the illumination system IL receives the radiation beam B from a radiation source SO.
  • the radiation source SO and the lithographic apparatus may be separate entities, for example when the radiation source SO is an excimer laser. In such cases, the radiation source SO is not considered to form part of the lithographic apparatus and the radiation beam B is passed from the radiation source SO to the illumination system IL with the aid of a beam delivery system BD comprising, for example, suitable directing mirrors and/or a beam expander. In other cases the radiation source SO may be an integral part of the lithographic apparatus, for example when the radiation source SO is a mercury lamp.
  • the radiation source SO and the illumination system IL, together with the beam delivery system BD if required, may be referred to as a radiation system.
  • the illumination system IL may comprise an adjuster AD for adjusting the angular intensity distribution of the radiation beam.
  • an adjuster AD for adjusting the angular intensity distribution of the radiation beam.
  • the illumination system IL may comprise various other components, such as an integrator IN and a condenser CO.
  • the illumination system IL may be used to condition the radiation beam B, to have a desired uniformity and intensity distribution in its cross-section.
  • UV radiation e.g. having a wavelength of or about 365, 355, 248, 193, 157 or 126 nm
  • EUV radiation e.g. having a wavelength in the range of 5-20 nm
  • particle beams such as ion beams or electron beams.
  • the support structure MT supports, i.e. bears the weight of, the patterning device MA.
  • the support structure MT holds the patterning device MA in a manner that depends on the orientation of the patterning device MA, the design of the lithographic apparatus, and other conditions, such as for example whether or not the patterning device MA is held in a vacuum environment.
  • the support structure MT can use mechanical, vacuum, electrostatic or other clamping techniques to hold the patterning device MA.
  • the support structure MT may be a frame or a table, for example, which may be fixed or movable as required.
  • the support structure MT may ensure that the patterning device MA is at a desired position, for example with respect to the projection system PS.
  • patterning device used herein should be broadly interpreted as referring to any device that can be used to impart a radiation beam with a pattern in its cross-section such as to create a pattern in a target portion C of the substrate W. It should be noted that the pattern imparted to the radiation beam B may not exactly correspond to the desired pattern in the target portion C of the substrate W, for example if the pattern includes phase-shifting features or so called assist features. Generally, the pattern imparted to the radiation beam B will correspond to a particular functional layer in a device being created in the target portion C, such as an integrated circuit.
  • the patterning device MA may be transmissive or reflective.
  • Examples of patterning devices include masks, programmable mirror arrays, and programmable LCD panels.
  • Masks are well known in lithography, and include mask types such as binary, alternating phase-shift, and attenuated phase-shift, as well as various hybrid mask types.
  • An example of a programmable mirror array employs a matrix arrangement of small mirrors, each of which can be individually tilted so as to reflect an incoming radiation beam in different directions. The tilted mirrors impart a pattern in the radiation beam B which is reflected by the mirror matrix.
  • projection system used herein should be broadly interpreted as encompassing any type of projection system, including refractive, reflective, catadioptric, magnetic, electromagnetic and electrostatic optical systems, or any combination thereof, as appropriate for the exposure radiation being used, or for other factors such as the use of an immersion liquid or the use of a vacuum.
  • the lithographic apparatus is of a transmissive type (e.g. employing a transmissive mask).
  • the lithographic apparatus may be of a reflective type (e.g. employing a programmable mirror array of a type as referred to above, or employing a reflective mask).
  • the lithographic apparatus may be of a type having two (dual stage) or more substrate tables (and/or two or more mask tables). In such "multiple stage" machines the additional tables may be used in parallel, or preparatory steps may be carried out on one or more tables while one or more other tables are being used for exposure.
  • An additional table may be arranged to hold at least one sensor, instead of holding a substrate W.
  • the at least one sensor may be a sensor to measure a property of the projection system PS, a sensor to detect a position of a marker on the patterning device MA relative to the sensor or may be any other type of sensor.
  • the additional table may comprise a cleaning device, for example for cleaning part of the projection system PS or any other part of the lithographic apparatus.
  • the lithographic apparatus may also be of a type wherein at least a portion of the substrate W may be covered by a liquid having a relatively high refractive index, e.g. water, so as to fill a space between the projection system PS and the substrate W.
  • a liquid having a relatively high refractive index e.g. water
  • An immersion liquid may also be applied to other spaces in the lithographic apparatus, for example, between the patterning device MA and the projection system PS. Immersion techniques are well known in the art for increasing the numerical aperture of projection systems.
  • immersion as used herein does not mean that a structure, such as a substrate W, must be submerged in liquid, but rather only means that liquid is located between the projection system PS and the substrate W during exposure.
  • the radiation beam B is incident on the patterning device MA, which is held on the support structure MT, and is patterned by the patterning device MA. Having traversed the support structure MT, the radiation beam B passes through the projection system PS, which focuses the beam onto a target portion C of the substrate W.
  • the substrate table WT can be moved accurately, e.g. so as to position different target portions C in the path of the radiation beam B.
  • the first positioner PM and another position sensor (which is not explicitly depicted in Figure 1 ) can be used to accurately position the patterning device MA with respect to the path of the radiation beam B, e.g.
  • movement of the support structure MT may be realized with the aid of a long-stroke module and a short-stroke module, which form part of the first positioner PM.
  • the long-stroke module provides movement of the support structure MT over a large range with limited accuracy (coarse positioning)
  • the short-stroke module provides movement of the support structure MT relative to the long-stroke module over a small range with high accuracy (fine positioning).
  • movement of the substrate table WT may be realized using a long-stroke module and a short-stroke module, which form part of the second positioner PW.
  • the support structure MT may be connected to a short-stroke actuator only, or may be fixed.
  • Patterning device MA and substrate W may be aligned using mask alignment marks M1, M2 and substrate alignment marks P1, P2.
  • substrate alignment marks P1, P2 as illustrated occupy dedicated target portions, they may be located in spaces between target portions C.
  • Substrate alignment marks P1, P2 are known as scribe-lane alignment marks, when they are located in spaces between the target portions C.
  • the mask alignment marks M1, M2 may be located between the dies.
  • the depicted apparatus could be used in at least one of the following modes:
  • the step mode, the support structure MT and the substrate table WT are kept essentially stationary, while an entire pattern imparted to the radiation beam B is projected onto a target portion C at one time (i.e. a single static exposure).
  • the substrate table WT is then shifted in the X and/or Y direction so that a different target portion C can be exposed.
  • the maximum size of the exposure field limits the size of the target portion C imaged in a single static exposure.
  • the scan mode, the support structure MT and the substrate table WT are scanned synchronously while a pattern imparted to the radiation beam B is projected onto a target portion C (i.e. a single dynamic exposure).
  • the velocity and direction of the substrate table WT relative to the support structure MT may be determined by the (de-)magnification and image reversal characteristics of the projection system PS.
  • the maximum size of the exposure field limits the width (in the non-scanning direction) of the target portion C in a single dynamic exposure, whereas the length of the scanning motion determines the height (in the scanning direction) of the target portion C.
  • the support structure MT is kept essentially stationary holding a programmable patterning device MA, and the substrate table WT is moved or scanned while a pattern imparted to the radiation beam B is projected onto a target portion C.
  • a pulsed radiation source is employed and the programmable patterning device MA is updated as required after each movement of the substrate table WT or in between successive radiation pulses during a scan.
  • This mode of operation can be readily applied to maskless lithography that utilizes programmable patterning device, such as a programmable mirror array of a type as referred to above.
  • the lithographic apparatus further includes a control unit which controls the actuators and sensors described.
  • the control unit also includes signal processing and data processing capacity to implement desired calculations relevant to the operation of the lithographic apparatus.
  • the control unit will be realized as a system of many sub-units. Each sub-unit may handle the real-time data acquisition, processing and/or control of component within the lithographic apparatus. For example, one sub-unit may be dedicated to servo control of the second positioner PW. Separate sub-units may handle the short-stroke module and the long-stroke module, or different axes. Another sub-unit may be dedicated to the readout of the position sensor IF.
  • Overall control of the lithographic apparatus may be controlled by a central processing unit, communicating with the sub-units, with operators and with other apparatuses involved in the lithographic manufacturing process.
  • Figure 2 depicts a manufacturing process for a finFET according to an embodiment of the present invention.
  • Figure 2 (a) schematically depicts a semiconductor substrate 100 comprising a first material 110, e.g. a silicon substrate that can be applied to manufacture a finFET.
  • a first material 110 e.g. a silicon substrate that can be applied to manufacture a finFET.
  • a fin refers to a structure having a certain height, in the indicated Z-direction, and extending in a longitudinal direction perpendicular to the plane of the drawing.
  • the fin 120 has a width W in a direction perpendicular to the longitudinal direction, i.e. the X-direction, also referred to as the lateral direction.
  • four fins 120, separated by trenches 130 are schematically shown.
  • Such a structure may e.g.
  • the etching being indicated by the arrows 150.
  • the resulting structure is schematically shown in Figure 2 (c) .
  • layers of the same material as the first material 110 and layers of another material are alternatingly grown or deposited in the trench or trenches.
  • alternating layers of two different materials are deposited in the trench or trenches.
  • the materials as applied to grow the alternating layers have different properties with respect to etching.
  • the first material may e.g. be silicon (Si), whereas the other material is silicon-germanium (SiGe).
  • Figure 2 (d) schematically shows the trenches 130 being provided with alternating layers of a first material (Si) and a second material (SiGe).
  • the first material 110 is assumed to be Si, as indicated.
  • portions of the alternating layers are removed, thereby forming a lateral fin or lateral fins adjacent to the already existing fins, the lateral fin or fins comprising a stack which comprises alternating portions of the first material (e.g. Si) and portions of the second material.
  • the removal of the portions of the alternating layers may be realized by applying a hard mask 240 covering the fins and part of the alternating layers and subsequently etching the portions of the alternating layers that are not covered by the hard mask 240 (the etching being indicated by the arrows 250). This process is schematically illustrated in Figure 2 (e) .
  • a structure as shown in Figure 2 (f) is obtained.
  • two lateral fins 220 are provided adjacent each fin 120, the two lateral fins being arranged adjacent opposite sides of the fin 120.
  • a lateral fin refers to a fin positioned adjacent a fin in the lateral direction, i.e. the indicated X-direction, perpendicular to the longitudinal direction.
  • lateral fins 220 are created adjacent the existing fins 120, the lateral fins having alternating portions of silicon (Si) and silicon-germanium (SiGe.)
  • a selective etching indicated by the arrows 350 is applied to remove the portions of the lateral fins 220 that are made of the second material (SiGe).
  • the material of which the second portions of the lateral fin or fins 220 is made should be selected in such manner that it can be removed, e.g. by means of etching, while the portions of the lateral fins 220 that are made of the first material are substantially preserved.
  • a fin structure 140 is created comprising the fin 120 and one or more lateral fin portions 145 formed by the portions of the first material.
  • four fin structures 140 are obtained.
  • the fin structure as shown in Figure 2 (g) may then be used as a channel in a finFET component.
  • the manufacturing process according to an embodiment of the present invention further comprises the step of providing an insulation layer on the fin structure e.g. by means of an oxide deposition.
  • the manufacturing process according to the present invention may further comprise the step of depositing an insulator and a gate on the fin structure, the gate being e.g. a highly n+-doped poly silicon layer, or containing metals such as Al or Ti, see e.g. T. Skotnicki, et al., (STMicroelectronics) T-ED, vol. 55, no. 1, p. 96, 2008 .
  • a sacrificial material may be applied, having the desired gate geometry, the sacrificial material being replaced by the actual gate at a later step.
  • Figure 2 (h) schematically shows the fin structure as can be obtained by the manufacturing process according to the present invention, combined with a gate 400. Alternative methods to arrive at a fin structure having one or more lateral fin portions will now be described.
  • a fin structure as schematically shown in Figure 2 (h) may be obtained by the application of two additional manufacturing steps. These additional step are schematically illustrated in F igures 2 (i),(j) and (k) .
  • alternating layers as applied to realize the superlattice in the trench or trenches are made of two different materials, referred to as materials B and C, both being different from the first material that is used to form the fin, a structure as schematically shown in Figure 2 (h) can be obtained by means of the processing steps as described above.
  • Figure 2 (i) schematically shows fins 120 made of Si, each fin having on both sides a lateral fin 222 comprising alternating portions of a material B, also referred to as the second material, and a material C, also referred to as the third material.
  • a mask 240 is further shown, covering the fins 120 and lateral fins 222.
  • a first additional step the structure as schematically shown in Figure 2 (i) is subjected to an etching to remove the material B or second material (indicated by the arrow 352 in Figure 2 (i) ), leaving only the lateral fin portions 222 of the material C or the third material.
  • the resulting structure is schematically shown in Figure 2 (j) .
  • lateral fin portions of the first material e.g. Si
  • Such a lateral growth of the lateral fin portions of the first material may e.g. be realized by epitaxy.
  • a structure as shown in Figure 2 (k) is obtained.
  • this structure is similar to the structure shown in Figure 2 (f) , this structure have lateral fin portions of the same material as the fin 120, Si in the example shown.
  • an array of fins separated by trenches filled with superlattices are applied.
  • the process starts by etching the trenches in a substrate comprising a first material or a layer of a first material.
  • the array of fins and superlattices as applied may also be obtained in an alternative manner. This is illustrated in Figure 3 .
  • Figure 3 (a) schematically depicts a semiconductor substrate 100 comprising a first material 110, e.g. a silicon substrate that can be applied to manufacture a finFET.
  • a first material 110 e.g. a silicon substrate that can be applied to manufacture a finFET.
  • a stack of alternating layers of a second material and either the first material or a third material is deposited or grown on a surface of the first material 110.
  • the first material may e.g. be in the shape of a layer.
  • Figure 3 (b) illustrating a cross-sectional view through a semiconductor substrate 100 comprising a first material 110 and a stack of alternating layers of a second material (referred to as material B) and a third material (referred to as material C).
  • fin shaped cavities are etched in the stack of alternating layers by removing portions of the first material 110.
  • This can e.g. be done by the application of a hard mask 340 and a suitable etchant, indicated by the arrows 350.
  • the resulting structure is schematically shown in Figure 3 (c).
  • Figure 3 (c) schematically shows a portion of a semiconductor substrate 100 comprising a first material 110 and alternating layers of a second material (B) and of a third material (C) and fin shaped cavities 350, obtained by removing of portions of the first material 110, e.g. by means of etching, by an appropriate covering of the stack of layers by means of a hard mask 340.
  • the fin shaped cavities 350 extend to the surface of the first material 110; i.e. the etching 350 is preformed through the entire stack or superlattice of alternating layers of materials B and C.
  • fins of the first material 110 are grown in the fin shaped cavities 350, indicated by the arrows 360 in Figure 3 (c) .
  • the fins of the first material 110 are grown to the same height level as the upper layer of the stack of materials B and C, a structure similar to the structure shown in Figure 2 (d) is obtained. Note that the structure of Figure 2 (d) describes a stack of alternating layers of Si and SiGe, but, as described with reference to Figures 2 (i)-(k) , a stack of alternating layers of materials B and C may be applied as well.
  • the process as described in Figures 2(e)-(g) or the process as described in Figures 2 (i) -(k) (followed by the process of Figure 2(f) ), depending on whether the superlattice comprises layers of the first material or not, can be applied, ultimately resulting in fin structures as shown in Figure 2 (g) .
  • the material C would correspond to the first material 110 of the substrate. In that case, the growing process would not only start from the bottom of the fin shaped cavity but also from the side portions of the fin shaped cavity that are made of the first material.
  • FIG. 2 (h) schematically shows the fin structure as can be obtained by any of the manufacturing process according to the present invention described above, combined with a gate 400.
  • the fin structures 140 are symmetrical about the fins 120. It can be pointed out that this is not required. Using the above described manufacturing method, and applying the appropriately sized hard masks, other fin structures may be realized as well.
  • Figure 4 schematically shows three alternative fin structures 400 that may be realized using the manufacturing method according to the present invention.
  • Figure 4 (a) shows a cross-sectional view of a fin structure 400 which can be applied as a channel in a finFET, the fin structure having a fin 420 comparable to fin 420 of Figure 2 , and having two lateral fin portions 430 arranged on the same side 420.1 of the fin 420.
  • the fin structure as realized by means of the manufacturing method according to the present invention need not be symmetrical about a central axis, such as an axis 440 through the fin 420.
  • the number of lateral fin portions 450 on both sides of a central fin 460 of the fin structure 400 need not be the same.
  • the fin structure 400 comprises one lateral fin portion adjacent side 460.1 of the central fin 460 and two lateral fin portions adjacent an opposite side 460.2 of the central fin 460.
  • the vertical position, i.e. along the Z-direction, and thickness T1 of the lateral fin portions 450 can be selected.
  • the stack of alternating layers or superlattice as applied on both sides of the fin 460 should be different. More specifically, the bottom layer of the stack of alternating layers should e.g.
  • Such an asymmetric pair of superlattices can e.g. be realized by, in a first step, covering the right side trench and fin 460 with a hard mask. In a second step, depositing a layer of a second material, e.g. SiGe, as a bottom layer in the left side trench. In a third step, removing the mask and depositing the alternating stack of layers as required in both trenches, e.g. starting with a layer of SiGe. By doing so, the bottom layer of SiGe in the left side trench will be thicker, enabling in an elevated position of the lateral fin portion on the left. As a result process, the lateral fin portions of the first material of the lateral fin on the left side can have a different vertical position than the lateral fin portions of the first material of the lateral fin on the right side of the fin 460.
  • a second material e.g. SiGe
  • the width of the lateral fins 470 as applied on both sides of a central fin 460, w1, w2, need not be the same.
  • Such a structure may e.g. be obtained by an asymmetrical positioning of a hard mask, such as hard mask to remove the stack.
  • the fin structures as can be obtained by means of the manufacturing method according to the present invention may provide several advantages over known fins or fin structures.
  • Figure 5 schematically shows three types of channel cross-sections as known in the art, shown in (a), (b) and (c) and a fin structure 600, shown in (d), as obtained by means of the manufacturing process according to the present invention.
  • the same device height is assumed to be available; for (c) and (d), the top-down area , indicated by the width W top-down is the same.
  • a second fin or nanowire stack has to be added, with a gate separating the two fins or stacks, thereby increasing top-down area significantly, as illustrated in Figure 5 (e) .
  • the largest channel cross-section may be realized by the fin structure 600 obtained by means of the manufacturing process according to the present invention.
  • the fin or fin structure needs to be comparatively slim, in order for the material constituting the fin or fin structure to be close to the gate.
  • increasing the width W of the fin 610 shown in Figure 5 (a) would not necessarily result in an improved performance of the gate as the inner portion of such an enlarged fin would be further away from the gate.
  • the fin structure 600 shown in Figure 5 (d) does not suffer from this drawback because the gate can extend in between the lateral fins 620, thus enabling all material of the channel to be close to the gate.
  • the fin structure of Figure 5 (d) is believed to be more easily manufactured.
  • the nanosheets and nanowires as shown in Figures 5 (b) and (c) need to be kept spaced apart and to be kept from collapsing during the manufacturing process. Because of this, the deposition of an isolation layer, e.g. a gate spacer dielectric isolating the gate from the source and the drain of the finFET, on the side of the gate (formed by the nanowires or nanosheets) may be difficult, due to the fact that the nanowires or nanosheets are spaced apart.
  • an isolation layer e.g. a gate spacer dielectric isolating the gate from the source and the drain of the finFET
  • Another challenge in transistor technology is to increase the current drawn by the transistor, preferably without increasing the height of the transistor or the parasitic capacitance.
  • transistors having nanowires or nanosheets as a channel both suffer from having a higher parasitic capacitance at a matched current.
  • the available cross-section of the fin structure 600 i.e. the cross-section available for a current through the channel formed by the fin structure, may be substantially larger than the cross-section of the combined nanowires 630 or combined nanosheets 640.
  • the manufacturing process according to the present invention enables the top-down width of the fin structure to be tuned to any desired need.
  • a device size can only be tuned in discrete increments, i.e. one can implement an integer number of fins 610 to arrive at a desired channel cross-section.
  • the cross-section of the fin structure e.g. structure 620 may be tuned because the manufacturing method provides in the flexibility to select the number of lateral fin portions, the position of the lateral fin portions and the dimensions of the lateral fin portions, the latter two in a substantially continuous manner.
  • the manufacturing methods according to the present invention enable the manufacturing of a fin structure of a first material, whereby, during the process, a second and optionally a third sacrificial material is used, as described above.
  • Table 1 First material (fin structure) Material
  • Material B Material C Si AlN GaAlN SiGe AlN GaAlN InGaAs Si SiGe GaAs Si SiGe
  • the fin structure as obtained by means of a manufacturing process according to the present invention may have a height in a range between 40 nm and 100 nm, preferably in a range between 50 and 70 nm.
  • the one or more lateral fins, e.g. lateral fins 145, 330, 350, 370, 620 may e.g. have a width in a range between 3 nm and 15nm and a height between 3 and 10 nm.
  • lithographic apparatus in the manufacture of ICs
  • the lithographic apparatus described herein may have other applications, such as the manufacture of integrated optical systems, guidance and detection patterns for magnetic domain memories, flat-panel displays, liquid-crystal displays (LCDs), thin-film magnetic heads, etc.
  • LCDs liquid-crystal displays
  • any use of the terms “wafer” or “die” herein may be considered as synonymous with the more general terms “substrate” or "target portion”, respectively.
  • the substrate W referred to herein may be processed, before or after exposure, in for example a track (a tool that typically applies a layer of resist to a substrate and develops the exposed resist), a metrology tool and/or an inspection tool. Where applicable, the disclosure herein may be applied to such and other substrate processing tools. Further, the substrate W may be processed more than once, for example in order to create a multi-layer IC, so that the term substrate W used herein may also refer to a substrate that already contains multiple processed layers.
  • imprint lithography a topography in a patterning device MA defines the pattern created on a substrate.
  • the topography of the patterning device may be pressed into a layer of resist supplied to the substrate whereupon the resist is cured by applying electromagnetic radiation, heat, pressure or a combination thereof.
  • the patterning device MA is moved out of the resist leaving a pattern in it after the resist is cured.
  • the invention may take the form of a computer program containing one or more sequences of machine-readable instructions describing a method as disclosed above, or a data storage medium (e.g. semiconductor memory, magnetic or optical disk) having such a computer program stored therein.
  • a data storage medium e.g. semiconductor memory, magnetic or optical disk

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
EP17166307.3A 2017-04-12 2017-04-12 Herstellungsverfahren für einen finfet, finfet und vorrichtung mit einem finfet Withdrawn EP3389095A1 (de)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP17166307.3A EP3389095A1 (de) 2017-04-12 2017-04-12 Herstellungsverfahren für einen finfet, finfet und vorrichtung mit einem finfet

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP17166307.3A EP3389095A1 (de) 2017-04-12 2017-04-12 Herstellungsverfahren für einen finfet, finfet und vorrichtung mit einem finfet

Publications (1)

Publication Number Publication Date
EP3389095A1 true EP3389095A1 (de) 2018-10-17

Family

ID=58547368

Family Applications (1)

Application Number Title Priority Date Filing Date
EP17166307.3A Withdrawn EP3389095A1 (de) 2017-04-12 2017-04-12 Herstellungsverfahren für einen finfet, finfet und vorrichtung mit einem finfet

Country Status (1)

Country Link
EP (1) EP3389095A1 (de)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20210384320A1 (en) * 2019-04-29 2021-12-09 International Business Machines Corporation Transistor device having a comb-shaped channel region to increase the effective gate width
DE112020000212B4 (de) 2019-02-27 2022-03-24 International Business Machines Corporation Verfahren zur herstellung eines transistorkanals mit vertikal gestapelten nanoschichten, die durch finnenförmige brückenzonen verbunden sind
GB2595160B (en) * 2019-02-27 2024-05-22 Ibm Transistor channel having vertically stacked nanosheets coupled by fin-shaped bridge regions

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050191795A1 (en) * 2004-03-01 2005-09-01 Dureseti Chidambarrao Method of manufacture of FinFET devices with T-shaped fins and devices manufactured thereby
US20070231997A1 (en) * 2006-03-31 2007-10-04 Doyle Brian S Stacked multi-gate transistor design and method of fabrication
US20090194826A1 (en) * 2003-10-22 2009-08-06 Commissariat A L'energie Atomique Field-effect microelectronic device, capable of forming one or several transistor channels
US20160118483A1 (en) * 2014-10-23 2016-04-28 Globalfoundries Inc. Multi-gate fets having corrugated semiconductor stacks and method of forming the same
WO2016200971A1 (en) * 2015-06-08 2016-12-15 Synopsys, Inc. Substrates and transistors with 2d material channels on 3d geometries

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20090194826A1 (en) * 2003-10-22 2009-08-06 Commissariat A L'energie Atomique Field-effect microelectronic device, capable of forming one or several transistor channels
US20050191795A1 (en) * 2004-03-01 2005-09-01 Dureseti Chidambarrao Method of manufacture of FinFET devices with T-shaped fins and devices manufactured thereby
US20070231997A1 (en) * 2006-03-31 2007-10-04 Doyle Brian S Stacked multi-gate transistor design and method of fabrication
US20160118483A1 (en) * 2014-10-23 2016-04-28 Globalfoundries Inc. Multi-gate fets having corrugated semiconductor stacks and method of forming the same
WO2016200971A1 (en) * 2015-06-08 2016-12-15 Synopsys, Inc. Substrates and transistors with 2d material channels on 3d geometries

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
T. SKOTNICKI ET AL., STMICROELECTRONICS, vol. 55, no. 1, 2008, pages 96

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE112020000212B4 (de) 2019-02-27 2022-03-24 International Business Machines Corporation Verfahren zur herstellung eines transistorkanals mit vertikal gestapelten nanoschichten, die durch finnenförmige brückenzonen verbunden sind
GB2595160B (en) * 2019-02-27 2024-05-22 Ibm Transistor channel having vertically stacked nanosheets coupled by fin-shaped bridge regions
US20210384320A1 (en) * 2019-04-29 2021-12-09 International Business Machines Corporation Transistor device having a comb-shaped channel region to increase the effective gate width

Similar Documents

Publication Publication Date Title
US7897058B2 (en) Device manufacturing method and computer program product
CN108885414B (zh) 光刻装置、器件制造方法以及相关的数据处理装置和计算机程序产品
US20070190762A1 (en) Device manufacturing method and computer program product
US7786477B2 (en) Semiconductor device for measuring an overlay error, method for measuring an overlay error, lithographic apparatus and device manufacturing method
US20080012511A1 (en) Planar Motor Device, Stage Device, Exposure Device and Device Manufacturing Method
JP4425256B2 (ja) リソグラフィ装置およびモータ
US20110126406A1 (en) Lithographic Apparatus and Method of Manufacturing an Electrostatic Clamp for a Lithographic Apparatus
US8029953B2 (en) Lithographic apparatus and device manufacturing method with double exposure overlay control
EP3389095A1 (de) Herstellungsverfahren für einen finfet, finfet und vorrichtung mit einem finfet
US20100214548A1 (en) Lithographic apparatus and device manufacturing method
JP2015532825A (ja) 電磁アクチュエータ、支持体、およびリソグラフィ装置
US8119333B2 (en) Lithographic method
US8947640B2 (en) Positioning device, lithographic apparatus, positioning method and device manufacturing method
US10437160B2 (en) Lorentz actuator, object positioning system, lithographic apparatus and Lorentz actuator operating method
WO2014122223A1 (en) Lithographic apparatus and device manufacturing method
US20220334505A1 (en) Method of designing an alignment mark
EP3812841A1 (de) Verfahren zum entwurf einer ausrichtungsmarkierung
US9753381B2 (en) Substrate table system, lithographic apparatus and substrate table swapping method
KR102243882B1 (ko) 액츄에이터, 선형 모터 및 리소그래피 장치
WO2018024529A1 (en) Positioning system, control system, method to position, lithographic apparatus and device manufacturing method

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

AX Request for extension of the european patent

Extension state: BA ME

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20190418