EP3387513A1 - Software defined fifo buffer for multithreaded access - Google Patents
Software defined fifo buffer for multithreaded accessInfo
- Publication number
- EP3387513A1 EP3387513A1 EP16874038.9A EP16874038A EP3387513A1 EP 3387513 A1 EP3387513 A1 EP 3387513A1 EP 16874038 A EP16874038 A EP 16874038A EP 3387513 A1 EP3387513 A1 EP 3387513A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- requests
- buffer
- write
- buffer controller
- hardware
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000872 buffer Substances 0.000 title claims abstract description 222
- 230000004044 response Effects 0.000 claims abstract description 16
- 238000000034 method Methods 0.000 claims description 58
- 230000000903 blocking effect Effects 0.000 claims description 7
- 230000008569 process Effects 0.000 claims description 5
- 230000004931 aggregating effect Effects 0.000 claims 4
- 230000000977 initiatory effect Effects 0.000 claims 1
- 230000006870 function Effects 0.000 description 13
- 238000010586 diagram Methods 0.000 description 11
- 238000004590 computer program Methods 0.000 description 8
- 230000003287 optical effect Effects 0.000 description 2
- 230000002093 peripheral effect Effects 0.000 description 2
- 241000699670 Mus sp. Species 0.000 description 1
- 238000001444 catalytic combustion detection Methods 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 238000009877 rendering Methods 0.000 description 1
- 230000009466 transformation Effects 0.000 description 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
- G06F3/0659—Command handling arrangements, e.g. command buffers, queues, command scheduling
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0604—Improving or facilitating administration, e.g. storage management
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
- G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
- G06F5/10—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using random access memory
- G06F5/12—Means for monitoring the fill level; Means for resolving contention, i.e. conflicts between simultaneous enqueue and dequeue operations
Definitions
- Bus 112 allows processor(s) 102, memory device(s) 104, interface(s) 106, mass storage device(s) 108, and I/O device(s) 110 to communicate with one another, as well as other devices or components coupled to bus 112.
- Bus 112 represents one or more of several types of bus structures, such as a system bus, PCI bus, IEEE 1394 bus, USB bus, and so forth.
- programs and other executable program components are shown herein as discrete blocks, although it is understood that such programs and components may reside at various times in different storage components of computing device 100, and are executed by processor(s) 102.
- the systems and procedures described herein can be implemented in hardware, or a combination of hardware, software, and/or firmware.
- one or more application specific integrated circuits (ASICs) can be programmed to carry out one or more of the systems and procedures described herein.
- the value of the smaller of the counters 226, 228 may be subtracted from the counters 226, 228, e.g. periodically or upon one of the counters 226, 228 approaching the maximum value that is representable by the counters 226, 228.
- the method 300 may further include outputting 310 to the memory subsystem 204 one or more write commands including the addresses generated at step 308, the write commands effective to invoke writing of data from the write requests at the addresses in the one or more write commands in one of the memory devices 104.
- N write commands may be output 310 for each write request received 302 and each including one of the addresses generated at step 308.
- a single write command may be output 310 that specifies all N addresses generated at step 308 or a range of addresses (e.g., start address and offset) spanning all N addresses.
- the write commands are then executed by the memory device 104 to which they are addressed and the method ends.
- the methods 300 and 312 may be executed substantially simultaneously.
- separate read and write pipelines may be implemented by the hardware buffer controller 208 such memory access commands can be simultaneously generated for both read and write requests.
- the memory access commands from steps 310 and 322 may be buffered and executed sequentially by the memory subsystem 204 according to any command execution scheme known in the art.
- the near empty threshold may be set equal to Q*M + R, where S is the size of the buffer and R is a value greater than zero in order to guarantee that underflow does not occur. In this manner, if a near empty condition is detected, buffer underflow will not occur before the near empty event causes blocking of the M threads that may issue read requests.
Abstract
Description
Claims
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US14/966,631 US10585623B2 (en) | 2015-12-11 | 2015-12-11 | Software defined FIFO buffer for multithreaded access |
PCT/US2016/066106 WO2017100748A1 (en) | 2015-12-11 | 2016-12-12 | Software defined fifo buffer for multithreaded access |
Publications (2)
Publication Number | Publication Date |
---|---|
EP3387513A1 true EP3387513A1 (en) | 2018-10-17 |
EP3387513A4 EP3387513A4 (en) | 2019-07-10 |
Family
ID=59013408
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
EP16874038.9A Pending EP3387513A4 (en) | 2015-12-11 | 2016-12-12 | Software defined fifo buffer for multithreaded access |
Country Status (6)
Country | Link |
---|---|
US (1) | US10585623B2 (en) |
EP (1) | EP3387513A4 (en) |
JP (1) | JP6884149B2 (en) |
KR (1) | KR20180107091A (en) |
CN (1) | CN108292162B (en) |
WO (1) | WO2017100748A1 (en) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US10095408B2 (en) * | 2017-03-10 | 2018-10-09 | Microsoft Technology Licensing, Llc | Reducing negative effects of insufficient data throughput for real-time processing |
CN108038006B (en) * | 2017-11-14 | 2022-02-08 | 北京小鸟看看科技有限公司 | Control method, device and system of head-mounted display device |
KR102421103B1 (en) * | 2018-01-04 | 2022-07-14 | 에스케이하이닉스 주식회사 | Controller, memory system including the same and operating methods of the controller and the memory system |
US10713746B2 (en) | 2018-01-29 | 2020-07-14 | Microsoft Technology Licensing, Llc | FIFO queue, memory resource, and task management for graphics processing |
US11068308B2 (en) | 2018-03-14 | 2021-07-20 | Texas Instruments Incorporated | Thread scheduling for multithreaded data processing environments |
US10719268B2 (en) | 2018-06-29 | 2020-07-21 | Microsoft Technology Licensing, Llc | Techniques for safely and efficiently enqueueing and dequeueing data on a graphics processor |
US10884933B2 (en) * | 2019-01-18 | 2021-01-05 | Silicon Motion Technology (Hong Kong) Limited | Method and apparatus for performing pipeline-based accessing management in a storage server |
Family Cites Families (30)
Publication number | Priority date | Publication date | Assignee | Title |
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JPH07118187B2 (en) | 1985-05-27 | 1995-12-18 | 松下電器産業株式会社 | First-in first-out storage |
US4894797A (en) | 1986-11-17 | 1990-01-16 | Amp Incorporated | FIFO data storage system using PLA controlled multiplexer for concurrent reading and writing of registers by different controllers |
US5581705A (en) | 1993-12-13 | 1996-12-03 | Cray Research, Inc. | Messaging facility with hardware tail pointer and software implemented head pointer message queue for distributed memory massively parallel processing system |
KR0139887B1 (en) | 1994-02-17 | 1999-02-18 | 김광호 | Circuit for preventign a data contact of an image memory |
US6115761A (en) | 1997-05-30 | 2000-09-05 | Lsi Logic Corporation | First-In-First-Out (FIFO) memories having dual descriptors and credit passing for efficient access in a multi-processor system environment |
US5978868A (en) * | 1997-08-28 | 1999-11-02 | Cypress Semiconductor Corp. | System for generating buffer status flags by comparing read and write pointers and determining direction of progression of read pointer with respect to write pointer |
US6044030A (en) | 1998-12-21 | 2000-03-28 | Philips Electronics North America Corporation | FIFO unit with single pointer |
US6756986B1 (en) | 1999-10-18 | 2004-06-29 | S3 Graphics Co., Ltd. | Non-flushing atomic operation in a burst mode transfer data storage access environment |
US20040098519A1 (en) | 2001-03-16 | 2004-05-20 | Hugo Cheung | Method and device for providing high data rate for a serial peripheral interface |
US7206904B2 (en) * | 2002-03-20 | 2007-04-17 | Hewlett-Packard Development Company, L.P. | Method and system for buffering multiple requests from multiple devices to a memory |
CN1201234C (en) * | 2003-03-28 | 2005-05-11 | 港湾网络有限公司 | Multichannel FILO data buffer storage devices |
JP4505450B2 (en) | 2003-04-17 | 2010-07-21 | トムソン ライセンシング | Data request transmitting apparatus and process and corresponding products |
US7181563B2 (en) | 2003-10-23 | 2007-02-20 | Lsi Logic Corporation | FIFO memory with single port memory modules for allowing simultaneous read and write operations |
US8135915B2 (en) | 2004-03-22 | 2012-03-13 | International Business Machines Corporation | Method and apparatus for hardware assistance for prefetching a pointer to a data structure identified by a prefetch indicator |
US6956776B1 (en) * | 2004-05-04 | 2005-10-18 | Xilinx, Inc. | Almost full, almost empty memory system |
US9436432B2 (en) | 2005-12-30 | 2016-09-06 | Stmicroelectronics International N.V. | First-in first-out (FIFO) memory with multi-port functionality |
US9015375B2 (en) | 2006-04-11 | 2015-04-21 | Sigmatel, Inc. | Buffer controller, codec and methods for use therewith |
JP2008293484A (en) | 2007-04-27 | 2008-12-04 | Panasonic Corp | Buffer memory sharing apparatus |
US20090132979A1 (en) | 2007-11-19 | 2009-05-21 | Simon Joshua Waters | Dynamic pointer dereferencing and conversion to static hardware |
GB2469299B (en) * | 2009-04-07 | 2011-02-16 | Imagination Tech Ltd | Ensuring consistency between a data cache and a main memory |
CN101661386B (en) * | 2009-09-24 | 2013-03-20 | 成都市华为赛门铁克科技有限公司 | Multi-hardware thread processor and business processing method thereof |
US8908564B2 (en) * | 2010-06-28 | 2014-12-09 | Avaya Inc. | Method for Media Access Control address learning and learning rate suppression |
US9098462B1 (en) * | 2010-09-14 | 2015-08-04 | The Boeing Company | Communications via shared memory |
US8949547B2 (en) * | 2011-08-08 | 2015-02-03 | Arm Limited | Coherency controller and method for data hazard handling for copending data access requests |
JP5842206B2 (en) * | 2012-01-27 | 2016-01-13 | 株式会社トプスシステムズ | Processor core and multi-core processor system |
US20130198419A1 (en) * | 2012-01-30 | 2013-08-01 | Stephen Jones | Lock-free fifo |
US9542227B2 (en) | 2012-01-30 | 2017-01-10 | Nvidia Corporation | Parallel dynamic memory allocation using a lock-free FIFO |
US9639371B2 (en) | 2013-01-29 | 2017-05-02 | Advanced Micro Devices, Inc. | Solution to divergent branches in a SIMD core using hardware pointers |
US9465729B2 (en) * | 2013-03-13 | 2016-10-11 | Empire Technology Development Llc | Memory allocation accelerator |
US9672008B2 (en) * | 2014-11-24 | 2017-06-06 | Nvidia Corporation | Pausible bisynchronous FIFO |
-
2015
- 2015-12-11 US US14/966,631 patent/US10585623B2/en active Active
-
2016
- 2016-12-12 CN CN201680070274.5A patent/CN108292162B/en active Active
- 2016-12-12 WO PCT/US2016/066106 patent/WO2017100748A1/en active Application Filing
- 2016-12-12 JP JP2018529209A patent/JP6884149B2/en active Active
- 2016-12-12 EP EP16874038.9A patent/EP3387513A4/en active Pending
- 2016-12-12 KR KR1020187018862A patent/KR20180107091A/en not_active Application Discontinuation
Also Published As
Publication number | Publication date |
---|---|
JP6884149B2 (en) | 2021-06-09 |
WO2017100748A1 (en) | 2017-06-15 |
KR20180107091A (en) | 2018-10-01 |
US20170168755A1 (en) | 2017-06-15 |
EP3387513A4 (en) | 2019-07-10 |
CN108292162A (en) | 2018-07-17 |
CN108292162B (en) | 2021-08-31 |
JP2019502201A (en) | 2019-01-24 |
US10585623B2 (en) | 2020-03-10 |
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Inventor name: LO, MANKIT |