EP3365994A1 - Appareil et procédés de synchronisation d'un contrôleur et de capteurs - Google Patents

Appareil et procédés de synchronisation d'un contrôleur et de capteurs

Info

Publication number
EP3365994A1
EP3365994A1 EP16788923.7A EP16788923A EP3365994A1 EP 3365994 A1 EP3365994 A1 EP 3365994A1 EP 16788923 A EP16788923 A EP 16788923A EP 3365994 A1 EP3365994 A1 EP 3365994A1
Authority
EP
European Patent Office
Prior art keywords
sensor
message
time
host controller
synchronization
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP16788923.7A
Other languages
German (de)
English (en)
Inventor
Radu Pitigoi-Aron
Leonid Sheynblat
Carlos Puig
Justin BLACK
Rashmi KULKARNI
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Inc
Original Assignee
Qualcomm Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US15/251,757 external-priority patent/US20160370845A1/en
Priority claimed from US15/299,382 external-priority patent/US20170041897A1/en
Application filed by Qualcomm Inc filed Critical Qualcomm Inc
Publication of EP3365994A1 publication Critical patent/EP3365994A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/0635—Clock or time synchronisation in a network
    • H04J3/0685—Clock or time synchronisation in a node; Intranode synchronisation
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q9/00—Arrangements in telecontrol or telemetry systems for selectively calling a substation from a main station, in which substation desired apparatus is selected for applying a control signal thereto or for obtaining measured values therefrom
    • H04Q9/04—Arrangements for synchronous operation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2209/00—Arrangements in telecontrol or telemetry systems
    • H04Q2209/30—Arrangements in telecontrol or telemetry systems using a wired architecture
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q2209/00—Arrangements in telecontrol or telemetry systems
    • H04Q2209/80—Arrangements in the sub-station, i.e. sensing device
    • H04Q2209/84—Measuring functions
    • H04Q2209/845—Measuring functions where the measuring is synchronized between sensing devices

Definitions

  • the subject matter disclosed herein relates to electronic devices, and more particularly to methods, apparatus, and systems for synchronizing controllers and sensors.
  • Modern-day mobile devices contain many sensors.
  • a data processing unit, controller, host device, or master device (hereinafter referred to as simply a controller or a host controller) is provided to receive and process data collected by sensors or slave units (hereinafter referred to a "sensor").
  • the controller is regularly placed into a sleep state when no data is being transferred from the sensors to the controller.
  • asynchronous method a sensor with available data to transfer notifies the controller by issuing a signal (e.g., a Data Ready Interrupt (DRI) signal through a dedicated DRI pin for certain known systems), which wakes up the controller, and then the sensor transfers the data when the controller is ready.
  • a signal e.g., a Data Ready Interrupt (DRI) signal through a dedicated DRI pin for certain known systems
  • the controller wakes up from the sleep state spontaneously at predetermined time intervals, polls the sensors, and receives from the sensors whatever data is present at the sensors.
  • the synchronous method is more energy efficient in a device comprising multiple sensors because data transfers from more than one sensor may be consolidated into a single poll and transfer session.
  • a method for transmitting sensor timing correction messages implemented with a host controller includes determining a synchronization message, the synchronization message configured to be transmitted to a sensor and to indicate a beginning of a synchronization period for synchronizing timing of the host controller and the sensor.
  • a delay time message is also determined where the delay time message is configured to indicate a time delay between the beginning of the synchronization period and an actual transmission time of the synchronization message.
  • the method further includes transmitting the synchronization message with the delay time message in an information message to the sensor, wherein the information message is configured to allow the sensor to correct timing of a sensor timer.
  • a host controller device having a transport medium interface configured to communicatively coupled to at least one sensor device via at least one transport medium;.
  • the host controller further includes at least one processing circuit communicatively coupled to the transport medium interface and configured to determine a synchronization message, the synchronization message configured to be transmitted to a sensor and to indicate a beginning of a synchronization period for synchronizing timing of the host controller and the sensor.
  • the at least one processing circuit is further configured to determine a delay time message configured to indicate a time delay between the beginning of the synchronization period and an actual transmission time of the synchronization message, and transmit the synchronization message with the delay time message in an information message to the sensor, wherein the information message is configured to allow the sensor to correct timing of a sensor timer.
  • a processor-readable storage medium has one or more instructions which, when executed by at least one processing circuit, cause the at least one processing circuit to determine a synchronization message, the synchronization message configured to be transmitted from a host controller to a sensor on a transport medium and to indicate a beginning of a synchronization period for synchronizing timing of the host controller and the sensor.
  • the instructions further cause the at least one processing circuit to determine a delay time message configured to indicate a time delay between the beginning of the synchronization period and an actual transmission time of the synchronization message, and transmit the synchronization message with the delay time message in an information message to the sensor, wherein the information message is configured to allow the sensor to correct timing of a sensor timer.
  • FIG. 1 is block diagram illustrating an exemplary mobile device in which the presently disclosed methods and apparatus may be implemented.
  • FIG. 2 is block diagram illustrating an exemplary hardware environment in which the presently disclosed methods and apparatus may be implemented.
  • FIG. 3 is a flowchart illustrating an exemplary method for synchronizing a host controller and sensor timers.
  • FIG. 4 illustrates an exemplary system timing diagram of activity on an interface.
  • FIG. 5 illustrates a timeline diagram showing an example of a synchronization procedure on an interface.
  • FIG. 6 illustrates a timeline diagram showing setting of polling timing by accounting for jitter and synchronization messaging timing.
  • FIG. 9 illustrates an exemplary host controller or master device according to the present disclosure.
  • the functions, engines or modules described herein may be performed by device itself and/or some or all of the functions, engines or modules described herein may be performed by another system connected through I/O controller 125 or network interface 110 (wirelessly or wired) to device.
  • I/O controller 125 or network interface 110 wirelesslessly or wired
  • some and/or all of the functions may be performed by another system and the results or intermediate calculations may be transferred back to the device 100.
  • such other devices may include a server configured to process information in real time or near real time.
  • the other device is configured to predetermine the results, for example based on a known configuration of the device.
  • one or more of the elements illustrated in FIG. 1 may be omitted from the device 100.
  • one or more of the sensors 130-165 may be omitted in some embodiments.
  • sensor 210 may receive information relating to the processor clock or timer, derive the timer or clock correction factor, and apply the timer correction factor. In some embodiments, sensor 210 may send information relating to its internal timer or clock to the host controller 205, receive the timer correction factor derived at host controller 205, and apply the timer correction factor.
  • the clock or timer information may be transferred using DRI line 240.
  • the clock or timer information may be transferred using a dedicated clock or timer correction line 250.
  • the clock or timer information may be transferred using a regular data connection between processor 101 and sensor 210, such as an PC or I3C bus described above.
  • host controller 205 may transmit two pulses to sensor 210, where the pulses are spaced by a predetermined time interval as measured by the processor timer.
  • the time interval is chosen such that it can be reliably used to derive a timer correction factor to correct the sensor timer 215.
  • This time interval may be referred to as the Frequency Time interval (T Fq).
  • T Fq Frequency Time interval
  • T_Fq may be in the range of a few milliseconds.
  • T Fq is chosen to coincide with the shortest sensor sampling period present.
  • T Fq may be chosen to be as long as T Ph. For example, T_Fq may be 1 second.
  • sensor 210 may compare the duration of the time interval bookended by the two identifiable significant edges included with the timer correction messages, as measured by the sensor timer 215, with the predetermined T Fq, also as measured by the sensor timer, derive a timer correction factor accordingly, and apply the timer correction factor to correct the internal sensor timer.
  • sensor 210 may send information relating to its internal timer to host controller 205, receive the timer correction factor derived at host controller 205, and apply the timer correction factor when the sensor timer 215 is being corrected.
  • sampling timer is based on the host controller timer, sampling events of sensor 210 and polling events of host controller 205 may always be aligned. It should also be appreciated that in some embodiments, the sampling timer signal may serve as the polling signal as well at the same time. In another embodiment, the processor timer may be directly provided to sensor 210, and sensor 210 may base the sampling events on the processor timer instead of its internal sensor timer. [0054] By utilizing the exemplary methods for synchronizing sensor timers described herein, a controller may coordinate timer corrections for sensors and receive all sensor data samples from multiple sensors in batches in an energy-efficient synchronous mode, without wasting energy in polling the sensors at a frequency that is higher than necessary.
  • the HW is mutually agreed upon by the host controller/master and sensor/slave, and is the event that is to be timestamped by the slave/sensor against its time base (i.e., its internal timer/counter).
  • the HW event could be the start of the communication on the line, which for I 2 C, I3C, or System Management Bus (SMBus), as examples, could be chosen as one of the transmission starts that will be the moment in time that is to be recorded/timestamped by the sensor/slave.
  • the HW event may be some other mechanism.
  • the HW event could be the CS line going LOW for the transmission.
  • the combination of the HW event and the ST message identifying the HW event may be referred to collectively as a "synchronization message.”
  • the HW event may be subsumed into the ST message where the starting edge or time of the ST message constitutes the HW event.
  • the slave/sensor can deduct the communicated DT from the time it receives the real time HW event (i.e., at the "Real T Ph time"), and therefore arrive at the Starting T Ph time when the T_Ph should have actually been started, against slave/sensor time base (i.e., the timer/counter of the sensor).
  • the information indicating the Delay Time period may indicate that the delay period is approximately 1/n as long as a time phase period T Ph, where n is a power of two (e.g., 1, 2, 4, 8 ... ). Based on the timing of the synchronization message and the information indicative of the Delay Time periods, the sensors/slaves may determine the expected beginning of new T_Ph periods.
  • sensors receiving this information may determine the expected beginning of a next or new T Ph period, indicated by pulse or timestamp 424 in timeline 410, for example, showing processing of the information message 420 has occurred. With the determined start of the next T Ph period the sensors may then transmit data at particular predetermined repetitions or system awake intervals within the T Ph period as may be seen in timeline 412. When the sensors' timers are synchronized, sensor data may be transmitted at each timestamp or sample frequency of each of the synchronized sensors as may be seen in timeline 412. Thus, the sensor data is synchronized (see generally 426 in FIG.
  • FIG. 4 illustrates that a synchronized system affords adjust of the frequency and phase of the sensors' sampling periods.
  • the host controller or master sends the synchronization information (i.e., information message 420 or Synchronization event) with a repetition period of T Ph.
  • the time phase period T Ph may be a relatively large time interval, such as 1 second, and is exactly divisible by the Least Common Multiple of the sampling periods of the sensors coupled to the host controller.
  • the synchronization process could either adjust some of the ODRs or, in the worst case, synchronize the sensors in more, but smaller groups.
  • a host controller may be configured to transmit various commands and corresponding data over the interface 217, such as an I2C or I3C interface.
  • a host controller will transmit an Output Data Rate (ODR) command and data to particular sensors or devices that sets or establishes the running output data rate for a sensor(s).
  • ODR Output Data Rate
  • the ODR value indicates the number of samples taken by a sensor in a given period of time and is also specific to each particular sensor or device sampling and transmitting data over the interface.
  • a host controller also issues a command and data that communicates the time phase period T Ph.
  • the T Ph may be expressed in the number of sampling periods of a chosen ODR.
  • the start of a T Ph interval may correspond to a time when most of the sensors would collect data simultaneously, and the sampling moments of several sensors should coincide at least once during one T Ph period. These coincident sampling moments allows the data transfer from all the sensors to occur during a same transaction, as may be also seen in timeline 412, for example, and sampling moments may be seen at the vertical dashed lines in FIG. 4 (See e.g., line 430 in FIG. 4). Also, in an aspect the T_Ph value is generally chosen such that the sensors' timers keep 0.1% accuracy with respect to T Ph duration, which generally is about one (1) second. [0070] FIG.
  • FIG. 5 illustrates a timeline diagram 500 showing an example of a synchronization procedure on an interface, such as and I2C or 13 C Bus.
  • FIG. 5 illustrates a timeline of communications over the interface between a controller (e.g., host controller 205) and a sensor (e.g., 210) in which the timing of the sensor is adjusted to provide efficiency in coordinating multiple sensors and to guarantee that sensor reads do not duplicate data or miss desired data.
  • the example of FIG. 5 utilizes the information message (e.g., message 420) including an ST message followed by or paired with a delay time DT message for synchronization of sensor timers to the host controller.
  • Timeline 502 shows read events of by a host controller (e.g., 205) of communications emanating from a sensor (e.g., 210) on the interface.
  • Timeline 502 shows the communication including a START 504 event, in the case of I2C or I3C, and then the data and control information 506 from the sensor.
  • a first portion of information 505 may include the Sync Tick (ST) and the Delay Time (DT), with the remainder of the communication information including typical communications exchanging polled data and control information.
  • ST Sync Tick
  • DT Delay Time
  • the sensor internally records when the ST occurs and uses that information if it is followed by a command indicating that it is used as a synchronization pulse or event.
  • the synchronization events are mutually identifiable hardware events between controller and sensor, which may be determined a priori.
  • the hardware event may be one of various START conditions known to I2C or 13 C interfaces, such as a START condition defined by a falling edge of the SDA line, but the event is certainly not limited to such.
  • Subsequent communications 506 within the T Ph period may include polling or other commands/messages.
  • Timeline 512 shows the ST and DT message 514 (e.g., the information message 420 as discussed earlier) that is used for synchronizing the host controller and the sensor.
  • the ST message is validated by the DT message, which gives the time delay that is usable by a sensor for timing correction. It is noted here that the correction for the delay arising in the host controller is different from sensor clock rate correction, which is determined within the sensor based upon the time between ST pulses.
  • the ST message and DT message in message 514 may be distinguished from one another by setting different values in a Defining Byte field for each message.
  • the host controller may determine or measure the delay time (DT) 520, which is the time from an expected start of a T Ph period (sequence period) as indicated on timeline 516 at timestamp pulse 518 at T Ph start that is in synchronization. Additional sensor timestamps 522 during the T Ph period are synched with the host controller.
  • the time correction communicated by the DT message accounts for the time between the start of the T Ph and when the ST message is sent out on the interface. As described before, this delay may occur because there is hardware and software overhead in the host controller. The hardware overhead is usually known ahead of time from the latency of digital logic of the host controller.
  • the software overhead latency may be less stable and may arise from competing priorities in the operating system or the control software.
  • the software may be handling priority interrupts during the time when the ST is about to be sent. This can cause sending of the ST to be delayed. Furthermore, these delays can change from cycle to cycle.
  • sending the measured DT 520 with the ST affords the ability for sensors to adapt to the delay of the beginning of the T Ph period and the sending of the ST.
  • the DT message effectively qualifies each ST time stamp.
  • the ST message is preferably sent as soon after a START Condition (and, for a Direct Message, the Slave Address) as possible, providing enough time for the DT Message to be sent and received.
  • the DT Message should arrive before a next shortest polling time window, as will be discussed in more detail later.
  • the DT Message may contain either a time delay between the START Condition and the required T Ph Start, or else an abort order for the current synchronization window.
  • various commands may be issued by a master or host controller (e.g., 205) to the sensors (e.g., sensor/slave 210) in particular I2C and I3C systems, for example, although the functionalities thereof are not necessarily limited to I2C and I3C systems.
  • the host controller issues an Output Data Rate (ODR) command for each sensor.
  • ODR command may communicate to a sensor the running ODR.
  • ODR command code may be a single byte (OxXX) along with another byte of sensor specific data.
  • T Ph time period i.e., the Synchronization Event repetition period or synchronization period
  • This command sets the repetition rate of the T Ph.
  • the ST message may include this TPH command code within the Defining Byte field, followed by specific data byte(s) concerning the particular time settings or values.
  • TU time unit
  • This command sets the value of the time unit transferred to the sensor or slave devices.
  • the ST message may include this TPH command code within the Defining Byte field, followed by specific data byte(s) concerning the particular time settings or values.
  • RR resolution ratio
  • the resolution ratio command provides a division factor that is applied for calculating resolution steps of the T Ph time for the DT command.
  • the use of relative division of the T Ph for transmitting the delay time avoids the need for either the host controller or the sensors to know each- others' real timer or clock value.
  • the calculation of a T Ph resolution step is determined by multiplying the corresponding T Ph time period by the RR.
  • the RR as described before, is expressed in the number of divisions by a selected inverse powers of 2 of the T Ph time.
  • the RR values may be expressed as 2 "x where x may be integer values from 11 to 14 (thus, the RR values range from 2 "11 to 2 "14 ).
  • the two least significant bits (LSBs) in the RR message can used to indicate to the sensors which T Ph division factor is used for calculating the time resolution steps from integer values 11 to value 14 that are inverse powers of 2 (e.g., 2'b00 ⁇ 2 A (-11), 2'b01 ⁇ 2 A (-12), 2'blO ⁇ 2 A (-13) 2'bll ⁇ 2 A (-14)).
  • T_Ph period is assumed to be 1 second (i.e., 1000 ms) and the RR value is set at 2 ⁇ u , for example, the resolution step time would be 1000 ms x 2 "11 or 488 ⁇ .
  • the multiplying operation is a simple right shift by the same number of positions as the positive integer exponent of the division value.
  • the DT message may be constructed with one byte such that 7 bits could be used for communicating the delay steps and a most significant bit (MSB) would indicate an abort (although the message is not necessarily limited to one byte of data).
  • MSB most significant bit
  • the absolute maximum delay time would be a time period that corresponds to 127 resolution steps. Based on the resolution step time determined as a division factor of the T Ph period and the predetermined number of resolution steps for a maximum delay time (DT) in which the ST+DT message should be transmitted, the maximum delay time may be computed.
  • the maximum DT correction range would be 488 x 127 or 62.01 ms.
  • Table 1 illustrates examples of various numbers of maximum ST+DT delay times (or DT correction range) given different T Ph periods and RR values from 11 to 14.
  • the RR provides a compact way of expressing the delay time, suitable for any real time units on which the timers of the host controller/master and sensor/slave are based.
  • the resolution of the result is implicitly set.
  • the ideal, fast, and slow marks are only shown for illustration purposes as a visualization of where these timings would occur.
  • the next three timelines 610, 612, and 614 represent ideal, fast, and slow timers or clocks on a sensor where the deviations fast or slow from the ideal represents the range of acceptability for a sensor.
  • the amount of time the sensor time stamp is off in time i.e., the fast timestamp 618, the ideal timestamp 616, and the slow timestamp 620
  • This timing can be affected by temperature, supply voltage, and other elements of the sensor's operation.
  • Timeline 622 illustrates times that the host controller may poll the sensor by taking into consideration the different situations of ideal, fast, or slow sensor timing.
  • the minimum delay to start polling as shown by pulse 624 must be late enough to ensure that even slow sensor timing has completed data sampling as illustrated by the pulse timing 624 occurring in time just after the timestamp 620 of the slow sensor timing as may be seen at time point 626. This timing would only be possible, however, if the host controller could guarantee polling at that exact time.
  • the host controller itself has a variation in when it is available to actually effect polling due to delays in the hardware, firmware, and software.
  • This variation is shown as the Host Jitter Maximum 628, where this maximum jitter represents the longest possible delay time, the end of which is the illustrated as a maximum delay timing 630 for the ST+DT pulse.
  • the Host Jitter Maximum 628 time period may be known a priori or based on measurements or calculations performed by the host controller.
  • the rate of sending the ST+DT information message 630 is set low enough that the Max Read Window is non-negative. Accordingly, the determination of the Max Read Window 636 includes actively setting or adjusting the ST+DT information message 630. Furthermore, it will be appreciated that the methodology of FIG. 6 allows for computation of determination of the number of ODR periods (e.g., period 603) for which sensor data may be sampled during a synchronization period (i.e.., a T Ph).
  • the number of ODR periods allowing for sampling of sensor data before the fastest possible sensor sampling timing would change the data to be read at a next ODR may be determined. From this determination of the number of ODR periods (or polling timing or the number of polling cycles) during a synchronization period (T Ph) (or resynchronization if occurring after initial synchronization) may be set or determined by the host controller.
  • T Ph synchronization period
  • range of fastest to slowest sensor timings i.e., 606 to 608 as represented in FIG. 6 do not necessarily represent a particular number of sensors, but rather it illustrating the possible range of the possible variations of a particular sensor's timings (or alternatively this could be the range of possible timer variations of a number of sensors collectively), and the number of sensors in the physical system may be one or more where the range encompasses the fastest and slowest possible timings of the one or more sensors.
  • the host controller may monitor the gradual drift of the sensor timers from the transmitted timestamps (e.g., 616, 618, 620, or other times not shown by FIG. 6) indicating time instants when data becomes available to the host controller. From this monitoring, the determinations of the minimum and/or maximum delay times (i.e., the range of variation between the slowest and fastest sensor timing) may be adjusted dynamically.
  • FIG. 7 illustrates a flowchart of an exemplary method 700 for transmitting sensor timing correction messages.
  • Method 700 may be implemented with master or host controller such as with host controller 205 or processor 101, as examples.
  • method 700 includes determining a synchronization message (e.g., an ST message), the synchronization message configured to be transmitted to a sensor (e.g., sensor 210) and to indicate a beginning of a synchronization period (e.g., the T Ph period) for synchronizing timing of the host controller and the sensor.
  • the method further includes determining a delay time message (i.e., DT) configured to indicate a time delay between the beginning of the synchronization period and an actual transmission time of the synchronization message.
  • a delay time message i.e., DT
  • the process of block 704 may be effected by a host controller measuring the time from the start of the synchronization period to the actual transmission of the synchronization message.
  • Method 700 further includes transmitting the synchronization message along with or paired with the delay time message in an information message to the sensor, wherein the information message is configured to allow the sensor to correct timing of a sensor timer as shown in block 706.
  • the DT message communicates the delay time to the sensor, that in turn allows the sensor to correct its internal timer (e.g., timer 215) accounting for this delay, thus accurately maintaining synchronization with the host controller.
  • the synchronization signal or message (e.g., a HW event and a Sync Tick (ST)) is used to indicate a beginning of a new synchronization or Time Phase period (e.g., T Ph) and may be configured as a START condition with a command and data, or may simply be a rising edge or a falling edge of a START condition of an PC or I3C bus message.
  • the signal may be a message on an SPI bus.
  • one or more polling messages or commands (e.g., 505 or 506) may be transmitted to the sensor after the information message including ST+DT during a particular synchronization period (T Ph), as may be seen in the example of FIG. 5. Additionally, these polling messages may be sent at a particular rate or cycle (ODR), which may also be set by the host controller.
  • ODR rate or cycle
  • FIG. 8 illustrates a flowchart illustrating an exemplary method 800 for determining the read time window as illustrated in FIG. 6. It is first noted that method 800 may be implemented in conjunction with or in parallel with the methodology described in connection with FIG. 7. As may be seen in FIG. 8, at block 802 a determination is made of a maximum possible jitter of a host controller and a range of sensor timings when data becomes available at at least one sensor. In an aspect, the processes of block 802 may be determined by the host controller (e.g., processor 101 or host controller 205), and may be a determination of the Host Jitter Max 628 and the range of timings from the earliest timestamp 618 and the latest timestamp 620 as may be seen in FIG. 6.
  • the host controller e.g., processor 101 or host controller 205
  • Method 800 also includes the process of block 804 including setting a time required to transmit the information message (i.e., the ST+DT message) based on the determined maximum possible jitter and the range of sensor timings to ensure the allocation of a window of time for reading data from the at least one sensor (i.e., a "read window") before a fastest sensor timing in the range of sensor timings would indicate a change in the sensor data in a next polling cycle (i.e., the next ODR cycle).
  • the processes in block 804 may also be implemented by a host controller, such as host controller 205 or processor 101.
  • the processes of block 804 include the determination and allocation of the Max Read Window 636 shown in FIG.
  • method 800 may include determining and setting a number of polling cycles (i.e. ODR cycles) in the synchronization period based on at least one of the determined maximum read window and the fastest sensor timing in the range of sensor timings.
  • FIG. 9 illustrates an exemplary host controller or master device 902 that may include processing or logic circuitry 904 coupled with a transmitter/receiver circuitry 906 for transmitting and receiving signals, commands, and data on a bus interface or circuit communicatively coupled with at least slave or sensor devices.
  • the transmitter/receiver circuitry 906 may include a timer circuit or clock 908 used at least for determining timing in synchronization of slave or sensor device coupled to the host controller 902 via the bus interface.
  • the host controller 902 may employ other clocking or timing devices for internal clocking, such as clocking for the processing circuitry 904 as an example.
  • the transmitter/receiver circuitry 906 also include a transport medium interfacing circuit 910 configured to interface the transmitter/receiver circuitry with the physical interface, which may an I 2 C or I3C bus, or even a wireless interface as examples.
  • the transport medium may employ at least two lines such as an SDA line and SCL line in the example of a bus, but could include further lines as discussed earlier with respect to interface 217 in FIG. 2.
  • the host controller 902 also may include a memory or storage medium 912 coupled with at least the processing circuitry 904 and include code or instructions for causing the circuitry 904 to implement or direct the transmitter/receiver circuit 906 to implement the various methodologies disclosed herein, such as those disclosed in connection with FIGs. 3-8.
  • the host controller 902 may include a dedicated synchronization circuitry or logic 914 that performs some or all of the functions of effecting sensor timer correction as disclosed in FIGs. 3-8.
  • FIG. 10 illustrates an exemplary sensor or slave device 1002 that may include processing or logic circuitry 1004 coupled with a transmitter/receiver circuitry 1006 for transmitting and receiving signals and data on a bus interface or circuit communicatively coupled with at least a host controller or master device, but also other devices on the bus as well.
  • the transmitter/receiver circuitry 1006 may include a timer circuit or clock 1008 used at least for determining timing in synchronization of the slave or sensor device 1002 under the direction of a host controller (e.g., controller 902) via the bus interface.
  • the sensor 1002 may employ other clocking or timing devices for internal clocking of the sensor, such as clocking for the processing circuitry 1004 as an example.
  • the transmitter/receiver circuitry 1006 also include a transport medium interfacing circuit 1010 configured to interface the transmitter/receiver circuitry with the physical interface, which may be an I 2 C or I3C bus, or even a wireless interfaces just a few examples.
  • the transport medium interfacing circuit 910 may employ at least two lines such as an SDA line and SCL line in the example of a bus, but could include further lines as discussed earlier with respect to interface 217 in FIG. 2.
  • the sensor 1002 also may include a memory or storage medium 1012 coupled with at least the processing circuitry 1004 and include code or instructions for causing the circuitry 1004 to implement or direct the transmitter/receiver circuit 1006 to implement the various methodologies disclosed herein, such as those disclosed in connection with FIGs. 3-8, particularly applying the ST+DT message for correction of the timer circuit 1008, as well as the RR command for calculating a maximum DT timing, for example.
  • the sensor 1002 may include a dedicated synchronization circuitry or logic 1014 that performs some or all of the functions of effecting sensor timer correction as disclosed in FIGs. 3-8.
  • circuitry of the device including but not limited to processor, may operate under the control of an application, program, routine, or the execution of instructions to execute methods or processes in accordance with embodiments of the invention (e.g., the processes illustrated by FIGs. 3-8).
  • a program may be implemented in firmware or software (e.g., stored in memory and/or other locations) and may be implemented by processors and/or other circuitry of the devices.
  • processor, microprocessor, circuitry, controller, etc. refer to any type of logic or circuitry capable of executing logic, commands, instructions, software, firmware, functionality, etc.
  • FIG. 11 is a diagram illustrating a simplified example of a hardware implementation for a host controller 1100 employing a processing circuit 1102. Examples of operations performed by the host controller 1100 include the operations described above with respect to the flow chart of FIGs. 3, 7 and 8, as well as the timelines in FIGs. 4-6.
  • the processing circuit 1102 typically has a processor 1104 that may include one or more of a microprocessor, microcontroller, digital signal processor, a sequencer and a state machine.
  • the processing circuit 1102 may be implemented with a bus architecture, represented generally by the bus 1106
  • the bus 1106 may include any number of interconnecting buses and bridges depending on the specific application of the processing circuit 1102 and the overall design constraints.
  • the bus 1106 communicatively couples various circuits including one or more processors and/or hardware modules, represented by the processor 1104, and an interface module or circuit 1108 that is configurable to support communication over various connectors or wires 1110 operable according to various transport protocols or wireless interfaces (as shown by optional antenna 1112) and a computer-readable storage medium 1114.
  • the bus 1106 may also link various other circuits such as timing sources, peripherals, voltage regulators, and power management circuits, which are well known in the art, and therefore, are not described in detail herein.
  • the interfaces 1110 may be one or more interfaces operable according to one or multiple transport formats, as well as being communicatively coupled to one or more slave/sensor devices or to other host controllers.
  • the processor 1104 is responsible for general processing, including the execution of software/instructions stored on the computer-readable storage medium 1114.
  • the software/instructions when executed by the processor 1104, causes the processing circuit 1102 to perform the various functions described before for any particular apparatus.
  • the computer or processor readable storage medium 1114 may also be used for storing data that is manipulated by the processor 1104 when executing software, including data decoded from symbols transmitted over the connectors or wires 1110 or antenna 1112.
  • the processing circuit 1102 further includes at least one of the modules/circuits 1108, which may be software modules running in the processor 1104, resident/stored in the computer-readable storage medium 1114, one or more hardware modules coupled to the processor 1104, or some combination thereof.
  • the modules/circuits 1108 may include microcontroller instructions, state machine configuration parameters, or some combination thereof.
  • the processor readable medium 1114 includes instructions for determining a synchronization message configured to be transmitted to a sensor and to indicate a beginning of a synchronization period for synchronizing timing of the host controller and the sensor. These instructions are configured to cause the processor 1104 to perform various functions including the processes illustrated in block 702 of FIG. 7, for example.
  • the processor readable medium 1114 also includes instructions for determining a delay time message configured to indicate a time delay between the beginning of the synchronization period and an actual transmission time of the synchronization message. These instructions are configured to cause the processor 1104 to perform various functions including the processes illustrated in block 704 of FIG. 7, for example.
  • the processor readable medium 1114 also includes instructions for transmitting the synchronization message with the delay time message in an information message to the sensor, wherein the information message is configured to allow the sensor to correct timing of a sensor timer. These instructions are configured to cause the processor 1104 to perform various functions including the processes illustrated in block 706 of FIG. 7, for example.
  • the processor readable medium 1114 may include instructions (not shown) to cause the processor 1104 to perform the functions of blocks 802 and 804 in FIG. 8, and the timeline of FIG. 6.
  • Methods described herein may be implemented in conjunction with various wireless communication networks such as a wireless wide area network (WW AN), a wireless local area network (WLAN), a wireless personal area network (WPAN), and so on.
  • WW AN wireless wide area network
  • WLAN wireless local area network
  • WPAN wireless personal area network
  • a WW AN may be a Code Division Multiple Access (CDMA) network, a Time Division Multiple Access (TDMA) network, a Frequency Division Multiple Access (FDMA) network, an Orthogonal Frequency Division Multiple Access (OFDMA) network, a Single-Carrier Frequency Division Multiple Access (SC-FDMA) network, and so on.
  • CDMA network may implement one or more radio access technologies (RATs) such as cdma2000, Wideband-CDMA (W-CDMA), and so on.
  • RATs radio access technologies
  • Cdma2000 includes IS-95, IS- 2000, and IS-856 standards.
  • a TDMA network may implement Global System for Mobile Communications (GSM), Digital Advanced Mobile Phone System (D-AMPS), or some other RAT.
  • GSM and W-CDMA are described in documents from a consortium named "3rd Generation Partnership Project” (3GPP).
  • Cdma2000 is described in documents from a consortium named "3rd Generation Partnership Project 2" (3GPP2).
  • 3GPP and 3GPP2 documents are publicly available.
  • a WLAN may be an IEEE 802.1 lx network
  • a WPAN may be a Bluetooth network, an IEEE 802.15x, or some other type of network.
  • the techniques may also be implemented in conjunction with any combination of WW AN, WLAN and/or WPAN.
  • Example methods, apparatuses, or articles of manufacture presented herein may be implemented, in whole or in part, for use in or with mobile communication devices.
  • mobile device mobile communication device
  • hand-held device handheld devices
  • tablettes etc.
  • the plural form of such terms may be used interchangeably and may refer to any kind of special purpose computing platform or device that may communicate through wireless transmission or receipt of information over suitable communications networks according to one or more communication protocols, and that may from time to time have a position or location that changes.
  • special purpose mobile communication devices may include, for example, cellular telephones, satellite telephones, smart telephones, heat map or radio map generation tools or devices, observed signal parameter generation tools or devices, personal digital assistants (PDAs), laptop computers, personal entertainment systems, e-book readers, tablet personal computers (PC), personal audio or video devices, personal navigation units, or the like.
  • PDAs personal digital assistants
  • laptop computers personal entertainment systems
  • e-book readers tablet personal computers
  • PC tablet personal computers
  • personal audio or video devices personal navigation units, or the like.
  • the herein described memory or storage media may comprise primary, secondary, and/or tertiary storage media.
  • Primary storage media may include memory such as random access memory and/or read-only memory, for example.
  • Secondary storage media may include mass storage such as a magnetic or solid state hard drive.
  • Tertiary storage media may include removable storage media such as a magnetic or optical disk, a magnetic tape, a solid state storage device, etc.
  • the storage media or portions thereof may be operatively receptive of, or otherwise configurable to couple to, other components of a computing platform, such as a processor.
  • one or more portions of the herein described storage media may store signals representative of data and/or information as expressed by a particular state of the storage media.
  • an electronic signal representative of data and/or information may be "stored" in a portion of the storage media (e.g., memory) by affecting or changing the state of such portions of the storage media to represent data and/or information as binary information (e.g., ones and zeroes).
  • a change of state of the portion of the storage media to store a signal representative of data and/or information constitutes a transformation of storage media to a different state or thing.
  • such quantities may take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared or otherwise manipulated as electronic signals representing information. It has proven convenient at times, principally for reasons of common usage, to refer to such signals as bits, data, values, elements, symbols, characters, terms, numbers, numerals, information, or the like. It should be understood, however, that all of these or similar terms are to be associated with appropriate physical quantities and are merely convenient labels.
  • DSP digital signal processor
  • ASIC application specific integrated circuit
  • FPGA field programmable gate array
  • a general purpose processor may be a microprocessor, but in the alternative, the processor may be any conventional processor, controller, microcontroller, or state machine.
  • a processor may also be implemented as a combination of computing devices, e.g., a combination of a DSP and a microprocessor, a plurality of microprocessors, one or more microprocessors in conjunction with a DSP core, or any other such configuration.
  • a software module may reside in RAM memory, flash memory, ROM memory, EPROM memory, EEPROM memory, registers, hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.
  • An exemplary storage medium is coupled to the processor such the processor can read information from, and write information to, the storage medium.
  • the storage medium may be integral to the processor.
  • the processor and the storage medium may reside in an ASIC.
  • the ASIC may reside in a user terminal.
  • the processor and the storage medium may reside as discrete components in a user terminal.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Signal Processing (AREA)
  • Arrangements For Transmission Of Measured Signals (AREA)
  • Electric Clocks (AREA)
  • Information Transfer Systems (AREA)

Abstract

La présente invention concerne des procédés et un appareil permettant de transmettre des messages de correction de temporisation de capteur avec un contrôleur hôte. Les procédés et l'appareil déterminent des messages de synchronisation qui sont transmis à un capteur couplé au contrôleur hôte par l'intermédiaire d'une interface, lesdits messages indiquant un début d'une période de synchronisation destinée à synchroniser une temporisation du contrôleur hôte et du capteur. De plus, un message de temps de retard est déterminé pour indiquer un temps de retard entre le début de la période de synchronisation et un temps de transmission réel du message de synchronisation. Le message de synchronisation est transmis au capteur avec le message de temps de retard dans un message d'informations, ledit message d'informations étant configuré pour permettre au capteur de corriger une synchronisation d'un temporisateur de capteur en tenant compte du temps de retard.
EP16788923.7A 2015-10-23 2016-10-21 Appareil et procédés de synchronisation d'un contrôleur et de capteurs Withdrawn EP3365994A1 (fr)

Applications Claiming Priority (7)

Application Number Priority Date Filing Date Title
US201562245914P 2015-10-23 2015-10-23
US201562245917P 2015-10-23 2015-10-23
US201562245922P 2015-10-23 2015-10-23
US201562245924P 2015-10-23 2015-10-23
US15/251,757 US20160370845A1 (en) 2013-11-12 2016-08-30 System and methods of reducing energy consumption by synchronizing sensors
US15/299,382 US20170041897A1 (en) 2013-11-12 2016-10-20 Apparatus and methods for synchronizing a controller and sensors
PCT/US2016/058284 WO2017070588A1 (fr) 2015-10-23 2016-10-21 Appareil et procédés de synchronisation d'un contrôleur et de capteurs

Publications (1)

Publication Number Publication Date
EP3365994A1 true EP3365994A1 (fr) 2018-08-29

Family

ID=58558165

Family Applications (1)

Application Number Title Priority Date Filing Date
EP16788923.7A Withdrawn EP3365994A1 (fr) 2015-10-23 2016-10-21 Appareil et procédés de synchronisation d'un contrôleur et de capteurs

Country Status (7)

Country Link
EP (1) EP3365994A1 (fr)
JP (1) JP2018534688A (fr)
KR (1) KR20180071268A (fr)
CN (1) CN108141293A (fr)
BR (1) BR112018008278A2 (fr)
CA (1) CA3000011A1 (fr)
WO (1) WO2017070588A1 (fr)

Families Citing this family (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US10707984B2 (en) * 2017-07-14 2020-07-07 Qualcomm Incorporated Techniques for synchronizing slave devices
EP3573342B1 (fr) * 2018-05-25 2021-03-31 Harman Becker Automotive Systems GmbH Synchronisation de capteur numérique multidébit
CN108923876B (zh) * 2018-06-27 2020-11-27 北京旷视机器人技术有限公司 时间同步方法、装置及系统
US11134460B2 (en) 2019-06-18 2021-09-28 Commscope Technologies Llc Synchronizing a cloud radio access network to a network time protocol reference clock
CN111077941B (zh) * 2019-11-06 2024-04-02 深圳震有科技股份有限公司 一种时钟同步设置方法、设备及存储介质
CN111309094A (zh) * 2020-02-06 2020-06-19 上海图趣信息科技有限公司 一种传感器设备采集数据的同步板卡及方法
CN111585682B (zh) * 2020-05-09 2022-10-04 森思泰克河北科技有限公司 传感器时间同步方法、装置及终端设备
JP7487551B2 (ja) 2020-05-18 2024-05-21 富士電機株式会社 同期制御システム
TWI767234B (zh) * 2020-05-21 2022-06-11 大陸商北京集創北方科技股份有限公司 串行周邊介面的傳輸速率提升方法、資料傳輸電路及資訊處理裝置
CN111711558B (zh) * 2020-05-28 2023-06-09 腾讯科技（深圳）有限公司 一种消息控制方法及装置
DE102020207995A1 (de) 2020-06-29 2021-12-30 Robert Bosch Gesellschaft mit beschränkter Haftung Verfahren und System zur Synchronisation zwischen einer Datenausgaberate eines Sensors und einem Synchronisationssignal
CN116348930A (zh) * 2020-10-16 2023-06-27 株式会社岛津制作所 数据测量系统及执行测量数据的数据处理的方法
CN113821469A (zh) * 2021-09-23 2021-12-21 深圳市元征科技股份有限公司 多处理器的同步方法、装置、终端设备及存储介质

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6370200B1 (en) * 1997-08-04 2002-04-09 Matsushita Electric Industrial Co., Ltd. Delay adjusting device and method for plural transmission lines
DE102012207138A1 (de) * 2012-04-27 2013-10-31 Robert Bosch Gmbh Sensorzeit-Synchronisation
AU2013204757A1 (en) * 2012-06-03 2013-12-19 Chronologic Pty Ltd Synchronisation of a system of distributed computers
JP6170311B2 (ja) * 2013-02-26 2017-07-26 キヤノン株式会社 撮像装置及びその制御方法
US9436214B2 (en) * 2013-11-12 2016-09-06 Qualcomm Incorporated System and methods of reducing energy consumption by synchronizing sensors

Also Published As

Publication number Publication date
BR112018008278A2 (pt) 2018-10-23
WO2017070588A1 (fr) 2017-04-27
CA3000011A1 (fr) 2017-04-27
CN108141293A (zh) 2018-06-08
JP2018534688A (ja) 2018-11-22
KR20180071268A (ko) 2018-06-27

Similar Documents

Publication Publication Date Title
US20170041897A1 (en) Apparatus and methods for synchronizing a controller and sensors
EP3365994A1 (fr) Appareil et procédés de synchronisation d'un contrôleur et de capteurs
US10707984B2 (en) Techniques for synchronizing slave devices
US20170041688A1 (en) Apparatus and methods for timestamping in a system synchronizing controller and sensors
EP3365746A2 (fr) Dispositives en procédés de synchronisation d'un contrôleur et des capteurs
US20160370845A1 (en) System and methods of reducing energy consumption by synchronizing sensors
TWI545985B (zh) 透過藍芽之裝置同步
US10863469B2 (en) System and method for accurate timestamping of virtual reality controller data
US9572102B2 (en) Correction of clock errors in a wireless station to enable reduction of power consumption
US20180224887A1 (en) Apparatus and method for asynchronous event timestamping
US20130343365A1 (en) Methods and apparatus for synchronization among integrated circuits within a wireless network
CN106937369B (zh) 低功耗节点同步唤醒方法、节点及系统
US9307571B2 (en) Communication device and frequency offset calibrating method
CN102412957A (zh) 一种高精度同步时钟调整方法
CN105873190B (zh) 一种闭环的时钟校准方法及终端
US10575345B2 (en) Apparatus and method for establishing a connection between nodes of a wireless network

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20180323

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

AX Request for extension of the european patent

Extension state: BA ME

DAV Request for validation of the european patent (deleted)
DAX Request for extension of the european patent (deleted)
GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

INTG Intention to grant announced

Effective date: 20190603

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20191015