EP3349196B1

EP3349196B1 - Master unit for automatic fire alarm system and automatic fire alarm system

Info

Publication number: EP3349196B1
Application number: EP16843915.6A
Authority: EP
Inventors: Motohiro OOI; Takasi ITOU; Kazuhiko Goshonoo; Tomoaki Mizuta; Ran Li
Original assignee: Panasonic Intellectual Property Management Co Ltd
Current assignee: Panasonic Intellectual Property Management Co Ltd
Priority date: 2015-09-11
Filing date: 2016-08-31
Publication date: 2019-12-04
Anticipated expiration: 2036-08-31
Also published as: JP6569981B2; EP3349196A4; JP2017054427A; WO2017043047A1; EP3349196A1

Description

Technical Field

The present invention generally relates to automatic fire alarm system master devices, automatic fire alarm systems, and automatic fire alarm system slave devices.

Background Art

A P-type (proprietary-type) automatic fire alarm (AFA) system has been known in the art as an automatic fire alarm system (see, for example, Patent Literature 1). In the P-type automatic fire alarm system, a fire detector electrically short-circuits a pair of cables functioning as detector lines to notify a fire receiver of the outbreak of a fire. In response, the fire receiver sounds a fire alarm. As such a P-type automatic fire alarm system, an automatic fire alarm system has been known in the art as disclosed in Patent Literature 1 in which a plurality of fire detectors (serving as slave devices) and a fire receiver (serving as a master device) are electrically connected to detector lines (implemented as a pair of cables). The plurality of fire detectors are connected to a plurality of detector lines extended from the fire receiver.
A "time division communication method" has been known in the art as an exemplary method of allowing a master device to communicate with a plurality of slave devices. According to the time division communication method, responsive to a synch signal transmitted from the master device to the plurality of slave devices, each of those slave devices transmits a response signal one after another time-sequentially to the master device.
In such a situation where the master device communicates with those slave devices by the time division communication method, some of the slave devices may have a clock generator with low accuracy. In that case, the longer the reception interval of the synch signal becomes, the longer the time lag between the reception timing of the synch signal and the starting timing when any slave device starts to transmit the response signal tends to be, thus possibly causing interference between two response signals.

Citation List

Patent Literature

Patent Literature 1: JP 2002-8154 A
DE 3529127 A1 discloses a method for data transmission in alarm systems. The method for wireless information transmission within an alarm system operates in such a way that, at the instigation of a sync pulse transmitted from the central station, a response telegram is transmitted back by each alarm detector in turn. This response telegram contains the status of the alarm detectors. The response telegrams are transmitted back serially in a plurality of cycles until a new sync pulse from the central station initiates a new polling cadence.

Summary of Invention

In view of the foregoing background, it is therefore an object of the present invention to provide an automatic fire alarm system master device and automatic fire alarm system that would reduce the chances of causing interference between respective response signals transmitted from a plurality of slave devices and also provide an automatic fire alarm system slave device configured to transmit a response signal to cause interference much less frequently with response signals transmitted from other slave devices.
The object of the present invention is solved by the independent claim Advantageous embodiments are described by the dependent claims. An automatic fire alarm system master device according to an aspect of the present invention is described in claim 1.
An automatic fire alarm system according to another aspect of the present invention includes: the master device described above; and a plurality of slave devices connected to the pair of cables and configured to transmit their respective response signals by varying the voltage between the pair of cables after their respective waiting times have passed since the reception of the synch signal.

Brief Description of Drawings

FIG. 1 illustrates a schematic configuration for an automatic fire alarm system according to a first embodiment;
FIG. 2 illustrates an overall configuration for the automatic fire alarm system according to the first embodiment;
FIG. 3 illustrates how a master device and slave devices perform their communication-related operations according to the first embodiment;
FIG. 4A illustrates signals to be transmitted by slave devices during their respective response periods according to the first embodiment, and FIG. 4B illustrates signals to be transmitted by slave devices according to a comparative example during their respective response periods shorter than those of the first embodiment;
FIG. 5 illustrates how a master device and slave devices perform their communication-related operations according to a variation of the first embodiment;
FIG. 6 illustrates an overall configuration for the automatic fire alarm system according to a second embodiment;
FIG. 7 illustrates a schematic configuration for an automatic fire alarm system according to a third embodiment;
FIG. 8 illustrates a mode of communication between a master device and slave devices according to the third embodiment;
FIG. 9A illustrates a mode of communication between a master device and slave devices according to a fourth embodiment; and FIG. 9B illustrates another mode of communication between a master device and slave devices according to the fourth embodiment.

Description of Embodiments

An automatic fire alarm system, automatic fire alarm system master device, and automatic fire alarm system slave device according to an embodiment respectively relate to an automatic fire alarm system configured to sound a fire alarm, a master device for such an automatic fire alarm system, and a slave device for the automatic fire alarm system.

(First embodiment)

A first embodiment to be described below with reference to FIGS. 1, 2, 3, 4A, and 4B is an automatic fire alarm system 1 configured to sound a fire alarm.
As shown in FIG. 2, an automatic fire alarm system 1 includes sixteen slave devices B1-B16 and one master device 20. In this automatic fire alarm system 1, each of the slave devices B1-B16 and the master device 20 is electrically connected to a pair of cables 51, 52. In the following description, the sixteen slave devices B1 to B16 will be collectively referred to as "slave devices 10" unless they need to be distinguished from each other.
Each of the slave devices 10 is implemented as a detector such as a heat detector, a smoke detector, or a flame detector, and transmits, on detecting the outbreak of a fire, a signal alarming the master device 20 to the outbreak of a fire (hereinafter referred to as a "fire alarm") by varying the value of a voltage between the pair of cables 51, 52. The slave devices 10 do not have to be detectors for detecting the outbreak of a fire but may also be emergency transmitters. As used herein, the "emergency transmitter" refers to a device with a press button, which may be manually pressed by a person who has detected a fire to transmit the fire alarm.
The master device 20 (such as a receiver) receives a signal transmitted from each of the slave devices 10 and, on finding the signal to be a fire alarm, sets off an alarm. The master device 20 may be arranged in, for example, a building manager room of a building in which the automatic fire alarm system 1 is installed.
In the following description, an automatic fire alarm system 1 is supposed to be used in a multi-family dwelling house (e.g., what is called a "mansion" in Japan). Naturally, however, the automatic fire alarm system 1 does not have to be used in a multi-family dwelling house, but may also be used in any of various other types of buildings including business facilities, hospitals, hotels, and multi-tenant buildings.
This automatic fire alarm system 1 includes sixteen slave devices 10 and one master device 20 for a single multi-family dwelling house 60. The multi-family dwelling house 60 is provided with four pairs of cables 51, 52, all of which are connected to the master device 20. A plurality of (e.g., four) slave devices 10 are electrically connected to each pair of cables 51, 52. Each of the four pairs of cables 51, 52 has one of the two ends thereof, opposite from the other end connected to the master device 20, connected to a terminal resistor 40. Each of the master device 20 and the plurality of (e.g., sixteen) slave devices 10 is electrically connected to, and sends a signal to, an associated one pair of cables 51, 52. The signal sent to the pair of cables 51, 52 may be a signal representing a variation in voltage or current between the pair of cables 51, 52.
In this automatic fire alarm system 1, forty to eighty slave devices 10 may be connected to each pair of cables 51, 52. Furthermore, fifty to two hundred pairs of cables 51, 52 may be connected to the single master device 20. For example, in a situation where at most forty slave devices 10 are connectible to each pair of cables 51, 52 and at most fifty pairs of cables 51, 52 are connectible to the single master device 20, up to 2,000 (= 40 × 50) slave devices 10 are connectible to the single master device 20. Note that these numerical values are only an example and should not be construed as limiting.
According to this embodiment, the master device 20 and the respective slave devices 10 operate synchronously with each other in accordance with a synch signal SY1 (see FIG. 3) transmitted from the master device 20 to the respective slave devices 10 to communicate with each other by the time division communication method.
FIG. 1 illustrates a state where only one of the slave devices 10 is connected to the single master device 20 via an associated one pair of cables 51, 52, and omits the illustration of the other slave devices 10 and the other pairs of cables 51, 52.
Next, the configuration and operation of the master device 20 will be described.
The master device 20 of this embodiment is a master device for an automatic fire alarm system 1 configured to transmit a signal to each of a plurality of slave devices 10 that are electrically connected to the pair of cables 51, 52 to which a voltage is applied. As shown in FIG. 1, the master device 20 includes a transmitter 24, a receiver 23, and a controller 27. The controller 27 includes a processor 271, a reception controller 273, and a transmission controller 274. The master device 20 further includes an application unit 21, a display unit 25, an interface unit 26, a coordination unit 28, and an emergency power supply 29. Note that the configurations of the display unit 25, the interface unit 26, the coordination unit 28, and the emergency power supply 29 will be described later.
The application unit 21 applies a DC voltage (of, e.g., 24 V) between the pair of cables 51, 52. The application unit 21 supplies operating power to each of the slave devices 10 connected to the pair of cables 51, 52.
A resistor 22 (with a resistance of 400 Ω to 600 Ω, for example) is inserted between one cable with the higher potential (e.g., the cable 51 in this embodiment) of the two cables 51, 52 and the application unit 21. The resistor 22 has two functions, namely, a first function of transforming a current signal transmitted through the pair of cables 51, 52 into a voltage signal and a second function of limiting the amount of a current flowing through the pair of cables 51, 52 when the cables 51, 52 are short-circuited with each other.
The transmitter 24 is electrically connected to the pair of cables 51, 52 and transmits a signal to each of the plurality of slave devices 10 by varying the voltage between the pair of cables 51, 52. The receiver 23 is also electrically connected to the pair of cables 51, 52 and receives the signal from each of the plurality of slave devices 10 based on a variation in voltage between the pair of cables 51, 52.
The controller 27 may be implemented as a microcomputer, for example, and performs the functions of the processor 271, the reception controller 273, and the transmission controller 274 by reading out and executing a program stored in a memory. Note that the program to be executed by the controller 27 may have been written in the memory in advance, or may also be provided by being stored on some storage medium such as a memory card or be downloaded through a telecommunications line such as the Internet.
The transmission controller 274 controls the transmitter 24. More specifically, the transmission controller 274 makes the transmitter 24 transmit a synch signal SY1 every time a predetermined amount of time T1 passes, as shown in FIG. 3. In FIG. 3, shown are two synch signals SY1 arranged time sequentially, of which the one transmitted earlier is designated as "synch signal SY11" and the one transmitted later is designated as "synch signal SY12."
Each of the plurality of slave devices B1-B16 (i.e., the slave devices 10) transmits its response signal SN1-SN16 by varying the voltage between the pair of cables 51, 52 after its waiting time W1-W16 has passed since the slave device 10 received the synch signal SY1. More specifically, the slave device B1 transmits a response signal SN1 by varying the voltage between the pair of cables 51, 52 after a waiting time W1 has passed since the slave device B1 received the synch signal SY1. Likewise, each of the other slave devices B2-B16 also transmits its response signal SN2-SN16 after its waiting time W2-W16 has passed since the slave device B2-B16 received the synch signal SY1. The waiting times W1-W16 are associated with the "slave devices B1-B16," respectively, and are defined to have mutually different lengths. In this embodiment, the waiting times W1-W16 are defined by respective pieces of unique identification information (e.g., addresses) assigned to the slave devices B1-B16.
The reception controller 273 controls the receiver 23. The reception controller 273 makes the receiver 23 o receive the response signal SN1-SN16 from the plurality of slave devices B1-B16 during their respective reception periods R1-R16 after their respective waiting times W1-W16 have passed since the transmitter 24 transmitted the synch signal SY1. The reception periods R1-R16 are time slots defined by the processor 271 to have the response signals SN1-SN16 received at the receiver 23. More specifically, the reception period R1 is a time slot to receive the response signal SN1. Likewise, the other reception periods R2-R16 are time slots to receive the response signals SN2-SN16, respectively. In other words, the reception periods R1-R16 are associated with the waiting times W1-W16, respectively. Information about the length of the waiting times W1-W16 is stored in a storage medium such as a memory.
A predetermined amount of time T1 is a time interval between transmission timings when the transmission controller 274 has the synch signal SY1 transmitted at regular intervals from the transmitter 24. The predetermined amount of time T1 is defined by the processor 271. In other words, the processor 271 determines the predetermined amount of time T1. For example, the processor 271 may determine the predetermined amount of time T1 by reading out an initial value for the predetermined amount of time T1 stored in a memory. In addition, the processor 271 acquires data included in the response signals SN1-SN16 from the output of the receiver 23.
The predetermined amount of time T1 is defined by the processor 271 to be long enough to allow the response signals SN1-SN16 to fall within their associated reception periods R1-R16, respectively. In other words, the predetermined amount of time T1 is defined by the processor 271 such that each of the response signals SN1-SN16 falls within an associated one of the reception periods R1-R16 without overlapping with any other unassociated one of the reception periods R1-R16.
The processor 271 defines a communication period C1 and an omnibus response period T2 after having had the synch signal SY1 transmitted from the transmitter 24. The master device 20 transmits a request signal in the communication period C1. As used herein, the request signal is a signal with an arbitrary type of data requesting each slave device 10 to transmit a signal. For example, the request signal may be a signal with request data requesting each slave device 10 to perform a self-diagnosis on itself and return a result of the self-diagnosis. Alternatively, the request signal may also be a signal with request data requesting only a slave device 10 that has detected a fire to respond. Each of the slave devices 10 transmits its response signal SN1-SN16, as a response to the request signal, within an associated one of the reception periods R1-R16.
The omnibus response period T2 is a period in which the receiver 23 is made to receive the response signals SN1-SN16 transmitted by the respective slave devices B1-B16 in response to the request signal sent from the master device 20 during the communication period C1. In the omnibus response period T2, the processor 271 determines, by the waiting times W1-W16, the reception periods R1-R16 to receive the response signals SN1-SN16 from the respective slave devices B1-B16. The processor 271 identifies, by determining the ongoing period to be any one of the reception periods R1-R16, the slave device B1-B16 that has transmitted the response signal SN1-SN16 received. In addition, the processor 271 also recognizes the data included in the response signals SN1-SN16 from the slave devices B1-B16.
The configuration and operation of the slave devices B1-B16 (hereinafter collectively referred to as "slave devices 10") will be described.
Each of the slave devices 10 (note that only one of the slave devices 10 is shown in FIG. 1) includes a transmitter circuit 15, a receiver circuit 16, a controller 19, a storage unit 17, and a sensing unit 13. In addition, each of the slave devices 10 further includes a diode bridge (DB) 11, a power supply circuit 12, and an alarm unit 14. The slave device 10 is connected to the pair of cables 51, 52.
The receiver circuit 16 receives a signal by sensing a variation in voltage between the pair of cables 51, 52. The receiver circuit 16 receives a request signal transmitted from the transmitter 24 of the master device 20 and outputs a result of the reception to the controller 19.
The transmitter circuit 15 has the function of pulling in a current flowing through the pair of cables 51, 52 and the function of stopping pulling in the current. As the amount of the current flowing through the pair of cables 51, 52 varies, a voltage drop at the resistor 22 of the master device 20 causes a variation in voltage between the pair of cables 51, 52. The transmitter circuit 15 changes the voltage level between the pair of cables 51, 52 from one of three stages to another, thus transmitting a signal notifying the master device 20 of a non-alarm condition, a fire alarm, and a coordination notification. Note that the number of stages of the voltage level to be changed by the transmitter circuit 15 between the pair of cables 51, 52 does not have to be three, but may also be any other number as long as the fire alarm can be sounded to say the least.
The diode bridge 11 includes a pair of input terminals to which the pair of cables 51, 52 are electrically connected, and a pair of output terminals, to which the power supply circuit 12, the transmitter circuit 15, and the receiver circuit 16 are electrically connected.
Next, it will be described in detail with reference to FIG. 3 how the plurality of slave devices B1-B16 operate.
Each of the plurality of slave devices B1-B16 starts clocking on receiving the synch signal SY11. Each slave device B1-B16 may record time with a timer which counts clock pulses, for example. The slave devices B1-B16 make the timer record their respective waiting times W1-W16 after having received the synch signal SY11. In the response periods S1-S16 after the waiting times W1-W16 have passed since the reception of the synch signal SY11, the slave devices B1-B16 transmit the response signals SN1-SN16, respectively, with the voltage between the pair of cables 51, 52 varied.
Each of the response periods S1-S16 is defined for an associated one of the slave devices B1-B16. Each of the response periods S1-S16 starts at a point in time (hereinafter referred to as "starting timing") when an associated one of the waiting times W1-W16 has passed since the reception of the synch signal SY1 by the receiver circuit 16. That is to say, the response periods S1-S16 are defined based on the waiting times W1-W16, respectively. Also, the response periods S1-S16 are periods in which their respective controllers 19 transmit the response signals SN1-SN16, respectively. In other words, the controllers 19 have the response signals SN1-SN16 transmitted from their respective transmitter circuits 15 during the response periods S1-S16 that have been defined based on the waiting times W1-W16, respectively.
Specifically, the waiting time W1 of the slave device B1 is as long as the communication period C1. The length of the waiting time W2 may be the sum of the waiting time W1 and a constant time interval T5, for example. Likewise, the length of the waiting time W3 may be the sum of the waiting time W2 and the constant time interval T5, for example. That is to say, the length of any one of the waiting times W1-W16 associated with one of the plurality of slave devices B1-B16 is different from that of the previous or following one of the waiting times W1-W16 by the constant time interval T5. In other words, each of the reception periods R1-R16 is as long as the constant time interval T5.
The controller 19 may be implemented as a microcomputer, for example, and performs desired functions by executing a program stored in a memory. Note that the program may have been written in the memory in advance, or may also be provided by being stored on some storage medium such as a memory card or be downloaded through a telecommunications line such as the Internet.
The controller 19 controls the transmitter circuit 15, the receiver circuit 16, the storage unit 17, and the alarm unit 14. The controller 19 acquires the data included in the request signal from the result of reception of the receiver circuit 16. The controller 19 has one of the response signals SN1-SN16 transmitted from the transmitter circuit 15 in an associated one of the response periods S1-S16 in response to the request signal.
The controller 19 of each of the slave devices B1-B16 makes the transmitter circuit 15 transmit two signals, namely, an associated one of the response signals SN1-SN16 and an associated one of alarm signals A1-A16, in their associated response period S1-S16. Each of the response signals SN1-SN16 is a signal with data responding to the request signal from the master device 20. Each of the alarm signals A1-A16 is a signal notifying the master device 20 of a non-alarm condition, a fire alarm, or a coordination notification. The coordination notification is a signal instructing other devices 30 (see FIG. 2), connected to the master device 20, to operate in coordination with the fire detecting operation of the slave devices 10.
In this embodiment, the response periods S1-S16 are shorter in time length than the reception periods R1-R16 defined by the master device 20. The controller 19 of each of the slave devices B1-B16 defines a guard period G1 between the starting timing of an associated one of the reception periods R1-R16 and that of an associated one of the response periods S1-S16. In addition, the controller 19 of each of the slave devices B1-B16 also defines another guard period G2 between the ending timing of an associated one of the response periods S1-S16 and that of an associated one of the reception periods R1-R16. Thus, the sum of the guard period G1, the response period S1, and the guard period G2 is as long as the reception period R1. The controller 19 prohibits the transmitter circuit 15 from transmitting any signal during the guard periods G1 and G2. The guard periods G1 and G2 are provided to make it less easy for a plurality of slave devices B1-B16 to transmit signals simultaneously.
During the interval between the timing when the synch signal SY1 (synch signal SY11) starts to be received and the timing when the synch signal SY11 finishes to be received, the controller 19 is in condition to operate in a normal mode. Next, during the interval between the timing when the synch signal SY11 finishes to be received and the timing when the next synch signal SY1 (synch signal SY12) starts to be received, the controller 19 operates in a "standby mode" in which the controller 19 consumes less power than in the "normal mode" in which the controller 19 operates normally. In the standby mode, the controller 19 is in a standby state in which the controller 19 consumes less power than in the normal operating state. In addition, in the standby state, the controller 19 disables all functions but the clocking function and the function of returning from the standby state to the normal state, thus reducing the power consumption. On entering the standby state, the controller 19 of each of the slave devices B1-B16 starts clocking from zero with the counter of the timer reset. Thereafter, before the starting timing of an associated one of the reception periods R1-R16 is reached, the controller 19 returns from the standby state to the normal state. Then, at a point in time when the starting timing of an associated one of the response periods S1-S16 is reached, the controller 19 of each of the slave devices B1-B16 has an associated response signal SN1-SN16 and an associated alarm signal A1-A16 transmitted from the transmitter circuit 15. That is to say, the controller 19 assumes the operating state while receiving the synch signal SY1 and enters the standby state while receiving no synch signal SY1.
The power supply circuit 12 includes a capacitor to be charged with the power supplied from the pair of cables 51, 52. The power supply circuit 12 supplies sufficient power to allow the transmitter circuit 15, the receiver circuit 16, the controller 19, the storage unit 17, and the sensing unit 13 to perform their respective functions.
The alarm unit 14 may include a buzzer, an LED, and other members, and is configured to alarm surrounding people to the outbreak of a fire. The operation of the alarm unit 14 is controlled by the controller 19.
The storage unit 17 may be implemented as an electrically erasable programmable read-only memory (EEPROM), for example. The storage unit 17 stores identification information unique to its associated slave device B1-B16. The unique identification information is a piece of information to be used for the master device 20 to uniquely identify each of the plurality of slave devices 10 and has no redundancy with any other piece of identification information. The storage unit 17 also stores a criterion for the controller 19 to determine whether the transmitter circuit 15 should be made to transmit a fire alarm or a coordination notification. Examples of the criteria include a threshold value set for the output of the sensing unit 13 and the number of times of sampling.
The controller 19 checks the detection value of the sensing unit 13 at regular intervals and determines, by the criterion stored in the storage unit 17, whether or not any fire has broken out. The controller 19 selects a signal to be transmitted to the master device 20 (such as a fire alarm, a coordination notification or a signal notifying the master device 20 of a non-alarm condition) based on the detection value of the sensing unit 13 and the criterion and has that selected signal transmitted from the transmitter circuit 15.
Other devices 30 (see FIG. 2) are electrically connected to the master device 20. Examples of those other devices 30 include smoke prevention and exhaustion systems such as fire doors and smoke exhaustion equipment, emergency broadcasting systems, devices for transferring a fire alarm to external devices, and fire extinguishing equipment including sprinklers. On receiving the coordination notification from any slave device 10, the master device 20 transmits a signal, instructing the other devices 30 to coordinate, to the other devices 30.
The coordination unit 28 outputs such a signal, instructing the other devices 30 to coordinate, to the other devices 30. The operation of the coordination unit 28 is controlled by the processor 271. On sensing the receipt of the coordination notification, the processor 271 may make the coordination unit 28 output a signal instructing the other devices 30 to coordinate with the slave device 10.
The emergency power supply 29 may be a storage battery, for example. The emergency power supply 29 is configured to have power of such a capacity as allowing the fire alarm system 1 to operate for a certain amount of time even in cases of power failure.
The display unit 25 may include a light-emitting diode (LED), a liquid crystal display, an organic electroluminescent display, or any other suitable type of display device. The operation of the display unit 25 is controlled by the processor 271. The processor 271 changes the content of the information to be displayed on the display unit 25 according to the information provided by the signal received through the pair of cables 51, 52. The display unit 25 may display some type of information indicating the outbreak of a fire in the multi-family dwelling house 60 and the floor on which the fire has broken out, for example.
The interface unit 26 may include a press button switch or a touchscreen type display, for example. The interface unit 26 may be configured to allow the processor 271 to stop the fire alarm operation, the operation of detecting any abnormality in any slave device 10, or any other type of operation.
Next, it will be described in detail with reference to FIG. 3 how the master device 20 and the respective slave devices 10 perform communication-related operations.
The transmission controller 274 of the master device 20 makes the transmitter 24 transmit the synch signal SY1 to the pair of cables 51, 52 at regular intervals. The processor 271 defines the communication period C1 after the transmission controller 274 has had the synch signal SY1 transmitted from the transmitter 24 to record the amount of time that has passed since the starting timing of the communication period C1. In the communication period C1, the transmission controller 274 makes the transmitter 24 transmit a request signal for the plurality of slave devices 10. When the ending timing of the communication period C1 is reached, the processor 271 defines the omnibus response period T2. For the omnibus response period T2, reception periods R1-R16 (time slots), which are divided in the time axis direction, are set.
The transmission controller 274 of the master device 20 makes the transmitter 24 transmit a synch signal SY1 (synch signal SY11) to start clocking. Then, when the amount of time recorded reaches a predetermined amount of time T1, the transmission controller 274 makes the transmitter 24 transmit another synch signal SY1 (synch signal SY12). The transmission controller 274 has the synch signal SY1 transmitted every time the amount of time recorded reaches the predetermined amount of time T1. The transmission controller 274 makes the transmitter 24 transmit a request signal during the communication period C1 after having had the synch signal SY11 transmitted.
In each of the slave devices B1-B16, when the receiver circuit 16 receives the synch signal SY11, the controller 19 then makes the receiver circuit 16 receive the request signal that has been transmitted during the communication period C1. The controller 19 of each of the slave devices B1-B16 has its response signal SN1-SN16 transmitted from the receiver circuit 16 in response to the request data included in the request signal received during the communication period C1 in one of the response periods S1-S16 associated with the slave device 10. In the following description, the operation of the slave devices B1, B2, and B16 in the omnibus response period T2 will be described as their typical exemplary operation. Note that since the other slave devices B3-B15 operate in basically the same way as the slave device B2, description of their operation will be omitted herein.
The controller 19 of the slave device B1 starts clocking at a point in time when the receiver circuit 16 receives the synch signal SY11. The controller 19 does not allow the transmitter circuit 15 to transmit any signals during the guard period G1. When the ending timing of the guard period G1 is reached, the controller 19 starts clocking for the response period S1. In the response period S1, the controller 19 makes the transmitter circuit 15 transmit a response signal SN1 and an alarm signal A1.
The controller 19 of the slave device B1 makes the transmitter circuit 15 transmit, in the response period S1, the response signal SN1 in response to the request signal received from the master device 20 during the communication period C1. After having had the response signal SN1 transmitted from the transmitter circuit 15, the controller 19 of the slave device B1 makes the transmitter circuit 15 transmit an alarm signal A1. The processor 271 of the master device 20 determines, based on the data included in the alarm signal A1, the condition of the slave device B1 to be one of a non-alarm condition, a fire alarm condition, or a coordination notification condition.
When the ending timing of the response period S1 is reached, the controller 19 of the slave device B1 enters a standby state. On entering the standby state, the controller 19 starts clocking from zero with the counter of the timer reset. Thereafter, before the starting timing of the reception period R1 is reached, the controller 19 will return from the standby state to the normal state. Then, at a point in time when the starting timing of the response period S1 is reached, the controller 19 has the response signal SN1 and the alarm signal A1 transmitted from the transmitter circuit 15. The same statement applies to the operation of the controller 19 of each of the slave devices B2-B16 returning from the standby state to the normal state.
When the ending timing of the communication period C1 is reached, the controller 19 of the slave device B2 enters the standby state. Thereafter, before the starting timing of the reception period R2 is reached, the controller 19 returns to the normal state. Then, when the ending timing of the guard period G1 of the reception period R2 is reached, the controller 19 of the slave device B2 has the response signal SN2 and the alarm signal A2 transmitted from the transmitter circuit 15. When the ending timing of the response period S2 is reached, the controller 19 changes from the normal state to the standby state.
When the ending timing of the communication period C1 is reached, the controller 19 of the slave device B16 enters a standby state. Thereafter, before the starting timing of the reception period R16 is reached, the controller 19 returns to the normal state. Then, when the ending timing of the guard period G1 of the reception period R16 is reached, the controller 19 of the slave device B16 has a response signal SN16 and an alarm signal A16 transmitted from the transmitter circuit 15. When the ending timing of the response period S16 is reached, the controller 19 of the slave device B16 is still in the operating state to receive the synch signal SY12 and the request signal included in the communication period C1. Thereafter, when the ending timing of the communication period C1 is reached, the controller 19 of the slave device B16 enters the standby state.
FIG. 3 illustrates an exemplary situation where every time the transmitter circuit 15 of the slave device B1 transmits the response signal SN1, the transmitter 24 of the master device 20 transmits the synch signal SY1 (i.e., the synch signal SY11, SY12). However, this is only an example and should not be construed as limiting. Alternatively, the processor 271 of the master device 20 may also determine the predetermined amount of time T1 such that the synch signal SY1 is transmitted when the transmitter circuit 15 of each of the slave devices B1-B16 transmits its response signal SN1-SN16 a predetermined number of times. In other words, two or more omnibus response periods T2 may be defined for the predetermined amount of time T1. For example, the synch signal SY1, the communication period C1, and a plurality of omnibus response periods T2 may be defined so as to recur in this order periodically. Stated otherwise, the predetermined amount of time T1 may be greater than the sum of as many reception periods R1-R16 as the slave devices B1-B16. For instance, the predetermined amount of time T1 may be defined to be n times (where n is an integer equal to or greater than two) as long as the combined length of the communication period C1 and the omnibus response period T2. The longer the predetermined amount of time T1 is, the smaller the number of times the synch signal SY1 is transmitted per unit time. Since the amount of time it takes to transmit the synch signal SY1 accounts for a decreased percentage of the total duration of communication between the master device 20 and the slave devices 10, the duration of communication with the slave devices 10 increases relatively, thus allowing the master device 20 to efficiently receive the signals from all slave devices 10 in a shorter time.
After having received the synch signal SY11, the controller 19 of each of the slave devices 10 records its associated waiting time W1-W16, thereby defining the starting timing and ending timing for its associated response period S1-S16. In a situation where the controller 19 is clocking with a timer, an oscillator circuit outputting a clock signal to the timer may have low accuracy. In that case, the longer the predetermined amount of time T1 is, the longer the time lags of the starting and ending timings of each of the response periods S1-S16 with respect to the associated reception period R1-R16 may become. It will be described as a comparative example a situation where the controller 19 is clocking with a timer and an oscillator circuit outputting a clock signal to the timer has low accuracy.
If an oscillator circuit outputting a clock signal to the timer of the controller 19 as a comparative example has low accuracy, the longer the predetermined amount of time T1 is, the longer the time lags of the starting and ending timings of each of the response periods S1-S16 with respect to its associated reception period R1-R16 may become. When the starting and ending timings of each of the response periods S1-S16 have significant time lags with respect to the associated reception period R1-R16, two slave devices 10 may output response signals simultaneously (i.e., a signal collision may occur). In that case, the processor 271 of the master device 20 may be unable to recognize the response signals and the alarm signals correctly.
Such a time lag may be decreased by increasing the oscillator circuit accuracy of the timer of the controller 19 as a comparative example, extending the length of the guard period G1, G2, or shortening the predetermined amount of time T1.
The time lags of each of the response periods S1-S16 with respect to the associated reception period R1-R16 could be decreased by increasing the oscillator circuit accuracy of the timer for the controller 19 of the comparative example (i.e., by increasing the clock accuracy). However, an increase in the oscillator circuit accuracy causes an increase in the power consumption of the oscillator circuit. For example, the slave devices 10 according to this embodiment have a consumption current of several hundred µA or less, while the oscillator circuit outputting clock pulses with high accuracy has a power consumption of several mA. That is why it is difficult to increase the clock accuracy of the oscillator circuit while reducing the power consumption of the slave devices 10.
Alternatively, defining each of the guard periods G1, G2 of the comparative example to be an extended period allows the response periods S1-S16 to fall within the reception periods R1-R16, respectively, even if the time lag described above increases. However, this causes an increase in the predetermined amount of time T1 as well. In that case, as the number of slave devices 10 connected to the master device 20 increases, the predetermined amount of time T1 becomes longer. The longer the predetermined amount of time T1 is, the longer the waiting time before the starting timing of the response period S1 is reached will be, if the slave device B1 has detected the outbreak of a fire in a period other than the response period S1. That is to say, it may take a longer time before the slave device B1 transmits a fire alarm to the master device 20 after having detected the outbreak of a fire.
Shortening the predetermined amount of time T1 of the comparative example may decrease the lag in synchronization timing between the master device 20 and the respective slave devices 10. However, defining the predetermined amount of time T1 to be relatively short for the number of slave devices 10 results in a shorter response period S1 for each slave device 10. As the response period S1 becomes shorter, the chances of the slave device B1 failing to transmit the response signal SN1 or the alarm signal A1 increase. FIG. 4A illustrates the communication state of the slave devices B1-B16 according to this embodiment, while FIG. 4B illustrates the communication state of the slave devices B1-B16 according to a comparative example. Note that the communication states of only two slave devices B1 and B16 are shown in FIGS. 4A and 4B. According to the comparative example, a predetermined amount of time Txl indicating the transmission interval of the synch signal SY1 is defined to be shorter than the predetermined amount of time T1. Also, according to the comparative example, the respective response periods S1-S16 are defined to be shorter than their counterparts of this embodiment. The slave devices B1-B16 of the comparative example transmit alarm signals Ax1-Ax16 shorter in duration than the alarm signals A1-A16. The shorter the duration of the alarm signals Ax1-Ax16 is, the greater the chances of the master device 20 either erroneously recognizing, or even failing to recognize, the respective alarm signals Ax1-Ax16 received. On top of that, the shorter the duration of the response signals SN1-SN16 is, the greater the chances of the master device 20 either erroneously recognizing, or even failing to recognize, the data included in the response signals SN1-SN16 received. For these reasons, the predetermined amount of time T1 needs to be defined to include the response periods S1-S16 that are long enough for the master device 20 to correctly receive the response signals SN1-SN16 and the alarm signals A1-A16.
Next, the operation of the processor 271 of the master device 20 defining the predetermined amount of time T1 will be described. For example, the processor 271 may establish test communication with the controller 19 of each of the slave devices B1-B16 in a state where the operation mode is set to be a test mode. As used herein, the test mode of the processor 271 is different from a normal mode in which a fire alarm is sounded to alert people to the outbreak of a fire but is an operation mode to set the predetermined amount of time T1. That is to say, the processor 271 chooses either the normal mode in which an alarm operation is performed when the receiver 23 receives a fire alarm or the test mode. For example, when the interface unit 26 performs the operation of switching the operation modes, the processor 271 makes a switch between the normal mode and the test mode. In the normal mode, when the receiver 23 receives a fire alarm transmitted from the transmitter circuit 15 of the slave device 10, the processor 271 performs an alarm operation to alarm people to the outbreak of a fire. In the test mode, the transmission controller 274 makes the transmitter 24 transmit a testing signal. Also, in the test mode, the reception controller 273 makes the receiver 23 receive a testing response signal from the transmitter circuit 15 of each slave device 10.
In the following description, it will be described how the master device 20 and the respective slave devices 10 operate in the test mode. The transmission controller 274 makes the transmitter 24 transmit a testing signal in the communication period C1, for example. The reception controller 273 makes the receiver 23 receive testing response signals from the respective slave devices B1-B16 in the reception periods R1-R16, respectively. The reception controller 273 determines whether or not the data included in the testing response signals received by the receiver 23 is correct. The correctness of the data may be checked by cyclic redundancy check or parity check, for example.
The processor 271 of the master device 20 defines a first amount of time TT1 for testing as the predetermined amount of time T1, and makes the transmitter 24 of the master device 20 transmit the synch signal SY1 and the testing signal a number of times. If the reception controller 273 has confirmed the correctness of the data included in the testing response signals received by the receiver 23 of the master device 20 from all slave devices 10, then the processor 271 newly calculates a different predetermined amount of time T1 by adding a second amount of time TT2 for testing to the predetermined amount of time T1, and makes the transmitter 24 transmit a testing signal. If the reception controller 273 has confirmed the correctness of the data included in the testing response signals received by the receiver 23 from all slave devices 10, then the processor 271 newly calculates a different predetermined amount of time T1 by adding a second amount of time TT2 for testing to the predetermined amount of time T1. Then, the processor 271 makes the transmitter 24 transmit a testing signal repeatedly. The larger the number of times the reception controller 273 has confirmed the correctness of the data included in the testing response signals received by the receiver 23 from all slave devices 10, the larger the value of the predetermined amount of time T1 becomes. Suppose the reception controller 273 has determined that the receiver 23 has not correctly received the data included in a testing response signal from at least one slave device 10. In that case, the processor 271 defines the predetermined amount of time T1 that has been determined in the previous test mode (or an even earlier test mode) as the predetermined amount of time T1 for the normal mode. Then the processor 271 changes from the test mode to the normal mode. That is to say, the processor 271 allows the transmitter 24 to transmit the synch signal SY1 and defines the length of the longest period in a situation where the data included in the response signals SN1-SN16 and the alarm signals A1-A16 has been received correctly as the predetermined amount of time T1. This allows the transmission controller 274 to transmit the synch signal SY1 before the lag described above becomes too significant for the reception controller 273 to correctly recognize the data included in the response signals SN1-SN16 and the alarm signals A1-A16. This reduces the chances of causing interference between the response signals SN1-SN16 from the slave devices B1-B16 even without increasing the oscillator circuit accuracy of the timer for the controller 19, increasing the length of the guard period G1, G2, or shortening the predetermined amount of time T1.
As can be seen from the foregoing description, the master device 20 according to this embodiment is a master device for an automatic fire alarm system 1 configured to transmit signals to a plurality of slave devices B1-B16 (slave devices 10) that are electrically connected to a pair of cables 51, 52, to which a voltage is applied. The master device 20 includes a transmitter 24, a transmission controller 274, a receiver 23, and a reception controller 273. The transmitter 24 is electrically connected to the pair of cables 51, 52 and configured to transmit the signals to the plurality of slave devices 10 by varying the voltage between the pair of cables 51, 52. The transmission controller 274 is configured to control the transmitter 24 to make the transmitter 24 transmit a synch signal SY1 every time a predetermined amount of time T1 passes. The receiver 23 is electrically connected to the pair of cables 51, 52 and configured to receive signals from the plurality of slave devices 10 in accordance with a variation in the voltage between the pair of cables 51, 52. The reception controller 273 is configured to control the receiver 23. The plurality of slave devices B1-B16 (slave devices 10) transmit their respective response signals SN1-SN16 by varying the voltage between the pair of cables 51, 52 after their respective waiting times W1-W16 have passed since the reception of the synch signal SY1. The waiting times W1-W16 vary their length from one of the plurality of slave devices B1-B16 to another. The reception controller 273 makes the receiver 23 receive the respective response signals SN1-SN16 from the plurality of slave devices B1-B16 (slave devices 10) during their respective reception periods R1-R16 after their respective waiting times W1-W16 have passed since the transmission of the synch signal SY1 by the transmitter 24. The predetermined amount of time T1 is long enough to allow the response signals SN1-SN16 to fall within their respective reception periods R1-R16.
According to this configuration, the predetermined amount of time T1 is long enough to allow response signals SN1-SN16 to fall within their respective reception periods R1-R16, and therefore, the response signals SN1-SN16 are less likely to fall out of their associated reception periods R1-R16, respectively. Every time a predetermined amount of time T1 passes, the plurality of slave devices 10 records their respective waiting times W1-W16 since the reception of the synch signal SY1 transmitted from the transmitter 24. After their respective waiting times W1-W16 have passed, the plurality of slave devices 10 transmit their respective response signals SN1-SN16. That is why even if the timing when the response signal SN1-SN16 starts to be transmitted has been advanced or delayed with respect to the time when the synch signal SY1 was received last time, each of the plurality of slave devices 10 is still able to adjust the time lag of the starting timing of its associated response signal SN1-SN16 with respect to the synch signal SY1 by receiving the synch signal SY1. In other words, the master device 20 for the automatic fire alarm system 1 is able to reduce the chances of causing interference between the response signals SN1-SN16 transmitted from the plurality of slave devices 10.
In the master device 20 for the automatic fire alarm system 1 according to this embodiment, the processor 271 has two operation modes, namely, the normal mode and the test mode, and defines the predetermined amount of time T1 in the test mode. The processor 271 defines the predetermined amount of time T1 to be the longest one in a situation where the reception controller 273 has determined that the data included in the response signals SN1-SN16 and the alarm signals A1-A16 has been received correctly by the receiver 23 in the test mode. That is why even if the lag of the starting timing of any of the response periods S1-S16 with respect to the associated reception period R1-R16 increases, the lag of the transmission starting timing of the response signal SN1-SN16 is adjusted every time the predetermined amount of time T1 passes. This allows the master device 20 to reduce the chances of causing interference between the response signals SN1-SN16 transmitted from the respective slave devices 10. In addition, the synch signal SY1 is transmitted a decreased number of times per unit time. Thus, the duration of communication with the slave devices 10 accounts for a relatively increased percentage of the total duration of communication between the master device 20 and the slave devices 10. This allows the master device 20 to efficiently receive the signals from all slave devices 10 in a shorter time.
In the master device 20 of this embodiment, the processor 271 establishes a test communication with each of the slave devices B1-B16 when its operation mode is set to be a test mode. The processor 271 operating in the test mode carries out the test communication with the controller 19 of each of the slave devices B1-B16 repeatedly, thus increasing the predetermined amount of time T1 stepwise. The processor 271 defines the predetermined amount of time T1 to be the longest one T1 in a situation where the receiver 23 has correctly received the data included in the response signals SN1-SN16 and the alarm signals A1-A16, and stops increasing the predetermined amount of time T1. This reduces the chances of causing interference between the response signals SN1-SN16 transmitted from the plurality of slave devices 10 while decreasing the number of times the synch signal SY1 is transmitted per unit time, even if the oscillator circuit of the slave devices 10 has relatively low accuracy.
In the master device 20 according to this embodiment, the predetermined amount of time T1 is suitably equal to or greater than a sum of the respective reception periods R1-R16 of all of the plurality of slave devices B1-B16 (slave devices 10).
According to this configuration, the predetermined amount of time T1 (corresponding to the transmission interval of the synch signal SY1) is defined to be equal to or longer than the total amount of time it takes for the slave devices B1-B16 to transmit their respective response signals SN1-SN16, thus causing a decrease in the number of times the synch signal SY1 is transmitted per unit time. This increases the percentage of the duration of communication with the slave devices 10 to the total duration of communication between the master device 20 and the slave devices 10. This allows the master device 20 to efficiently receive the signals from all slave devices 10 in a shorter time.
An automatic fire alarm system 1 according to this embodiment includes: the master device 20 described above; and a plurality of slave devices B1-B16 (slave devices 10), which are connected to the pair of cables 51, 52 and configured to transmit their respective response signals SN1-SN16 by varying the voltage between the pair of cables 51, 52 after their respective waiting times W1-W16 have passed since reception of the synch signal SY1.
According to this configuration, the automatic fire alarm system 1 includes the master device 20 described above, and therefore, is able to adjust the lag of the starting timing when the response signal SN1-SN16 of any of the slave devices B1-B16 starts to be transmitted. In other words, the automatic fire alarm system 1 is able to reduce the chances of causing interference between the respective response signals SN1-SN16 transmitted from the plurality of slave devices B1-B16.
A slave device B1-B16 (slave device 10) according to this embodiment is designed to be used in the automatic fire alarm system 1.
According to this configuration, the slave device B1-B16 (slave device 10) is able to adjust the lag of the starting timing when the response signal SN1-SN16 starts to be transmitted in response to the synch signal SY1 transmitted from the master device 20. In other words, the slave devices B1-B16 (slave devices 10) of the automatic fire alarm system 1 are able to transmit the response signals SN1-SN16 with the chances of causing interference between them reduced.
Each slave device B1-B16 for an automatic fire alarm system 1 according to this embodiment transmits its associated response signal SN1-SN16 and its associated alarm signal A1-A16 within an associated one of response periods S1-S16 corresponding to respective reception periods R1-R16. This allows each of the response signals SN1-SN16 and the alarm signals A1-A16 to be transmitted with the chances of falling out of its associated reception period R1-R16 reduced.
The slave device 10 of this embodiment suitably assumes an operating state (corresponding to the normal mode according to the embodiment described above) while receiving the synch signal SY1 and assumes a standby state (corresponding to the standby mode according to the embodiment described above), which consumes less power than in the operating state, while receiving no synch signals SY1.
This configuration allows the slave device 10 to assume the standby state, consuming less power than in the operating state, while no synch signals SY1 are transmitted from the transmitter 24, thus reducing the power consumption of the slave device 10.
In the embodiment described above, each of the waiting times W1-W16 is defined based on the identification information unique to an associated one of the slave devices 10. However, this is only an example and should not be construed as limiting. Alternatively, the waiting time W1-W16 may also be defined by any appropriate method for each of the slave devices 10. That is to say, the waiting times W1-W16 just need to be defined so that a plurality of slave devices 10 do not transmit signals simultaneously.
Information about the length of the waiting times W1-W16 does not have to be stored in a storage medium such as a memory but may also be set with a dip switch, for example.
In the embodiment described above, the predetermined amount of time T1 is defined by the processor 271. However, this is only an example and should not be construed as limiting. Alternatively, the predetermined amount of time T1 may also be determined in accordance with the command input through the interface unit 26.
Also, in the embodiment described above, the processor 271 starts recording the predetermined amount of time T1 at the timing when the synch signal SY1 starts to be transmitted. However, this is only an example and should not be construed as limiting. That is to say, the timing when the predetermined amount of time T1 starts to be recorded does not have to be the same as the timing when the synch signal SY1 starts to be transmitted. Alternatively, the processor 271 may start recording the predetermined amount of time T1 at a point in time when a small amount of time has passed since the timing when the synch signal SY1 starts to be transmitted. As used herein, the "small amount of time" is long enough for each of the plurality of slave devices 10 to recognize the received signal as the synch signal SY1 based on the data included in the received signal. Still alternatively, the timing when the predetermined amount of time T1 starts to be recorded may also be a timing when the synch signal SY1 finishes being transmitted, i.e., the timing when the communication period C1 begins.
Furthermore, in the embodiment described above, the controller 19 of each of the slave devices 10 defines the guard periods G1, G2. Optionally, at least one of the guard periods G1, G2 may be omitted.
Furthermore, in the embodiment described above, the controller 19 of the plurality of slave devices 10 always assumes the standby state except during a period in which the receiver circuit 16 receives the synch signal SY1 and during the communication period C1 in which the receiver circuit 16 receives the request signal. However, this is only an example and should not be construed as limiting. Alternatively, the controller 19 may also be configured to selectively assume either the standby state or the operating state during the communication period C1.
Furthermore, in the embodiment described above, the processor 271, the reception controller 273, and the transmission controller 274 are implemented as the single controller 27. However, this is only an example and should not be construed as limiting. Alternatively, the processor 271, the reception controller 273, and the transmission controller 274 may also be implemented as separately provided microcomputers or integrated circuits (ICs) to serve as arithmetic logic units, for example.
Furthermore, in the embodiment described above, each slave device 10 stores identification information in the memory of its controller 19. However, this is only an example and should not be construed as limiting. Alternatively, the identification information may also be set with a dip switch or any other means provided for the slave device 10, for example.
Furthermore, in the embodiment described above, each of the master device 20 and the slave devices 10 transmits a signal by varying a voltage applied between a pair of cables 51, 52 with the amount of a current flowing through the pair of cables 51, 52 varied. However, this is only an example and should not be construed as limiting. Alternatively, each of the master device 20 and the slave devices 10 may also transmit a signal by directly varying the voltage between the pair of cables 51, 52.
Furthermore, the automatic fire alarm system 1 of the embodiment described above uses a pair of cables 51, 52 just like the pair of cables for use in known P-type automatic fire alarm systems. That is why when the automatic fire alarm system 1 of this embodiment is introduced into a multi-family dwelling house or any other type of building that uses the known P-type automatic fire alarm system, the pair of cables of the known automatic fire alarm system may be used without newly installing another pair of cables. Optionally, the automatic fire alarm system 1 may also be implemented by replacing the master device and slave devices of the known P-type automatic fire alarm system with the master device 20 and the slave devices 10, respectively.

(Variation of first embodiment)

In the first embodiment described above, the controller 19 of each of the slave devices 10 provides the guard periods G1, G2 before and after its associated response period. Optionally, the guard periods G1, G2 may be omitted. Such an example with no guard periods G1, G2 will be described as a variation of the first embodiment. FIG. 5 illustrates how communication is carried out between the master device 20 and slave devices 10 according to this variation.
In this variation, each of the reception periods R21-R36 is defined by the master device 20 to be as long as an associated one of the response periods S1-S16 of the slave devices B1-B16. In other words, each of the reception periods R21-R36 is as long as the period obtained by removing the guard periods G1, G2 from an associated one of the reception periods R1-R16 of the first embodiment. That is why the ending timing of each of the reception periods R21-R35 and the starting timing of the next proximate one of the reception periods R22-R36 are defined at the same point in time.
Each of the reception periods R21-R36 is defined to be shorter in length than an associated one of the reception periods R1-R16 of the first embodiment. That is why the overall length of the omnibus response period T21 including all of these reception periods R21-R36 may be defined to be shorter than that of the omnibus response period T2 of the first embodiment. Shortening the omnibus response period T21 means shortening the interval between the point in time of reception of the synch signal SY1 and the starting timing of each of the response periods S1-S16. This decreases the lag of the starting timing of each of the response periods S1-S16.
Nevertheless, a lag of the starting timing of any of the response periods S1-S16 could sometimes cause a slight temporal overlap between two successive response periods. If two signals overlap with each other so as to increase the value of the voltage between the pair of cables 51, 52, then the voltage value becomes greater than a voltage value while a signal is being transmitted normally. The processor 271 of the master device 20 regards, as noise, any surplus of the voltage between the pair of cables 51, 52 over a predetermined upper limit value in the vicinity of each of the starting and ending timings of the reception periods R21-R36, and distinguishes the noise from the response signals SN1-SN16. As used herein, the predetermined value of the voltage value is a value obtained by adding a margin to the value of the voltage generated between the pair of cables 51, 52 when a single slave device 10 transmits the response signal. Supposing the response periods S1 and S2 slightly overlap with each other, the magnitude of the variation in voltage between the pair of cables 51, 52 increases only instantaneously, compared to a situation where the response periods S1 and S2 do not overlap with each other.
The master device 20 regards this voltage signal with the greater magnitude of variation as noise. If the period during which the response signals SN1, SN2 are transmitted simultaneously is shorter than the transmission duration of one bit, which is transmitted during each of the response periods S1 and S2, then the master device 20 is able to receive the noise and the response signals SN1-SN16 separately from each other.
Meanwhile, if two signals overlap with each other to decrease the value of the voltage between the pair of cables 51, 52, that voltage value becomes smaller than the voltage value when signals are transmitted normally. The processor 271 of the master device 20 regards, as noise, any deficit in the voltage between the pair of cables 51, 52 under a predetermined lower limit value in the vicinity of each of the starting and ending timings of any reception period R21-R36, and distinguishes the noise from the response signals SN1-SN16.
In the test mode, the master device 20 defines the predetermined amount of time T11 such that the period during which two successive response periods overlap with each other is shorter than the transmission duration of one bit of the response signals SN1-SN16. The operation of the master device 20 defining the predetermined amount of time T11 in the test mode will not be described again, because the foregoing description for the test mode of the first embodiment applies mostly to this variation simply by replacing the predetermined amount of time T1 with the predetermined amount of time T11.
The predetermined amount of time T11 is the interval from the transmission timing of the synch signal SY1 through the ending timing of the reception period R36, and is equivalent to the transmission interval of the synch signal SY1. FIG. 5 illustrates an example in which the predetermined amount of time T11 is defined to be the sum of the transmission period of the synch signal SY1, the communication period C1, and the omnibus response period T21. Alternatively, the predetermined amount of time T11 may also be the sum of the product of the length of the omnibus response period T21 and an integer of two or more, the length of the transmission period of the synch signal SY1, and the length of the communication period C1. After the reception controller 273 has received the response signals SN1-SN16 from the respective slave devices B1-B16 a number of times, the transmission controller 274 may have the synch signal SY12 transmitted from the transmitter 24. This increases the percentage of the response signals SN1-SN16 transmitted from the slave devices 10 to the signals transmitted to the pair of cables 51, 52 by decreasing the number of times the synch signal SY1 is transmitted per unit time. Consequently, this allows the master device 20 to communicate with all slave devices 10 in a shorter time.
As described above, in the master device 20 of this variation, the lengths of each pair of successive waiting times W1-W16 of the plurality of slave devices B1-B16 (slave devices 10) are suitably different from each other by the constant time interval T5, and each of the reception periods R21-R36 is suitably as long as the constant time interval T5.
According to this configuration, each of the reception periods R21-R36 is as long as the constant time interval T5, and therefore, is also as long as an associated one of the response periods S1-S16. The length of each of the reception periods R21-R36 is the minimum length falling within an associated one of the response periods S1-S16, and therefore, the sum of the respective lengths of the reception periods R21-R36 (i.e., the overall length of the omnibus response period T21) can be minimized. The shorter the sum of the lengths of the reception periods R21-R36 is, the smaller the lag of the starting timing of each of the response periods S1-S16 of the slave devices 10 tends to be. This allows the master device 20 to increase the transmission interval of the synch signal SY1 (corresponding to the predetermined amount of time T11) to adjust the lag. This increases the percentage of the response signals SN1-SN16 transmitted from the slave devices 10 to the signals transmitted to the pair of cables 51, 52, thus allowing the master device 20 to communicate with all slave devices 10 in a shorter time.
The master device 20 of this variation regards, as noise, any surplus of the voltage between the pair of cables 51, 52 over a predetermined value in the vicinity of each of the starting and ending timings of the reception periods R21-R36, and distinguishes the noise from the response signals SN1-SN16. This allows the master device 20 to distinguish the last bit of one response signal from the first bit of the next response signal overlapping with the last bit, and therefore, to receive the response signals SN1-SN16 separately from each other.
In the variation described above, the period during which the response signals SN1 and SN2 are transmitted simultaneously is shorter than the amount of time it takes to transmit one bit of the data included in the response signals SN1, SN2. However, this is only an example and should not be construed as limiting. Alternatively, the period during which the response signals SN1 and SN2 are transmitted simultaneously may be shorter than the amount of time it takes to transmit multiple bits of the data included in the response signals SN1, SN2. For example, the processor 271 of the master device 20 may have the capability to detect and correct errors of multiple bits (e.g., two bits) of the data received. In that case, even if multiple bits (e.g., two bits) of the data included in the response signals SN1, SN2 are not received correctly, the processor 271 is still able to recognize the data included in the response signals SN1-SN16. This allows the processor 271 to define the predetermined amount of time T11 to be an even longer time.

(Second embodiment)

A master device 20b according to a second embodiment is configured to, when connected to multiple pairs of cables as shown in FIG. 6, communicate with slave devices 10 connected to at least one pair of cables 51, 52. FIG. 6 illustrates a schematic configuration for an automatic fire alarm system 1b according to this embodiment. The master device 20b has the same configuration as the master device 20 of the first embodiment. In the following description, any constituent member of the second embodiment having the same function as the counterpart of the first embodiment described above will be designated by the same reference numeral as that counterpart's, and a detailed description thereof will be omitted herein.
When one pair of cables is regarded as a single communications channel, four communications channels are connected to the transmitter 24 (see FIG. 1) and the receiver 23 (see also FIG. 1) according to this embodiment. Specifically, the master device 20b is connected to one communications channel (implemented as one pair of cables 51, 52) and three other communications channels (implemented as three pairs of cables 53, 54). Four slave devices 10 (slave devices B1-B4) are connected to the one pair of cables 51, 52. Likewise, four slave devices 70 are connected to the cables 53, 54 in each of the three other pairs. That is to say, twelve slave devices 70 (slave devices E1-E12) are connected in total to the three other pairs of cables 53, 54. On detecting the outbreak of a fire, each of the slave devices 70 short-circuits its associated pair of cables 53, 54 to notify the master device 20b of the outbreak of the fire. Unlike the slave devices 10, none of the slave devices 70 have the function of transmitting a response signal in response to a request signal from the master device 20b. That is to say, in this automatic fire alarm system 1b, the slave devices 10, each having the capability to transmit a response signal in response to the request signal from the master device 20b, and the slave devices 70, each having no capability to transmit a response signal in response to the request signal from the master device 20b, are all connected to the master device 20b.
Each of the three pairs of cables 53, 54 has one of the two ends thereof, opposite from the other end connected to the master device 20b, connected to a terminal resistor 41. The master device 20b is able to detect any disconnection on each pair of cables 53, 54 by measuring the value of a current flowing through the pair of cables 53, 54. Note that the terminal resistor 41 is not an essential component and may be omitted.
The transmission controller 274 (see FIG. 1) of the master device 20b makes the transmitter 24 transmit the synch signal SY1 and a request signal for the communication period C1 to each of the four pairs of cables, namely, the one pair of cables 51, 52 and the three pairs of cables 53, 54. The controller 19 of each of the slave devices B1-B4 (see FIG. 1) makes the transmitter circuit 15 transmit its response signal SN1-SN4 in response to the request signal. The reception controller 273 (see FIG. 1) makes the receiver 23 receive the response signals SN1-SN4 transmitted to the pair of cables 51, 52 during the reception periods R1-R4, respectively. The processor 271 of the master device 20b (see FIG. 1) senses the slave devices B1-B4 connected to the pair of cables 51, 52. On the other hand, since none of the slave devices E1-E12 transmit any response signal in response to the request signal, the processor 271 determines that the slave devices 10 are not connected to any pair of cables 53, 54.
Suppose the transmission controller 274 has determined that the slave devices 10 are connected to the pair of cables 51, 52. In that case, when the predetermined amount of time T1 passes since a point in time when the transmission controller 274 made the transmitter 24 transmit the synch signal SY1 (synch signal SY11), the transmission controller 274 makes the transmitter 24 transmit another synch signal SY1 (synch signal SY12) to the pair of cables 51, 52. Thereafter, every time the predetermined amount of time T1 passes since the transmission controller 274 made the transmitter 24 transmit the synch signal SY1, the transmission controller 274 makes the transmitter 24 transmit the synch signal SY1 to the pair of cables 51, 52. On the other hand, the transmission controller 274 does not make the transmitter 24 transmit the synch signal SY1 to any of the three other pairs of cables 53, 54 to which the slave devices 10 are not connected. That is to say, even though the slave devices 10 and the slave devices 70 are all connected to the same master device 20b, the master device 20b is still able to communicate with the slave devices 10 on an individual basis by transmitting the synch signal SY1. Thus, the master device 20b reduces the chances of causing interference between the response signals SN1-SN4 transmitted from the plurality of slave devices B1-B4 (slave devices 10).
As described above, a plurality of (e.g., four in this embodiment) communications channels, each of which is made up of the pair of cables 51, 52, are connected to the transmitter 24 and the receiver 23 according to this embodiment. The transmission controller 274 makes the transmitter 24 transmit the synch signal SY1 to at least one communication channel (e.g., the pair of cables 51, 52 in this embodiment) to which the plurality of slave devices B1-B4 (slave devices 10) are connected.
According to this configuration, when the slave devices B1-B4 (slave devices 10) are connected to the at least one communications channel (one pair of cables 51, 52), the master device 20b transmits the synch signal SY1 to that communications channel. This allows the master device 20b to reduce the chances of causing interference between the response signals SN1-SN4 transmitted from the plurality of slave devices B1-B4 (slave devices 10).
Even though the slave devices B1-B4 (slave devices 10) and the slave devices 70 with no capability to transmit any response signal in response to the request signal from the master device 20b are all connected to the same master device 20b, the master device 20b is still able to transmit the synch signal SY11 to the slave devices B1-B4 and receive their respective response signals SN1-SN4. That is why even if the slave devices 10 and the slave devices 70 are all connected to the same master device 20b, the master device 20b is still able to adjust the lag of the starting timing of any of the response periods S1-S4 with respect to an associated one of the reception periods R1-R4. In other words, the master device 20b is able to reduce the chances of causing interference between the response signals SN1-SN4 transmitted from the plurality of slave devices B1-B4 (slave devices 10).

(Third embodiment)

A master device 20c and an automatic fire alarm system 1c including the master device 20c will be described with reference to FIGS. 7 and 8. The master device 20c of the third embodiment includes a comparator 272 as shown in FIG. 7. The other constituent elements of this embodiment have the same configuration as their counterparts of the first embodiment described above, and each of those elements will be designated by the same reference numeral as their counterpart's, and a detailed description thereof will be omitted herein.
The reception periods R41-R56 of this embodiment respectively correspond to the reception periods R1-R16 of the first embodiment. The master device 20c includes a comparator 272 for comparing the starting timing of each of the reception periods R41-R56 with the reception timing of one of the response signals SN1-SN16 associated with the reception period R41-R56. The processor 271 defines the predetermined amount of time T1 based on a result of the comparison made by the comparator 272.
The comparator 272 compares, with a reference value, the time lag D1 between the starting timing of each of the reception periods R41-R56 and the reception timing of one of the response signals SN1-SN16 associated with the reception period R41-R56. In this embodiment, the reference value is the length of the guard period G1. As shown in Portion A of FIG. 8, the guard period G1 is shorter than the remainder of the reception period R42 from which the response period S2 is subtracted. For example, the length of the guard period G1 may be obtained by evenly dividing, by two, the remainder of the reception period R42 from which the response period S2 is subtracted.
The comparator 272 outputs a result of the comparison to the processor 271. The comparator 272 may be implemented by making the controller 27 read out and execute a program stored in a memory. Note that the program implementing the function of the comparator 272 may have been written in the memory in advance, or may also be provided by being stored on some storage medium such as a memory card or be downloaded through a telecommunications line such as the Internet.
Portions A-C of FIG. 8 illustrate how the master device 20c and the slave device B2 (slave device 10) communicate with each other. Each of portions A-C of FIG. 8 illustrates the reception period R42 defined by the master device 20c during the transmission of the synch signal SY1, and the response signal SN2 transmitted by the slave device B2 in response to the synch signal SY1. The starting timing of the reception period R42 is defined to be a point in time when the waiting time W2 has passed since the transmission controller 274 finished transmitting the synch signal SY11. Note that the operation of each of the slave devices B1 and B3-B16 communicating with the master device 20c is the same as the operation of the master device 20c communicating with the slave device B2, and description thereof will be omitted herein.
Portion A of FIG. 8 illustrates a situation where there is no need to adjust the lag of the transmission starting timing of the response signal SN2 for the response period S2. The transmission starting timing of the response signal SN2 (i.e., the starting timing of the response period S2) is almost the same as the ending timing of the guard period G1. Also, in Portion A of FIG. 8, the guard periods G1 and G2 have almost the same length. The transmission controller 274 of the master device 20c defines the reception period R420 when the predetermined amount of time T1 has passed since the starting timing at which the synch signal SY1 started to be transmitted from the transmitter 24.
When the starting timing at which the response signal SN2 is transmitted from the transmitter circuit 15 (i.e., the starting timing of the response period S2) is reached, the controller 19 of the slave device B2 makes the transmitter circuit 15 transmit the response signal SN2. The comparator 272 measures the length of the time lag D1 from a point in time when the starting timing of the reception period R42 is reached to a point in time when the response signal SN2 is received. In this embodiment, the time lag D1 is obtained based on the number of clock pulses counted by the timer. In Portion A of FIG. 8, the time lag D1 is almost as long as the guard period G1. If the processor 271 has determined the time lag D1 to be almost as long as the guard period G1, the processor 271 does not change the predetermined amount of time T1. The transmission controller 274 makes the transmitter 24 transmit the synch signal SY12 when the predetermined amount of time T1 has passed since the synch signal SY11 was transmitted from the transmitter 24.
Portion B of FIG. 8 illustrates an exemplary situation where the starting timing of the response period S2 defined by the controller 19 of the slave device B2 has become closer (i.e., has become earlier) with respect to the starting timing of the reception period R42. The reception timing of the response signal SN2 (i.e., the starting timing of the response period S2) has become earlier than the ending timing of the guard period G1. Such a situation may arise when one period of oscillation of the oscillator circuit has become slightly shorter in the controller 19 of the slave device B2. The time lag D1 in Portion B of FIG. 8 is shorter than the time lag D1 in Portion A of FIG. 8. Supposing the transmission controller 274 makes the transmitter 24 transmit the synch signal SY12 at a point in time when the predetermined amount of time T1 has passed since the synch signal SY11 was transmitted, the time lag D1 may become even shorter.
The comparator 272 outputs a result of comparison, indicating that the length of the time lag D1 has become shorter than that of the guard period G1, to the processor 271. In accordance with this decision made by the comparator 272, the processor 271 defines the predetermined amount of time T43 to be a period longer than the predetermined amount of time T1. For example, the processor 271 obtains the predetermined amount of time T43 by adding the difference, calculated by subtracting the length of the time lag D1 from that of the guard period G1, to the predetermined amount of time T1, and defines the predetermined amount of time T43 thus obtained as a changed predetermined amount of time T1. In other words, the processor 271 defines the predetermined amount of time T43, obtained by adding the length of the interval in which the response period S1 and the guard period G1 overlap with each other to the predetermined amount of time T1, as the changed predetermined amount of time T1. At a point in time when the predetermined amount of time T43 has passed since the synch signal SY11 started to be transmitted, the transmission controller 274 makes the transmitter 24 transmit the synch signal SY21. When the predetermined amount of time T1 has passed since the synch signal SY11 started to be transmitted, the reception controller 273 defines the reception period R421. That is to say, the reception controller 273 defines a point in time when the waiting time W2 has passed since the predetermined amount of time T1 passed to be the starting timing of the reception period R421. On the other hand, the transmission timing of the response signal SN2 (i.e., the starting timing of the response period S2) is defined with respect to the point in time when the synch signal SY12 was transmitted (i.e., a point in time when the predetermined amount of time T43 has passed since the synch signal SY11 was transmitted). That is why the reception timing of the response signal SN2 (i.e., the starting timing of the response period S2) lags behind the starting timing of the reception period R421. That is to say, the transmission timing of the response signal SN2 (i.e., the starting timing of the response period S2) that has become closer to the starting timing of the reception period R42 is corrected into a timing closer to the ending timing of the guard period G1. In other words, the processor 271 changes the predetermined amount of time T1 into a longer one if the time lag D1 is less than the reference value (i.e., the length of the guard period G1).
Portion C of FIG. 8 illustrates an exemplary situation where the transmission timing of the response signal SN2 defined by the controller 19 of the slave device B2 (i.e., the starting timing of the response period S2) has been delayed (i.e., has become later) with respect to starting timing of the reception period R42. Such a situation may arise when one period of oscillation of the oscillator circuit has become slightly longer in the controller 19 of the slave device B2. The transmission timing of the response signal SN2 (i.e., the starting timing of the response period S2) has become later than the ending timing of the guard period G1. The time lag D1 in Portion C of FIG. 8 is longer than the time lag D1 in Portion A of FIG. 8. Supposing the transmission controller 274 makes the transmitter 24 transmit the synch signal SY12 at a point in time when the predetermined amount of time T1 has passed since synch signal SY11 was transmitted, the time lag D1 may become even longer.
The comparator 272 outputs a result of comparison, indicating that the length of the time lag D1 has become longer than that of the guard period G1, to the processor 271. In accordance with this decision made by the comparator 272, the processor 271 defines the predetermined amount of time T44 to be a shorter period than the predetermined amount of time T1. For example, the processor 271 obtains the predetermined amount of time T44 by calculating the difference in length between the guard period G1 and the time lag D1 and then subtracting the difference thus calculated from the predetermined amount of time T1, and defines the predetermined amount of time T44 thus obtained as a changed predetermined amount of time T1. In other words, the processor 271 defines the predetermined amount of time T44, obtained by subtracting the length of the interval between the ending timing of the guard period G1 and the starting timing of the response period S2 from the predetermined amount of time T1, as the changed predetermined amount of time T1. At a point in time when the predetermined amount of time T44 has passed since the synch signal SY11 started to be transmitted, the transmission controller 274 makes the transmitter 24 transmit the synch signal SY31. When the predetermined amount of time T1 has passed since the synch signal SY11 started to be transmitted, the reception controller 273 defines the reception period R431. That is to say, the reception controller 273 defines a point in time when the waiting time W2 has passed since the predetermined amount of time T1 passed to be the starting timing of the reception period R431. On the other hand, the transmission timing of the response signal SN2 (i.e., the starting timing of the response period S2) is defined with respect to the point in time when the synch signal SY31 was transmitted (i.e., a point in time when the predetermined amount of time T44 has passed since the synch signal SY11 was transmitted). That is why the reception timing of the response signal SN2 (i.e., the starting timing of the response period S2) becomes closer with respect to the starting timing of the reception period R431. That is to say, the transmission timing of the response signal SN2 (i.e., the starting timing of the response period S2) that has become closer to the ending timing of the reception period R42 is corrected into a timing closer to the ending timing of the guard period G1. In other words, the processor 271 changes the predetermined amount of time T1 into a shorter one if the time lag D1 is greater than the reference value (i.e., the length of the guard period G1).
The processor 271 of the master device 20c changes the predetermined amount of time T1 in accordance with the result of comparison made by the comparator 272. The processor 271 is allowed, while operating in the normal mode, to adjust the lag of the reception timing of each of the response signals SN1-SN16 from the slave devices 10 (i.e., the starting timing of each of the response periods S1-S16) with respect to an associated one of the reception periods R41-R56. This allows the master device 20c to reduce the chances of causing interference between the response signals SN1-SN16 transmitted from the plurality of slave devices B1-B16.
As described above, the master device 20c of this embodiment further includes the comparator 272 for comparing, with a reference value, the time lag D1 between the starting timing of each of the reception periods R41-R56 and the reception timing of one of the response signals SN1-SN16 associated with the reception period R41-R56. If the time lag D1 is greater than the reference value (e.g., the length of the guard period G1 in this embodiment), the predetermined amount of time T1 is changed into a shorter one (e.g., the predetermined amount of time T1 is defined to be as long as the predetermined amount of time T44 in this embodiment).
According to the configuration described above, the processor 271 changes the predetermined amount of time T1 in accordance with a result of comparison made by the comparator 272. Even if a starting timing at which a slave device 10 starts to transmit the response signal SN1-SN16 is delayed with respect to the starting timing of an associated one of the reception periods R41-R56, the delay may still be adjusted by changing the predetermined amount of time T1 into a shorter one. In addition, even if the starting timing at which the slave device 10 transmits the response signal SN1-SN16 is advanced (i.e., has become earlier) with respect to the starting timing of an associated one of the reception periods R41-R56, the processor 271 is still able to adjust the advance by changing the predetermined amount of time T1 into a longer one. This allows the master device 20c to reduce the chances of causing interference between the response signals SN1-SN16 transmitted from the plurality of slave devices B1-B16.
In the embodiment described above, the length of the guard period G1 is used as a reference value with respect to the time lag D1. However, this is only an example and should not be construed as limiting. The reference value may also be a value stored in a storage medium such as a memory or a value set for a dip switch or any other device, for example. Alternatively, the reference value with respect to the time lag D1 may also be determined based on the latency from a point in time when the processor 271 made the transmitter 24 transmit the request signal to a point in time when the receiver 23 receives the response signal. The processor 271 may transmit the request signal and receive the response signal either only once or a number of times, and may determine the reference value with respect to the time lag D1 based on the average of the latencies from the point in time when the transmitter 24 was made to transmit the request signal to the point in time when the receiver 23 receives the response signals.
In the embodiment described above, the comparator 272 compares the time lag D1 between the reception period R42 and the response period S2 with the reference value every time the comparator 272 receives the response signal SN2. However, this is only an example and should not be construed as limiting. Alternatively, the comparator 272 may compare the time lag D1 between the reception period R42 and the response period S2 with the reference value every n times (where n is an integer equal to or greater than two) the comparator 272 receives the response signal SN2.
In the embodiment described above, it has been described how the comparator 272 operates in the reception periods R42, R421, and R431 and the response period S2. However, this is only an example and should not be construed as limiting. Alternatively, the comparator 272 may measure the length of the time lag D1 in each of the reception periods R1-R16 and response periods S1-S16 according to the first embodiment. In that case, the predetermined amount of time T1 may be changed based on the longest time lag D1 at any of the starting timings of the response periods S1-S16.
The comparator 272 may also measure the length of the time lag between the ending timing of the reception period R42 and the reception ending timing of the response signal SN2. That is to say, the comparator 272 may also be configured appropriately to measure the length of the lag of the reception timing of any of the response signals SN1-SN16 with respect to the associated reception period R1-R16.
In the first embodiment and its variation and the second and third embodiments, the processor 271 changes the predetermined amount of time T1 (predetermined amount of time T11). However, this is only an example and should not be construed as limiting. Alternatively, the controller 27 may change the predetermined amount of time T1 (predetermined amount of time T11) by executing a program. Still alternatively, a microcomputer other than the one functioning as the controller 27, an IC for performing arithmetic operations, and other computers or processors may also be configured to change the predetermined amount of time T1 (predetermined amount of time T11).
Optionally, the first embodiment, the variation thereof, and the second and third embodiments may be combined with each other. For example, the master device 20b of the second embodiment may also be configured to include the comparator 272 and communicate with the slave devices B1-B4 by defining the predetermined amount of time T1 and the reception periods R1-R4 in the same way as in the first embodiment.

(Fourth embodiment)

A master device according to a fourth embodiment and an automatic fire alarm system including the master device will be described with reference to FIGS. 9A and 9B. The master device and automatic fire alarm system of this embodiment have the same configuration as their counterparts of the third embodiment described above. Therefore, any pair of corresponding elements will be designated by the same reference numeral, and a detailed description thereof will be omitted herein.
In the master device of this embodiment, the processor 271 (see FIG. 7) and the comparator 272 (see FIG. 7) operate differently from their counterparts of the third embodiment. Also, the reception periods R61-R76 to be described below respectively correspond to the reception periods R1-R16 of the first embodiment.
The processor 271 chooses either an omnibus response mode or a divisional response mode. In the omnibus response mode, the processor 271 controls the reception controller 273 (see FIG. 7) to make the receiver 23 (see FIG. 7) receive the response signals SN1-SN16 from all of the sixteen slave devices B1-B16 (slave devices 10) (see FIGS. 2 and 7). The processor 271 operating in the omnibus response mode defines sixteen reception periods R61-R76 as shown in FIG. 9A.
On the other hand, in the divisional response mode, the processor 271 transmits a synch signal SY1 (synch signal SY51) and a request signal H51 to make the receiver 23 receive the response signals SN1-SN8 transmitted from one group of eight slave devices B1-B8 (one group of slave devices), for example, as shown in FIG. 9B. At a point in time when the predetermined amount of time T51 has passed since the synch signal SY51 was transmitted, the processor 271 operating in the divisional response mode transmits another synch signal SY1 (synch signal SY52). Then, the processor 271 transmits another request signal H52 to make the receiver 23 (see FIG. 7) receive the response signals SN9-SN16 from the other group of eight slave devices B9-B16 (the other group of slave devices). That is to say, in the divisional response mode, the processor 271 divides the sixteen slave devices B1-B16 into the two groups and makes the receiver 23 receive the response signals transmitted from all of the eight slave devices 10 belonging to each of the two groups. In this embodiment, the master device operating in the divisional response mode transmits the synch signal SY1 (synch signal SY51, SY52) every time the predetermined amount of time T51, which is long enough to receive all of the response signals transmitted from the eight slave devices 10, passes. In the divisional response mode, the synch signal SY1 is transmitted at shorter intervals than in the omnibus response mode, thus more frequently requiring each of the slave devices B1-B16 to adjust the lag of the transmission timing of an associated one of the response signals SN1-SN16 with respect to the starting timing of an associated divisional reception period R511-R518. This reduces the lag of the transmission timing of each response signal SN1-SN16 with respect to the starting timing of its associated divisional reception period R511-R518. In other words, this allows the master device for an automatic fire alarm system according to this embodiment to reduce the chances of causing interference between the response signals SN1-SN16 transmitted from the plurality of slave devices 10.
Next, it will be described in more detail how the processor 271 and the comparator 272 operate.
Choosing the omnibus response mode as operation mode, the processor 271 controls the transmission controller 274 (see FIG. 7) to make the transmitter 24 (see FIG. 7) transmit the synch signal SY1 (synch signal SY11). The processor 271 also controls the transmission controller 274 to make the transmitter 24 transmit a request signal H1 in the communication period C1. The request signal H1 includes data requesting all of the sixteen slave devices B1-B16 to transmit their respective response signals SN1-SN16.
For example, the comparator 272 records the starting timing of the reception period R70 and the reception timing of the response signal SN10 associated with the reception period R70, thus calculating the time lag D1 between the starting timing of the reception period R70 and the reception timing of the response signal SN10. The comparator 272 compares the absolute value K1 of the difference between the time lag D1 and a first reference value F1 with a second reference value F2, and outputs a result of the comparison to the processor 271. The first reference value F1 and the second reference value F2 may be each defined to be one half as long as the guard period G1, for example.
When provided by the comparator 272 with a result of comparison that the absolute value K1 of the difference between the time lag D1 and the first reference value F1 is equal to or greater than the second reference value F2, the processor 271 chooses the divisional response mode as its operation mode. An exemplary situation where the reception timing of the response signal SN10 has advanced to be earlier than the ending timing of the guard period G1 as shown in FIG. 9A will be described.
Since the reception timing of the response signal SN10 is earlier than the ending timing of the guard period G1, the time lag D1 is less than one half as long as the guard period G1.
The comparator 272 calculates the absolute value K1 of the difference between the time lag D1 and the first reference value F1. The absolute value K1 (i.e., the absolute value of the difference in length between the guard period G1 and the time lag D1) is more than one half as long as the guard period G1. The comparator 272 outputs a result of comparison, indicating that the absolute value K1 of the difference between the time lag D1 and the first reference value F1 is equal to or greater than the second reference value F2, to the processor 271. In accordance with the result of comparison provided by the comparator 272, the processor 271 chooses the divisional response mode as the operation mode. Next, it will be described in further detail how the processor 271 operates in the divisional response mode.
The processor 271 controls the transmission controller 274 to make the transmitter 24 transmit a synch signal SY1 (synch signal SY51) in the divisional response mode after the predetermined amount of time T1 has passed since the synch signal SY1 (synch signal SY11) was transmitted from the transmitter 24 in the omnibus response mode. The processor 271 controls the transmission controller 274 to make the transmitter 24 transmit the request signal H51 during the communication period C1 following the transmission of the synch signal SY1 (synch signal SY51) as shown in FIG. 9B. The request signal H51 includes data requesting the plurality of slave devices B1-B8 to transmit their respective response signals SN1-SN8. In other words, the request signal H51 includes data requesting one group of slave devices B1-B8, among the plurality of slave devices B1-B16 (slave devices 10) that have been classified into two groups, each consisting of eight slave devices 10, to transmit response signals SN1-SN8, respectively.
The processor 271 defines an omnibus response period T22 after having had the request signal H51 transmitted during the communication period C1. The omnibus response period T22 in the divisional response mode is made up of divisional reception periods R511-R518 for receiving the response signals SN1-SN8, respectively. The divisional reception periods R511-R518 respectively correspond to the reception periods R1-R8 according to the first embodiment. The response periods S1-S8 fall within the divisional reception periods R511-R18, respectively. Two guard periods G1, G2 are provided before and after each of the response periods S1-S8. The divisional reception periods R511-R518 are reception periods, of which the number corresponds to that of the slave devices 10 designated by the request signals H51, H52. This is a major difference between the divisional reception periods R511-R518 and the reception periods R1-R16 in the omnibus response period T2. That is to say, the number of the reception periods R1-R16 in the omnibus response period T2 according to the first embodiment is defined by that of the slave devices 10. On the other hand, the omnibus response period T22 according to this embodiment has a length varying with the number of slave devices 10 designated by the request signal H51, H52.
Choosing the divisional response mode, the processor 271 changes the predetermined amount of time T1 into a shorter one. Depending on the number of slave devices 10 designated by the request signal H51, H52, the processor 271 changes the transmission interval of the synch signal SY1 from the predetermined amount of time T1 into a predetermined amount of time T51 shorter than the predetermined amount of time T1. According to this embodiment, the number of slave devices 10 designated by the request signal H51, H52 is eight. The predetermined amount of time T51 is the sum of the length of the synch signal SY1, the length W511 of the communication period C1, and the omnibus response period T22. In other words, the predetermined amount of time T51 is long enough for the response signals SN1-SN8 to fall within the divisional reception periods R511-R518, respectively. The processor 271 controls the reception controller 273 to make the receiver 23 receive the response signals SN1-SN8 and alarm signals A1-A8 in the divisional reception periods R511-R518, respectively.
When the receiver circuit 16 (see FIG. 7) of each of the slave devices B1-B8 forming one group receives the request signal H51, the controller 19 of each of the slave devices B1-B8 in the one group (see FIG. 7) starts recording an associated divisional waiting time W511-W518. On the other hand, the controller 19 of each of the slave devices B9-B16 forming the other group does not make the transmitter circuit 15 transmit any response signal SN9-SN16 in response to the request signal H51 received, and does not record any divisional waiting time.
The controller 19 of each of the slave devices B1-B8 forming the one group makes the transmitter circuit 15 (see FIG. 7) transmit an associated response signal SN1-SN8 after an associated divisional waiting time W511-W518 has passed since the synch signal SY1 (synch signal SY51) was received. The length of the divisional waiting time W511-W518 varies from one slave device B1-B8 to another in the group of slave devices B1-B8. Each of the divisional waiting times W511-W518 has been defined in advance by the number of slave devices 10 designated by the data included in the request signal H51, H52. In this embodiment, the request signal H51, H52 designates eight different slave devices 10, and eight divisional waiting times W511-W518 are stored in the memory of the master device and in the respective storage units 17 of the slave devices 10 (see FIG. 7) according to this embodiment.
The reception controller 273 makes the receiver 23 receive the response signals SN1-SN8, which have been transmitted from the respective transmitter circuits 15 of the group of slave devices B1-B8, in divisional reception periods R511-R518, respectively.
The processor 271 transmits the synch signal SY1 (synch signal SY52) at a point in time when the predetermined amount of time T51 has passed since the synch signal SY1 was transmitted. The processor 271 controls the transmission controller 274 to make the transmitter 24 transmit a request signal H52, designating slave devices B9-B16, during the communication period C1 after the synch signal SY1 (synch signal SY52) has been transmitted. The request signal H52 includes data requesting the plurality of slave devices B9-B16 to transmit the response signal SN9-SN16, respectively. In other words, the request signal H52 includes data requesting the transmitter circuit 15 of each of the slave devices B9-B16, forming a different group from the group of slave devices B1-B8 designated by the request signal H51, to transmit an associated one of the response signals SN9-SN16. The processor 271 controls the reception controller 273 to make the receiver 23 receive the response signals SN9-SN16 and alarm signals A9-A16 in the divisional reception periods R511-R518, respectively.
When the receiver circuit 16 of each of the slave devices B9-B16 forming the other group receives the request signal H52, the controller 19 of that slave device B9-B16 in the other group starts recording its associated divisional waiting time W511-W518. On the other hand, the controller 19 of each of the slave devices B1-B8 forming the one group does not make the transmitter circuit 15 transmit any response signal SN1-SN8 in response to the request signal H52 received, and does not record any divisional waiting time.
The controller 19 of each of the slave devices B9-B16 forming the other group makes the transmitter circuit 15 transmit an associated response signal SN9-SN16 after an associated divisional waiting time W511-W518 has passed. That is to say, the transmitter circuit 15 of each of the slave devices B9-B16 transmits the response signal SN9-SN16 in an associated one of the divisional reception periods R511-R518.
The reception controller 273 makes the receiver 23 receive the response signals SN9-SN16 from the other group of slave devices B9-B16 in the divisional reception periods R511-R518, respectively.
The processor 271 also changes the selected one group cyclically every time the synch signal SY1 (synch signal SY51, SY52) is transmitted from the transmitter 24. In this embodiment, the processor 271 alternately selects the group designating the slave devices B1-B8 with the other group designating the slave devices B9-B16. That is to say, the processor 271 controls the transmission controller 274 to make the transmitter 24 transmit the request signal H51 and the request signal H52 alternately in the communication period C1, every time the synch signal SY1 (synch signal SY52, SY52) is transmitted.
In the embodiment described above, the reception timing of the response signal SN10 has advanced to be earlier than the ending timing of the guard period G1 in an exemplary situation. Alternatively, the reception timing of the response signal SN10 may be delayed to be later than the ending timing of the guard period G1. Having obtained the absolute value of the difference between the time lag D1 and the first reference value F1, the comparator 272 is able to output a result of the comparison, no matter whether the reception timing of the response signal SN10 has become earlier or later than the ending timing of the guard period G1. This allows the processor 271 to shorten the predetermined amount of time T1 and increase the frequency of transmission of the synch signal SY1, even if the reception timing of the response signal SN10 has been delayed to be later than the ending timing of the guard period G1.
As can be seen from the foregoing description, an automatic fire alarm system master device according to this embodiment includes a comparator 272 and a processor 271. The processor 271 is configured to control the transmission controller 274 to make the transmitter 24 transmit a request signal H51, H52 and change the predetermined amount of time T1, every time the synch signal SY1 is transmitted from the transmitter 24. The plurality of slave devices B1-B16 (slave devices 10) are classified into at least two groups of slave devices. The request signal H51, H52 includes data requesting one group of slave devices, selected by the processor 271 from the at least two groups, to transmit their respective response signals SN1-SN16. In this embodiment, the plurality of slave devices B1-B16 (slave devices 10) are classified into two groups, namely, slave devices B1-B8 and slave devices B9-B16. The processor 271 chooses either an omnibus response mode or a divisional response mode. The omnibus response mode is a mode in which the response signals SN1-SN16 from all of the plurality of slave devices B1-B16 (slave devices 10) are received at the receiver 23. The divisional response mode is a mode in which the response signals (either response signals SN1-SN8 or response signals SN9-SN16) from the slave devices forming the one group (either slave devices B1-B8 or slave devices B9-B16) are received at the receiver 23. The comparator 272 compares the absolute value of a difference between a first reference value F1 and a time lag D1 from the starting timing of a reception period (e.g., the reception period R70 in this embodiment) to a reception timing of a response signal (e.g., the response signal SN10 in this embodiment) associated with the reception period with a second reference value F2. If the absolute value of the difference between the time lag D1 and the first reference value F1 is equal to or greater than the second reference value F2, the processor 271 chooses the divisional response mode. The processor 271, which has chosen the divisional response mode, controls the transmission controller 274 to make the transmitter 24 transmit the request signal H51, H52 and change the predetermined amount of time T1 into a shorter time. The processor 271 also changes the selected one group cyclically every time the synch signal SY1 is transmitted from the transmitter 24. The one group of slave devices (either the slave devices B1-B8 or the slave devices B9-B16) transmit their respective response signals (either the response signals SN1-SN8 or the response signals SN9-SN16) after their respective divisional waiting times W511-W518 have passed since the reception of the synch signal SY1. The divisional waiting times W511-W518 vary their length from one slave device to another in the one group of slave devices (either the slave devices B1-B8 or the slave devices B9-B16). The reception controller 273 makes the receiver 23 receive the response signals (either the response signals SN1-SN8 or the response signals SN9-SN16) from the plurality of slave devices forming the one group (either the slave devices B1-B8 or the slave devices B9-B16) during their respective divisional reception periods R511-R518. The divisional reception periods R511-R518 are reception periods after their respective divisional waiting times W511-W518 have passed since the transmission of the synch signal SY1 by the transmitter 24. The predetermined amount of time T51 is long enough to allow the response signals (either the response signals SN1-SN8 or the response signals SN9-SN16) to fall within their respective divisional reception periods R511-R518.
According to this configuration, the processor 271 of the master device according to this embodiment chooses the divisional response mode if the absolute value of the difference between the time lag D1 and the first reference value F1 is equal to or greater than the second reference value F2. The predetermined amount of time T51 in the divisional response mode is defined to be shorter than the predetermined amount of time T1 in the omnibus response mode. The processor 271 operating in the divisional response mode transmits a synch signal SY1 (synch signal SY51, SY52) every time the predetermined amount of time T51 passes. In the divisional response mode, the synch signal SY1 is transmitted at shorter intervals than in the omnibus response mode. This requires each of the slave devices B1-B8 (or slave devices B9-B16) to more frequently adjust the lag of the transmission timing of its associated response signal SN1-SN8 (or response signal SN9-SN16) with respect to the starting timing of an associated one of the divisional reception periods R511-R518. The processor 271 cyclically changes the selected one group every time the synch signal SY1 (synch signal SY51, SY52) is transmitted from the transmitter 24. This allows the processor 271 to make all of the slave devices B1-B16 transmit their respective response signals SN1-SN16 even in the divisional response mode, thus decreasing the lag of the transmission timing of each of the response signals SN1-SN8 (or the response signals SN9-SN16) with respect to the starting timing of its associated divisional reception period R511-R518. In other words, this allows the automatic fire alarm system master device according to this embodiment to reduce the chances of causing interference between the respective response signals SN1-SN16 transmitted from the plurality of slave devices 10.
In the embodiment described above, the processor 271 is supposed to operate by classifying the sixteen slave devices 10 into two groups, each consisting of eight slave devices. Alternatively, the processor 271 may also be configured to subdivide each of these two groups into a plurality of smaller groups. For example, if in one reception period within the omnibus response period T22, the absolute value of the difference between the time lag D1 and the first reference value F1 becomes equal to or greater than the second reference value F2, then the processor 271 may classify the sixteen slave devices 10 into four groups by subdividing each group of eight slave devices 10 into two sub-groups, each consisting of four slave devices. In that case, the predetermined amount of time T51 is shortened to a half. Furthermore, the processor 271 does not always have to evenly divide each group of original slave devices 10 into two halves but may also divide each group into a plurality of groups, each consisting of any appropriate number of slave devices. In that case, the master device and slave devices 10 according to this embodiment may be each configured to define their divisional waiting time in accordance with the data, included in the request signal, about the number of slave devices 10. Alternatively, the processor 271 may determine the number of the slave devices 10 that form each group so that each group is made up of almost the same number of slave devices 10 or arbitrarily determine the number of slave devices that form each group.
In the embodiment described above, the comparator 272 obtains the time lag D1. However, the time lag D1 does not have to be calculated by the comparator 272. Alternatively, the time lag D1 may also be determined by the processor 271, for example. Still alternatively, an arithmetic unit for calculating the time lag D1 may be provided separately as well.
Furthermore, in the embodiment described above, the comparator 272 is supposed to operate based on the time lag D1 with respect to the timing of reception of the response signal SN10 associated with the reception period R70. However, the time lag D1 does not have to be based on the reception period R70 and the response signal SN10. Alternatively, the comparator 272 may also use the time lag D1 between the starting timing of any arbitrary response period and the timing of reception of a response signal associated with the response period. Still alternatively, the comparator 272 may also use the time lags D1 of multiple arbitrary slave devices. In that case, the comparator 272 may define the average of the plurality of time lags D1 as a new time lag D1 or may also define the largest one of the time lags D1 as the new time lag D1.
Furthermore, in the embodiment described above, the divisional waiting times W511-W518 associated with the request signal H51, H52 are stored in the memory of the master device and the respective storage units 17 of the slave devices 10 according to this embodiment. However, this is only an example and should not be construed as limiting. Alternatively, the divisional waiting times W511-W518 associated with the request signal H51, H52 may also be obtained by the master device and slave devices 10 according to this embodiment executing their respective programs in accordance with the data included in the request signal H51, H52.
The processor 271 of this embodiment is applicable to the first embodiment except its variations and to the second embodiment.

Reference Signs List

1, 1b, 1c: Automatic Fire Alarm System
10, B1-B16: Slave Device
20, 20b, 20c: Master Device
23: Receiver
24: Transmitter
51, 52: Pair of Cables (Communication Channel)
53, 54: Pair of Cables (Communication Channel)
272: Comparator
273: Reception Controller
274: Transmission Controller
D1: Time Lag
H1, H51, H52: Request Signal
R1-R16, R21-R36: Reception Period
R41-R56, R61-R76, R421, R431: Reception Period
SN1-SN16: Response Signal
SY1, SY11, SY12, SY51, SY52: Synch Signal
T1, T11, T43, T44, T51: Predetermined Amount of Time
T5: Constant Time Interval
W1-W16: Waiting Time
W511-W518: Divisional Waiting Time
R511-R518: Divisional Reception Period

Claims

An automatic fire alarm system master device (20) configured to transmit signals to a plurality of slave devices (10, B1-B16) electrically connected to a pair of cables (51, 52), a voltage being applied to the pair of cables (51, 52), the automatic fire alarm system master device (20) comprising:
a transmitter (24) electrically connected to the pair of cables (51, 52) and configured to transmit the signals to the plurality of slave devices (10, B1-B16) by varying the voltage between the pair of cables (51, 52);

a transmission controller (274) configured to control the transmitter (24) to have a synch signal (SY1, SY11, SY12) transmitted from the transmitter (24) every time a predetermined amount of time passes;

a receiver (23) electrically connected to the pair of cables (51, 52) and configured to receive signals from the plurality of slave devices (10, B1-B16) in accordance with a variation in the voltage between the pair of cables (51, 52);

a reception controller (273) configured to control the receiver (23); and

a processor (271) configured to acquire data included in response signals (SN1-SN16) from an output of the receiver (23),

the plurality of slave devices (10, B1-B16) transmitting their respective response signals (SN1-SN16) by varying the voltage between the pair of cables (51, 52) after their respective waiting times (W1-W16) have passed since reception of the synch signal (SY1, SY11, SY12),

the waiting times (W1-W16) varying their length from one of the plurality of slave devices (10, B1-B16) to another,

the reception controller (273) making the receiver (23) receive the respective response signals (SN1-SN16) from the plurality of slave devices (10, B1-B16) during their respective reception periods (R21-R36) after the respective waiting times (W1-W16) have passed since transmission of the synch signal (SY1, SY11, SY12) by the transmitter (24),

the predetermined amount of time being long enough to allow the response signals (SN1-SN16) to fall within the respective reception periods (R21-R36),

characterized in that

any two successive ones of the waiting times (W1-W16) of the plurality of slave devices (10, B1-B16) are different in length from each other by a constant time interval (T5),

each of the reception periods (R21-R36) is as long as the constant time interval (T5),

the processor (271) is configured to regard, as noise, any surplus of the voltage between the pair of cables (51, 52) over a predetermined upper limit value in a vicinity of each of starting and ending timings of the reception periods (R21-R36), and is configured to distinguish the noise from the response signals (SN1-SN16), and/or

the processor (271) is configured to regard, as noise, any deficit in the voltage between the pair of cables (51, 52) under a predetermined lower limit value in a vicinity of each of starting and ending timings of the reception periods (R21-R36), and is configured to distinguish the noise from the response signals (SN1-SN16).
The automatic fire alarm system master device of claim 1, wherein
the predetermined amount of time is equal to or greater than a sum of the respective reception periods (R21-R36) of all of the plurality of slave devices (10, B1-B16).
The automatic fire alarm system master device of claim 1 or 2, further comprising
a comparator (272) configured to compare, with a reference value, a time lag (D1) between a starting timing of a reception period, selected from the reception periods (R1-R16), and a timing of reception of one of the response signals (R1-R16) associated with the reception period, wherein
if the time lag (D1) is greater than the reference value, the predetermined amount of time is changed into a shorter time.
The automatic fire alarm system master device of claim 1 or 2, comprising:
a comparator (272); and

a processor (271) configured to control the transmission controller (274) to make the transmitter (24) transmit a request signal and to change the predetermined amount of time, every time the synch signal (SY1, SY11, SY12, S51, S52) is transmitted from the transmitter (24), wherein

the plurality of slave devices (10, B1-B16) are classified into at least two groups of slave devices,

the request signal includes data requesting one group of slave devices, selected by the processor (271) from the at least two groups, to transmit their respective response signals,

the processor (271) chooses either an omnibus response mode in which the response signals from all of the plurality of slave devices (10, B1-B16) are received at the receiver (23) or a divisional response mode in which the response signals from only the one group of slave devices are received at the receiver (23),

the comparator (272) compares an absolute value of a difference between a first reference value and a time lag (D1) from a starting timing of a reception period, selected from the reception periods (R1-R16), to a timing of reception of one of the response signals (SN1-SN16) associated with the reception period with a second reference value,

if the absolute value of the difference is equal to or greater than the second reference value, the processor (271) chooses the divisional response mode, controls the transmission controller (274) to make the transmitter (24) transmit the request signal, and changes the predetermined amount of time into a shorter time, and changes the selected one group cyclically, every time the synch signal is transmitted from the transmitter (24),

the one group of slave devices transmit the respective response signals after their respective divisional waiting times have passed since reception of the synch signal,

the divisional waiting times vary their length from one slave device to another in the one group of slave devices,

the reception controller (273) makes the receiver (23) receive the response signals from the plurality of slave devices (10, B1-B16) in the one group during their respective divisional reception periods after the respective divisional waiting times have passed since transmission of the synch signal by the transmitter (24), and

the predetermined amount of time is long enough to allow the response signals to fall within the respective divisional reception periods.
The automatic fire alarm system master device (20, 20c, 20d) of any one of claims 1 to 4, wherein
a plurality of communications channels, each of which is comprised of the pair of cables (51, 52), are connected to the transmitter (24) and the receiver (23), and
the transmission controller (274) makes the transmitter (24) transmit the synch signal to at least one of the plurality of communication channels to which the plurality of slave devices (10, B1-B16) are connected.
An automatic fire alarm system (1, 1b, 1c) comprising:
the master device (20, 20b, 20c) of any one of claims 1 to 5; and

a plurality of slave devices (10, B1-B16) connected to the pair of cables (51, 52) and configured to transmit their respective response signals (SN1-SN16) by varying the voltage between the pair of cables (51, 52) after their respective waiting times (W1-W16) have passed since the reception of the synch signal.