EP3298503A1

EP3298503A1 - Method and apparatus for providing a test response

Info

Publication number: EP3298503A1
Application number: EP16707440.0A
Authority: EP
Inventors: Wilhelm Petkof
Original assignee: Robert Bosch GmbH
Current assignee: Robert Bosch GmbH
Priority date: 2015-05-18
Filing date: 2016-03-02
Publication date: 2018-03-28
Also published as: US20180143889A1; JP2018519576A; CN107851079A; JP6550149B2; KR20180008629A; WO2016184583A1; DE102015209033A1

Abstract

The invention relates to a method (200) for providing a test response (102) for testing a function of a master unit (112) of a synchronous serial data bus (110), wherein the method (200) has a monitoring step (202) and a providing step (204). In the monitoring step (202), a command bit sequence (120) in a command channel (108) of the data bus (110) is monitored in order to detect a predetermined command (118) from the master unit (112). In the providing step (204), the test response (102) is provided in a response channel (116) of the data bus (110) in response to a detected predetermined command (118), wherein a response bit sequence (128) of the test response (102) is provided using a response rule (126) predefined in a short-term memory (124).

Description

Description title

Method and apparatus for providing a test response prior art

The invention is based on a device or a method

Type of independent claims. The subject of the present invention is also a computer program.

In a data bus, a master unit of the data bus can be checked by at least one slave unit driven by the master unit providing a data value defined in the master unit as a threshold value. For example, the slave unit can be provided with a defined measured variable by an external testing apparatus.

Disclosure of the invention

Against this background, with the approach presented here, a method for providing a test response for testing a function of a master unit of a synchronous serial data bus, furthermore a device, this method is used and finally presented a corresponding computer program according to the main claims. By in the dependent

Claims listed measures advantageous refinements and improvements of the independent claim device are possible.

If a measure is mapped by a slave unit into a data value, mapping errors can corrupt the data value. If the data value of the slave unit is manipulated as a digital value, a to be checked Threshold in the master unit are tested to the nearest bit, as in a direct manipulation of the data value aberrations in the slave unit play no role.

By the approach presented here, a function of a master unit can be checked in a data bus quickly, accurately and cost-effectively, which can be dispensed with a costly testing apparatus.

A method of providing a test response for testing a function of a master unit of a synchronous serial data bus is presented, the method comprising the steps of:

Monitoring a command bit sequence on a command channel of the data bus to detect a predetermined command from the master unit; and

Providing the test response on a response channel of the data bus in response to a detected predetermined instruction, wherein a

Answer bit sequence of the test response using a in a

Short term memory predefined response rule is provided.

A master unit can be understood to mean a computing unit that is designed to be able to handle other arithmetic units (such as a computer)

Slave unit) or to run a running algorithm in these arithmetic units or to supply data. A function of a master unit can be understood as a software-controlled reaction to an information received by the master unit. A test response may be a predefined information for the master unit. A command bit string may be a bit string representing a sequence of different commands on the command channel. A predetermined command may be a segment of the command bit sequence. A response bit string may be a bit sequence that represents the verification response on the response channel. A response rule may be an action to generate the response bit string. This method can be implemented, for example, in software or hardware or in a mixed form of software and hardware, for example in a control unit. The method may include a step of writing in which another

Response rule is written to the temporary memory after the command is recognized. The further response instructions can be written using a test specification. By directly reloading a new response rule, one can immediately respond to a next recognition of the predetermined command.

The check response may also be made using one of the command

resulting response can be provided on the response channel. The response is read in and may be changed using the response rule in at least one bit of the response to obtain the test response. By changing a real response bit by bit, it is possible to specify exactly which position of the response bit sequence is changed to the test response. Thus, the test response around the defined altered location may have a naturally occurring variance.

In the monitoring step, at least one address channel of the

Data bus to be monitored. In this case, the command can be detected if a predetermined, connected to the data bus, the master unit hierarchically subordinate, slave unit is addressed on the address channel. By monitoring the address channel, a master unit of a comprehensive data bus can be checked. By monitoring the address channel can be prevented that a response of an unwanted slave unit is changed. The command bit sequence may be monitored using a predetermined command pattern to recognize the command. A command pattern may include multiple bits. The command pattern may be characteristic of the command. Through the command pattern, the command can be safely detected. In the monitoring step, at least a predetermined subset of the command bitstream can be monitored to detect the command. In particular, a first subarea and at least a second subarea of the

Command bit sequences are monitored to detect the command. Between the first partial area and the second partial area, there may be a gap with a width of at least one bit. The instruction may be characterized by a bit string located at an arbitrary location of the instruction bitstream. Due to a defined monitoring range irrelevant bits can be ignored.

The test response may be further provided in response to an enable signal. The enable signal may represent a satisfied external condition. This allows the master unit to be checked if the external condition is met.

The method may include a predefining step in which the response rule is predefined in the short term memory in response to a start signal. In particular, the predefining step may be performed prior to the providing step. By predefining directly the first command on the command channel can be recognized and a

Test response be provided. Predefining allows testing to be done quickly.

There is further provided an apparatus for providing a test response for testing a function of a master unit of a synchronous serial data bus, the apparatus comprising: a monitor adapted to monitor a command bit sequence on a command channel of the data bus for a predetermined command to recognize from the master unit; and an output device configured to be responsive to a detected predetermined command using one in a

Short-term memory predefined response instruction a response bit sequence of a Provide test response on a response channel of the data bus, wherein the output device is looped into the response channel.

Also by this embodiment of the invention in the form of a device, the object underlying the invention can be solved quickly and efficiently.

In the present case, a device can be understood as meaning an electrical device which processes sensor signals and outputs control and / or data signals in dependence thereon. The device may have an interface, which may be formed in hardware and / or software. In the case of a hardware-based embodiment, the interfaces can be part of a so-called system ASIC, for example, which contains a wide variety of functions of the device. However, it is also possible that the interfaces are their own integrated circuits or at least partially consist of discrete components. In a software training, the interfaces may be software modules that are present, for example, on a microcontroller in addition to other software modules.

Also of advantage is a computer program product or computer program with program code which can be stored on a machine-readable carrier or storage medium such as a semiconductor memory, a hard disk memory or an optical memory and for carrying out, implementing and / or controlling the steps of the method according to one of the above

described embodiments, in particular when the program product or program is executed on a computer or a device.

Embodiments of the invention are illustrated in the drawings and explained in more detail in the following description. It shows:

1 is a block diagram of an apparatus for providing a test response according to an embodiment; FIG. 2 is a flowchart of a method for providing a test response according to an embodiment; FIG.

3 is an illustration of a synchronous serial data bus having a device for providing a test response in accordance with an embodiment; and

4 is an illustration of an apparatus for providing a test response in accordance with one embodiment. In the following description of favorable embodiments of the present invention are for the in the various figures

represented and similar elements acting the same or similar

Reference numeral used, wherein a repeated description of these elements is omitted.

Fig. 1 shows a block diagram of a device 100 for delivering a

Test Response 102 according to one embodiment. The device 100 has a monitoring device 104 and an output device 106. The monitoring device 104 is connected to a command channel 108 of a synchronous serial data bus 110. The data bus 110 connects a

Master unit 112 and at least one of the master unit 112 hierarchically subordinate slave unit 114 with each other. The data bus 110 has at least one response channel 116 in addition to the command channel 108. On the

Command channel 108 sends master unit 112 commands 118 to slave unit 114. Via response channel 116, slave unit 114 responds to the commands

118. The monitor 104 is configured to monitor a command bit train 120 of the instructions 118 on the command channel 108 to detect a predetermined command 118 from the master unit 112. At the

Upon detection of command bit train 120 corresponding to command 118, trigger information 122 is provided.

The output device 106 is looped into the response channel 116 and configured to provide the test response 102 on the response channel 116 of the data bus 110 in response to the trigger information 122. The test response 102 is predefined using a temporary memory 124 Response rule 126 provided. The response instruction 126 is read out bit by bit from the temporary memory 124. The test response 102 has a

Answer bit string 128 on. In particular, corresponds to a length of

Response specification 126 of a length of the response bit string 128. The verification response 102 is configured to check a function of the master unit 112.

A response of the master unit 112 may be detected by monitoring the channels 108, 116 of the data bus 110. For example, the

Slave unit 114 may be a sensor. Then, the test response 102 may simulate a value measured by the sensor, although the sensor currently does not measure that value. For example, the simulated value may be less than one

Threshold for triggering another command on the command channel 108. If the master unit 112 functions as intended, the other command is not output. In the event of a malfunction of the master unit 112, for example, the other command may be issued despite the too low simulated value or a wrong command. Similarly, the simulated value may be greater than the threshold. Then the master unit 112 asserts

intended function of the other command. For example, if the master unit 112 malfunctions, no command can be issued.

In one embodiment, the test response 102 is provided to the instruction 118 using a response 130 of the slave unit 114.

For example, response policy 126 then defines at which locations a bit string of response 130 should be changed to obtain the response bit string 128.

The master unit 112 may poll the same command 118 periodically

Send data bus 110 to the slave unit 114. Then, the bit string of the response 130 may be changed similarly using the response law 126 each time.

If the test response 102 is to be changed, another

Response rule 132 is needed. In one embodiment, the device 100 includes a unit 134 for writing to the short term memory 124. The writing unit 134 is adapted to the further answering rule 132 in the temporary memory 124 to write. The writing may be done in response to the trigger information 122. The write unit 134 generates the further response rule 132 using a test specification 135. The test specification 136 is specially adapted to the instruction 118 to be checked. The test specification 136 is in one

Configuration memory 138 of the device 100 deposited.

The writing can be done bit by bit. In this case, the first bit of the further response instruction 132 can be written into the short-term memory 124, while the first bit of the response instruction 126 is read from the short-term memory 124. In particular, the short-term memory 124 may be a register that can be written on an input side and written on an input side

Output side is readable.

FIG. 2 shows a flowchart of a method 200 for providing a test response according to an embodiment. The method 200 may

for example, on a device as shown in Fig. 1 are executed. The method 200 includes a step 202 of monitoring and a step 204 of providing. The check response is designed to check a function of a master unit of a synchronous serial data bus. To this end, in step 202 of monitoring, a command bit sequence is monitored on a command channel of the data bus to detect a predetermined command from the master unit. In response to the detection, in step 204 of the provisioning, the check response is provided on a response channel of the data bus. A response bit string of the check response is provided using a predefined response rule in a short term memory.

In one embodiment, the method 200 includes a step 206 of writing in which another response policy is written to the short term memory after the command is recognized. The others

Response instructions are written using a test specification.

FIG. 3 shows a representation of a synchronous serial data bus 110 with a device 100 for providing a test response in accordance with FIG Embodiment. The device 100 essentially corresponds to one

Device as shown in Fig. 1. Here is only the

Output device 106 shown. In addition, the device 100 is connected to at least one further synchronous serial data bus 110 analogously to the data bus 110 in order to also provide the check response in the further data bus 110 for testing the further master unit 112. In particular, up to four data buses 110 can be connected to the device 100.

In addition to the data bus in FIG. 1, at least one further slave unit 114 is connected to the data bus 110 here. In order to be able to address the slave units 114 individually, the data bus 110 therefore has an address channel 300. Thus, the command may be assigned to a particular slave unit 114, even if the command bit sequence is identical. The address channel 300 is also monitored by the device 100 to provide the check response when a response is issued by the particular slave unit 114.

Furthermore, the data bus 110 has a clock channel 302 via which the

Communication of all participants 112, 114 is synchronized or clocked on the data bus 110. The device 100 is also with the

Clock channel 302 connected to provide the test response synchronized or timed.

To check the command, the device 100 is connected to a

Configuration information 304 configured. The configuration information 304 is stored in the configuration memory. This represents the

Configuration information 304 a characteristic bit pattern or command pattern of the command under test. Furthermore represents the

Configuration information 304 is a bitmask to define which bits of the command bitstream to check. In one exemplary embodiment, the command is partially mapped in the bit pattern or the bit mask in order to be able to check several similar commands. The bitmask may also have multiple ones distributed over a data word of the command bitstream

Define check window, with the bits in the check windows be checked to recognize the command. In other words, the bit mask defines at least one portion of the command bit sequence to be checked.

In one embodiment, configuration information 304 includes a bus number to determine which data bus (s) 110 to check. Furthermore, the configuration information 304 may include an address of the slave unit 114 whose response on the response channel 116 is to be changed. Furthermore, the configuration information 304 includes manipulation data and a manipulation mode. The manipulation data represent part of the response rule for providing the test response or for providing a sequence of test replies to be provided one after the other. One or more complete ones can be used in the manipulation data

Test responses be deposited. Also, individual bits to be changed can be

Response of the slave unit 114 may be stored in the manipulation data. The manipulation mode also represents part of the response to providing the test response. The manipulation mode characterizes the necessary framework conditions for providing the test response.

In other words, FIG. 3 shows a device 100 for software tests based on SPI manipulations in real time. In this case, the data bus 110 is an SPI bus 110. The device 100 can also be referred to as an SPI manipulator 100. In SPI bus 110, the Matereinheit 112 is referred to as master 112, while the slave units 114 are referred to as slaves 114. At a device 100, up to four separate SPI buses 110 may be connected simultaneously. The SPI bus 110 has as the clock channel 302 an SCLK or

System clock on. As a command channel, the SPI bus 110 has a MOSI or master out slave in. As response channel 116, the SPI bus 110 has an M ISO channel (which is also known as master-in-slave-out).

Data transmission channel can be called) on. The address channel 300 in the SPI bus 110 is formed by an SS channel (which may also be referred to as a slave select channel) per slave. In the illustrated

Thus, the SPI bus has an SSI channel for the first slave 114 and an SS2 channel for the second slave 114. The SPI Manipulator 100 is looped into the MISO channels. Thus, there is no direct connection of the MISO (channel) outputs of the slaves 114 to the MISO (channel) input of the master 112. Via MOSI channel, for example, 120 different commands from the

Master 112 are transmitted to the slaves 114. Slaves 114 continuously monitor the MOSI channel, but only respond when addressed via their associated SS channel 300. When a slave 114 is addressed by a command on the MOSI channel, a response to the command is provided directly through the M ISO channel. The SPI manipulator 100 modifies or falsifies this response to accommodate a response of the master 112 to it

To be able to analyze the wrong answer or the test answer. In this case, for example, values that are stored in the master 112 as threshold values for an action can be mapped in the test response.

As configuration information 304, the SPI bus 110 stores the SPI number, the slave select line, the SPI trigger bits, the SPI trigger mask and the conditional control register (32 bits per fault unit). It is about the

SPI number defines which of the connected buses is checked. The slave select line defines which slave 114 should be checked. The bit pattern of the command to be checked is stored in the SPI trigger bits. In the SPI trigger mask, the number of bits necessary to recognize the command and the location within the bit string of the command is defined. The position can also be defined at several locations within the bit sequence.

Furthermore, the manipulation data and the manipulation mode are stored in the configuration information 304.

The SPI manipulator 100 is for manipulating data bits on the SPI MISO channel in real time. This makes it possible to test bit-accurate software systems in which the communication between the microcontroller μθ (SPI master) 112 and the ASICs (SPI slaves) 114 takes place via the SPI bus line. Through the approach presented here, a change in the Peripheral settings of the control unit can be avoided. About the

Settings on the periphery, bit-accurate testing is not possible in most cases.

By the same principle, the SPI-MOSI line can also be manipulated, or both lines, if the unit 124 is duplicated.

The SPI manipulator 100 is for manipulating data bits on the SPI MISO channel in real time.

4 shows an illustration of an apparatus 100 for providing a test response 102 according to one embodiment. The device 100 essentially corresponds to a device as shown in FIG. Only the monitoring device 104 and the output device 106 as well as the short-term memory 124 are shown here. The illustrated device 100 is

in particular part of the device in Fig. 3. The

Monitoring device 104 here has various modules. One

Trigger module 400 monitors the bit sequence on the command channel 108.

For example, the instructions are 32 bits long. To recognize the command, the first ten bits of the bit string are monitored. The remaining bits contain additional information, for example. Furthermore, the trigger module monitors the address channel 300 and the clock channel 302. If the slave unit specified in the configuration information is addressed on the address channel 300 and the command sequence representing the command information set in the configuration information is received, a trigger signal 402 is provided. The trigger signal 402 is provided to a manipulator control module 404 and a memory control module 406.

In the manipulator control module 404, the trigger information 122 for the temporary memory 124 is output when the trigger signal 402 is received and an additional condition 408 is met. For example, one and the same command in different contexts may be used on the data bus. The additional condition 408 may provide the test response 102 if the correct context exists and is retained when the wrong context exists. The additional condition 408 may be referred to as an enable signal 408.

Buffer memories 410, 412, 414 are activated via the memory control module 406. The buffer memories 410, 412, 414 in this case correspond to the unit 134 for writing to the short-term memory 124 in FIG. 1. The buffer memories 410, 412, 414 are operated here as FI FO memories, one first into one of the buffer memories 410, 412, 414 read-in information is again read out first. The buffers 410, 412, 414 are over

Readout signal 416 driven by the memory control module 406. The readout signal 416 is provided by the memory control module 406 when a global start signal 418 or an external start signal 420 has been read in and the trigger signal 402 is received.

The manipulation mode is stored in the first buffer memory 410. When the first buffer memory 410 is read in response to the readout signal 416, a time trigger 422 and / or the memory control module 406 are actuated.

In the second buffer memory 412 and third buffer memory 414, the response instruction 132 to be reloaded into the short-term memory 124 is pre-stored. In response to the readout signal 416, the contents of the second buffer memory 412 and the third buffer memory 414 are written into the

Short-term memory 124 shifted. Because the readout signal 416 like the

Trigger information 122 is dependent on the trigger signal 402, the buffer memory 124 is already emptied when the buffer memory 412, 414 are read out. In this case, a control information 424 of the next response rule 132 is stored in the second buffer memory 412. In the third buffer memory 414, data information 426 of the next response rule 132 is stored. The control information 424 in this case represents a bit sequence of control bits 428 for driving the output device 106. The data information 426 represents a bit sequence of data bits 430 for driving the output device 106. The temporary memory 124 is here a 32-bit shift register. For the

Control information 424, the temporary memory 124 has a 32-bit control shift register. For the data information 426, the short-term memory has a 32-bit data shift register.

In this case, the output device 106 is a four-bit to one-bit multiplexer 106. The multiplexer 106 is activated for each bit output as test response 102 by a respective control bit 428 and a data bit 430. At the four inputs of the multiplexer 106 are the response channel 116 with the response 130 from the addressed slave unit, the inverted response channel 432 with the inverted

Response from the addressed slave unit, logical zero and logical one on.

If the control bit 428 and the data bit 430 are zero, the corresponding bit of the response 130 is output as the test response 102. If the control bit 428 is zero and the data bit 430 is one, then the corresponding bit of the inverted response is output as test response 102. If the control bit 428 is one and the data bit 430 is zero, logic zero is output as test response 102. When the control bit 428 and the data bit 430 are one, the check response 102 is output logical one.

The basic idea of the SPI manipulator 100 is based on a 4-bit-to-1-bit multiplexer 106, which is driven by the most significant bit MSB of two shift registers 124. The shift registers 124 are preloaded with the values from the FI FOs Control and Data 412, 414 when the SPI pattern is recognized and shifted or shifted by one bit with each SPI cycle.

The manipulation of the MISO line 116 or channel begins with the next bit after the recognition of the SPI pattern. With each new SPI command, the two shift registers 124 are cleared. As a result, the MISO bits remain unmanipulated when the SPI pattern is not recognized.

An SPI manipulation module 100 detects an SPI instruction to be disturbed and controls the synchronous reading of the three FIFOs 410, 412, 414 depending on one of the four selected modes. If several SPI commands are to be manipulated at the same time, a corresponding number of SPI manipulation modules can be used. For example, the control FIFO 412 and the data FI FO 414 have a width of 32 bits and a depth of 512 entries. The control FI FO 412 and the data FIFO 414 contain the manipulation data for driving the 4-bit-to-1-bit multiplexer 106.

For example, the mode FI FO 410 has a width of 32 bits and a depth of 512 entries. Bits 31 to 28 contain the modes which determine under which conditions the next reading of the three FI FOs 410, 412, 414 occurs. Bit 27 to bit 0 contain the preload value for the timer. These bits are only relevant for the timer mode.

In the SPI trigger mode, after each detected SPI pattern, the three FI FOs 410, 412, 414 are read. In the time trigger mode, the FI FOs 410, 412, 414 are read when the 28-bit timer has expired. At the same time a new timer value is loaded. This achieves an adjustable manipulation time. In global trigger mode, the FI FOs are read simultaneously by all SPI manipulation modules based on a defined event. In external trigger mode, the trigger for reading the FI FOs 410, 412, 414 interactively from a PC, after previously, also from the PC, an entry in the FIFOs

410, 412, 414 took place. This can be done via a "virtual periphery"

Changes to the periphery can be simulated without losing the real

Change peripheral settings. The FI FO control module 406 decides when to read the three FIFOs 410, 412, 414 again, depending on the active trigger mode and trigger. With each reading of the mode FIFO 410, the mode can also be switched.

The SPI trigger module 400 is for detecting an arbitrary pattern on the SPI. This is done with the help of two 32 bit registers. The Mask Register contains a "1" for the relevant bits, and the Pattern Register contains the bits to test against MOSI line 108. Both registers are shifted left in SPI clock 302 and padded with "0". As soon as all bits in the mask register have the value zero, the pattern is considered recognized and a trigger 402 is sent to the modules FI FO control 406 and manipulator control 404. The time-trigger module 422 transmits a trigger to the FI FO control module after the expiration of a μδ-ηηεεεε. 406 This causes the FIFOs 410, 412, 414 to be read again, thus precharging a new timer value.

The manipulator control module 404 determines when the disturbance patterns 132 applied to the outputs of the FI FOs 412, 414 are copied to the two shift registers 124. However, copying occurs only when conditional control 408 is logic "1." The conditional control condition can be used when the detection of an SPI pattern on MOSI line 108 is ambiguous or another condition must be met in the system. For this, an additional module is to be created, which generates the condition to which one or more perturbations can react, if they are configured accordingly.

If an exemplary embodiment comprises an "and / or" link between a first feature and a second feature, then this is to be read so that the embodiment according to one embodiment, both the first feature and the second feature and according to another embodiment either only first feature or only the second feature.

Claims

claims

A method (200) for providing a test response (102) for testing a function of a master unit (112) of a synchronous serial

Data bus (110), the method (200) comprising the steps of:

Monitoring (202) a command bit stream (120) on a command channel (108) of the data bus (110) to detect a predetermined command (118) from the master unit (112); and

Providing (204) the test response (102) on a response channel (116) of the data bus (110) in response to a detected one

predetermined command (118), wherein a response bit string (128) of the check response (102) is provided using a predefined response rule (126) in a temporary memory (124).

The method (200) of claim 1, further comprising a step (206) of

Write another response (132) in the

Short term memory (124) after the command (118) is detected, the further response rule (132) using a

Test Specification (136) is written.

The method (200) of any one of the preceding claims, wherein in the step (204) of providing, the test response (102) is further provided on the response channel (116) using a response (130) resulting from the instruction (118), wherein the Response (130) is read in and using the response rule (126) at least one bit of the response (130) is changed to obtain the test response (102). 4. The method of claim 1, further comprising at least one of monitoring in step (202) Address channel (300) of the data bus (110) is monitored, the command (118) is detected when on the address channel (300), a predetermined, with the data bus (110) connected to the master unit (112) hierarchically subordinate, slave unit (114 ) is addressed.

The method (200) of any one of the preceding claims, wherein in the step (202) of monitoring, the command bit stream (120) is monitored using a predetermined command pattern to recognize the command (118).

Method (200) according to one of the preceding claims, in which in the step (202) of monitoring at least a predefined subarea of the command bit sequence (120) is monitored in order to recognize the command (118), in particular wherein in step (202) of

Monitor a first subarea and at least a second

Part of the command bit sequence (120) are monitored to detect the command (118).

The method (200) of any one of the preceding claims, wherein in the step (204) of providing, the test response (102) is further provided in response to an enable signal (408).

The method (200) according to one of the preceding claims, comprising a predefining step in response to a

Start signal (418) the response rule (126) in the temporary memory (124) is predefined, in particular wherein the step of

Predefining is performed before the step (204) of providing.

Apparatus (100) for providing a test response (102) for testing a function of a synchronous serial master unit (112)

Data bus (110), the device (100) having the following features: a monitor (104) adapted to monitor a command bit stream (120) on a command channel (108) of the data bus (110) to detect a predetermined command (118) from the master unit (112); and output means (106) arranged to responsive to a detected predetermined command (118) using a response prescription (126) predefined in a temporary memory (124), a response bit string (128) of the check response (102) on a response channel (116 ) of the data bus (110), wherein the output device (106) is looped into the response channel (116).

A computer program adapted to carry out the method according to any one of the preceding claims.

11. A machine-readable storage medium on which the computer program according to claim 9 is stored.