DE102018201710A1 - Method and device for checking a function of a neural network - Google Patents

Abstract

The invention relates to an apparatus for testing a test area of a neural network (1) with a plurality of hardware-formed neurons (3), comprising: - a test control unit (13) for performing a test of a test area selected from the plurality of neurons (3) in a test mode - multiplexers (11) connected to input side neurons of the test area and controllable by the test control unit (13) to apply input test data (TE) to input side neurons of the test area depending on the existence of the test operation; demultiplexer (12), which are connected to output side neurons (3) of the test area and which are controllable by the test control unit (13) to provide output test data (TA) to the test control unit (3) depending on the existence of the test operation; wherein the test control unit (13) is adapted to compare the output test data (TA) with test maintenance data associated with the test input data (TE) and to detect an error in the event of a deviation.

Description

Technical area

The invention relates to neural networks, in particular deep neural networks, having a high number of layers with a high number of neuron functions. The invention further relates to measures for checking neuron functions of hardware implemented neurons of a deep neural network.

Technical background

The realization of neural networks, in particular deep neural networks, in hardware leads to complex interconnections, in particular due to the cascading of neuron layers, each with a high number of neurons. A review and monitoring of the operation of such hardware is possible due to the complexity of the circuit only with great effort and / or low reliability, which does not meet the requirements, especially the legal requirements, especially in safety-critical systems. Also, such a review requires a longer amount of time that is not available to an application during a review.

The publication CN 101110155 A discloses a built-in intelligent fault diagnosis unit based on pattern recognition.

The publication EP 1 806 636 B1 describes a hardware-in-the-loop (HiL) system for testing ECUs of a vehicle control system with a real-time simulation device operable via at least one central computer to perform a system simulation associated with multiple test modules for connection to each associated ECU of the control system. The simulation device is distributed on a central unit connected to the central unit and a plurality of module units of the respective assigned test modules, wherein the part of the simulation unit accommodated in the central unit simulates a control unit-spanning sequences of interaction of the control units, whereas the part of the simulation units accommodated in the module units ECU-specific processes for the connected control units simulates. In the event of a performance bottleneck, parts of the control unit-specific sequences of the simulation can also be moved from the module units to the central unit.

Disclosure of the invention

According to the invention, a device with a plurality of hardware-formed neurons coupled together to form a neural network according to claim 1 and a method for testing such a device with a hardware-formed neural network according to the independent claim are provided.

Further embodiments are specified in the dependent claims.

• - eine Teststeuereinheit zum Durchführen eines Tests eines aus den mehreren Neuronen ausgewählten Testbereichs;
• - Multiplexer, die mit eingangsseitigen Neuronen des Testbereichs verbunden sind und die durch die Teststeuereinheit ansteuerbar sind, um abhängig von dem Vorliegen eines Testbetriebs Eingangstestdaten an die eingangsseitigen Neuronen weiterzureichen;
• - Demultiplexer, die mit ausgangsseitigen Neuronen des Testbereichs verbunden sind und die durch die Teststeuereinheit ansteuerbar sind, um abhängig von dem Vorliegen des Testbetriebs Ausgangstestdaten an die Teststeuereinheit anzulegen;

wobei die Teststeuereinheit ausgebildet ist, um die Ausgangstestdaten mit Testerwartungsdaten, die den Eingangstestdaten zugeordnet sind, zu vergleichen und um bei einer Abweichung einen Fehler festzustellen.According to a first aspect, there is provided an apparatus for testing a test area of a neural network having a plurality of hardware-formed neurons, comprising:

• a test control unit for performing a test on a test area selected from the plurality of neurons;
• Multiplexers connected to input-side neurons of the test area and controllable by the test control unit to pass input test data to the input-side neurons in response to the presence of a test operation;
• Demultiplexers connected to output side neurons of the test area and controllable by the test control unit to apply output test data to the test control unit depending on the existence of the test operation;

wherein the test control unit is configured to compare the output test data with test maintenance data associated with the input test data and to detect an error in the event of a deviation.

Previous methods for verifying a function of a hardware-implemented neural network use test patterns to check all hardware for proper operation. This blocks all computational hardware for further computation for the duration of a complete computation pass. The above device makes it possible to test test areas as parts of the neural network computing hardware and thus to specify the duration of the test runout failure by choosing the size of the test area.

Furthermore, the multiplexers can be connected to an input of the neural network or to neuron outputs of at least one further neuron, in order to apply either input data of the neural network or calculation results of further neurons of the neural network or the input test data to the input-side neurons, depending on the existence of the test operation.

The demultiplexers can furthermore be connected to neuron inputs of further neurons of the neural network or to an output of the neural network, depending on the existence of the test operation, either calculation results at the output of the neural network or at other neurons of the neural network or as output test data to the Create test control unit.

It can be provided that the test area is selected such that it is self-contained between the input-side neurons of the test area and the output-side neurons of the test area, wherein in particular the remaining neurons outside the test area have no connections to neuron inputs of neurons within the test area and each of the neurons in the test area is connected to its neuron outputs with neuron inputs of one or more further neurons of the test area or demultiplexers.

According to one embodiment, the control unit may be configured to stop the calculation in the neural network and to store intermediate results and calculation results before the test operation, and in particular to continue the calculation based on the stored intermediate results and calculation results after the test operation.

By buffering the incoming data on the input side of the test area, it is possible to stop the current calculation of the neural network, so that testing of the test area can be performed and subsequently the buffered data can be used to continue the calculation in the neural network. Thus, no invoice results are lost.

It can be provided that the test control unit is designed to change neuron parameters of neurons in the test area before the test operation.

In particular, the test control unit may be configured to change neuron parameters for the test operation to define calculation paths within the test area such that upon detection of an error from the calculation path, it is identified as an error in neurons of the calculation path.

For this purpose, the test control unit may be configured to change the calculation paths for a plurality of test runs of the test operation such that in the multiple test passes each of the neurons performs at least one calculation.

The test control unit may alternatively or additionally be configured to change the calculation paths for a plurality of test runs of the test operation such that, when an error is detected in two of the calculation paths, the error is assigned to one of the neurons jointly contained in both calculation paths.

According to another aspect, there is provided a neural network comprising a plurality of hardware-trained, coupled-together neurons, wherein a part of the neurons form a test area, and the above device.

• - Einstellen eines Testbetriebs;
• - Anlegen von Eingangstestdaten an eingangsseitige Neuronen des Testbereichs mithilfe der Multiplexer;
• - Auslesen von Ausgangstestdaten mithilfe der Demultiplexer;
• - Feststellen eines Fehlers abhängig von einem Vergleich der Ausgangstestdaten mit vorgegebenen Testerwartungsdaten.

According to a further aspect, a method for testing the above device is provided, comprising the following steps:

• - Setting a test operation;
• - applying input test data to input side neurons of the test area using the multiplexers;
• - reading out output test data using the demultiplexer;
• - Determining an error depending on a comparison of the output test data with given tester maintenance data.

list of figures

• 1 den Aufbau eines herkömmlichen neuronalen Netzes;
• 2 eine schematische Darstellung einer Berechnungshardware eines neuronalen Netzes mit mehreren Schichten und mit einer Testschaltung zum Testen eines Testbereichs als ein Teil der Berechnungsschaltung des neuronalen Netzes; und
• 3 eine schematische Darstellung eines Verfahrens zum Betreiben der Berechnungsschaltung zum Testen eines Testbereichs.
• 4a und 4b Berechnungspfade durch einen Testbereich bei einem Testbereich mit Neuronenschichten mit identischer Anzahl von Neuronen;
• 5a und 5b Berechnungspfade durch einen Testbereich bei einem Testbereich mit Neuronenschichten mit unterschiedlicher Anzahl von Neuronen.

Embodiments are explained below with reference to the accompanying drawings. Show it:

• 1 the construction of a conventional neural network;
• 2 a schematic representation of a computational hardware of a neural network with multiple layers and with a test circuit for testing a test area as part of the calculation circuit of the neural network; and
• 3 a schematic representation of a method for operating the calculation circuit for testing a test area.
• 4a and 4b Calculation paths through a test area in a test area with neuron layers with identical numbers of neurons;
• 5a and 5b Computational paths through a test area in a test area with neuron layers with different numbers of neurons.

Description of embodiments

1 basically shows the structure of a neural network 1 , which usually consists of several cascaded neuron layers 2 of several neurons each 3 having. The neuron layers have an input layer 2E for creating input data, several intermediate layers 2Z and an initial layer 2A to output calculation results.

entsprechen, wobei O_j dem Neuronenausgang des Neurons, φ der Aktivierungsfunktion, x_i dem jeweiligen Eingangswert des Neurons, w_i,j einem Gewichtungsparameter für den i-ten Neuroneneingang in der j-ten Neuronenschicht und θ_j einer Aktivierungsschwelle entsprechen. Die Gewichtungsparameter, die Aktivierungsschwelle und die Wahl der Aktivierungsfunktion können als Neuronenparameter in Registern des Neurons gespeichert sein.The neurons 3 the neuronal layers 2 can use a conventional neuron function $$O_j=\phi \left({\displaystyle \underset{i=1}{\overset{M}{\Sigma }}\left(x_i{w}_{i.j}\right)-{\theta }_j}\right)$$

match, where O _j the neuron output of the neuron, φ the activation function, x _i the respective input value of the neuron, w _{i, j} a weighting parameter for the i-th neuron input in the j-th neuron layer and θ _j corresponding to an activation threshold. The weighting parameters, the activation threshold and the selection of the activation function can be stored as neuron parameters in registers of the neuron.

The neuron outputs of a neuron 3 can each be called neuron inputs to neurons 3 the remaining neuron layers, ie one of the following or one of the preceding neuron layers 2 , passed on or, if it is a neuron 3 the starting layer 2A acts as a calculation result.

So formed neural networks 1 may be implemented in the form of computing hardware that maps some or all of the neural network as an electronic (integrated) circuit. Such a calculation hardware is usually then chosen to build a neural network, if the calculation should be very fast, which would not be achieved with implementation in software.

To test the functionality of the computational hardware, a test functionality is provided that allows in a test mode to select individual test areas of the computational hardware. The function of these test areas comprising a plurality of neurons in one or more neuron layers or parts of one or more neuron layers can be achieved by applying input test data TE to the input side neurons of the test area and checking for the input test data TE resulting output test data TA be tested with a given test service value.

The test areas within the computing hardware are chosen to be self-contained between the input side neurons of the test area and the output side neurons of the test area, ie the remaining neurons outside the test area have no connections to neuron inputs of neurons within the test area and each of the Neurons in the test area with its neuron output with at least one input of another neuron 3 the test area is connected.

As in a detailed illustration of a test area of a neural network in the 2 shown, the test area is the input side by multiplexer 11 and on the output side by demultiplexer 12 certainly. The multiplexers 11 and the demultiplexers 12 be through a test control unit 13 controlled by a test signal TM. The multiplexers 11 and / or the demultiplexer represent in a simple embodiment switch.

The demultiplexer 11 allow, depending on the presence of the test operation, to select that to the inputs of the input side neurons 3 the test area either input data of the calculation hardware or intermediate results from calculations of previous neuron layers or the input test data TE the input-side neurons of the test area are created. The multiplexers 11 are doing through the test control unit 13 using a test signal TM controlled, indicating whether the test mode is present or whether the test area should be tested.

Accordingly, the outputs of the output side neurons of the test area are via the demultiplexers 12 with inputs from neurons 3 a subsequent neuron layer or the output of the calculation unit, so as to forward either regular calculation results to the next neuron layer or the output of the calculation unit or the output test data TA to the test control unit 13 to forward them there with test maintenance data for the injected input test data TE can be compared to detect an error in deviations and to signal this in a suitable manner.

The entrance test data TE and test servicing data is determined after training the new neural network using exemplary input test data TE which are assumed to be duly accepted test result data as reference data.

If the test area is tested, it may be provided that the test control unit 13 continue the calculation in the remaining neural Network stops, so that after completing the testing of the test area, the calculation can continue where it was stopped before the start of testing.

According to a further embodiment it can be provided that, for testing the neurons in the test area, the neuron parameters stored therein are buffered during testing and instead neuron test parameters are written. By appropriate choice of the neuron test parameters, it can be ensured that the functionality of each of the neurons within the test area can be properly checked. After completion of the test, the cached neuron parameters can then be written back into the neurons of the test area.

In 3 FIG. 10 is a flow chart illustrating the test control unit. FIG 13 procedure for testing a selected test area within the neural network computing hardware.

In step S1 First, the test area is selected and the corresponding demultiplexer 12 and multiplexers 11 which are assigned to the input-side neurons of the test area and the output-side neurons of the test area.

In step S3 holds the test control unit 13 the further calculations of the neural network, so that the currently located in registers, latches and the like calculation results are retained and secured with the configuration parameters of the neurons in the test area.

The correspondingly assigned demultiplexer 12 and multiplexers 11 be using the test signal TM now in step S2 controlled so that the test area on the input side and output side with the test control unit 13 connected is.

In step S4 Now test data is sent to the inputs of the multiplexers 11 selected input-side neurons 3 of the test area.

In step S5 the calculation is started in the neurons of the test area until calculation results are applied to the output-side neurons of the test area.

In a subsequent step S6 the corresponding output test data are determined at the outputs of the output-side neurons of the test area.

In a review in step S7 By comparing the output test data TA with the corresponding reference data associated with the test maintenance data, it is determined whether there is an error within the test area or not. If there is an error (alternative: yes), it will be in step S8 accordingly signaled and the process with step S9 continued. Otherwise (alternative: no) the procedure goes directly to step S9 continued.

In step S9 becomes the test signal TM modified accordingly to leave the test mode, so that the multiplexer 11 and demultiplexer 12 connect the input-side neurons of the test area again with their predecessor neurons and the output-side neurons of the test area again with the following neurons. Subsequently, the configuration parameters of the neurons in the test area, which were stored before the test, are restored.

Subsequently, in step S10 the calculations in the neural network are restarted, so that the previously stopped calculation can be continued.

By being able to change the neuron parameters during testing, neuron paths through the test area can be defined by appropriate choice of weights. This is exemplary in 4a for the case where each of three neuron layers has the same number of neurons. Thus, a defined calculation path (bold line) through the test area can be defined by programming a sequence of neurons, each with a set of weighting parameters, in which one weighting parameter is greater than 0 and the remaining 0. If, after applying an input test data to the input side neuron of the test area at which the calculation path starts, an error is detected by evaluating the corresponding test output data at the output side neuron of the test area with which the calculation path ends, a malfunction in one of the neurons may be detected of the calculation path.

In 4b is defined for an identical configuration of the test area of the neural network by a suitable choice of the weighting parameters for testing another calculation path (bold line). As a result, a faulty neuron can be identified by multiple test runs.

Another possibility for checking the function of a test area of neurons can be made possible by feeding in certain input test data TE. By the Adjusted weighting parameters and information from a neuron only horizontally propagated through the network, a statement about the functioning of the neurons contained in this test chain can be made at the end of the test chain. If TE is applied as input test data for a = 1, b = 2, c = 4, d = 8, then the weighting parameters and the activation functions can be selected such that, if correctly calculated in the neurons and the activation function [eg. ReLU]) the values of the output test data are identical to the values of the values of the input test data TE are. The values of the input test data TE can be chosen so that a quick check on the basis of the bit pattern is possible, since only exactly one bit may be activated at the output.

For neuron layers with different numbers of neurons in the test area, the compounds can be selected by the weighting parameters so that there is always a defined calculation path through the test area. The 5a and 5b show, for an exemplary test area, various calculation paths chosen in this way, which are tested in successive test runs of the test operation.

Filtering neuron layers in computational hardware, such as MaxPooling layers at CNN, should be given special treatment for a test procedure. For this purpose, the calculation result should be calculated and checked up to this point before the filtering neuron layer, and subsequently with new predefined input test data TE be restarted in the filtering neuron layer.

QUOTES INCLUDE IN THE DESCRIPTION

This list of the documents listed by the applicant has been generated automatically and is included solely for the better information of the reader. The list is not part of the German patent or utility model application. The DPMA assumes no liability for any errors or omissions.

Cited patent literature

• CN 101110155 A [0003]
• EP 1806636 B1 [0004]

Claims (13)

Apparatus for testing a test area of a neural network (1) having a plurality of hardware-formed neurons (3), comprising: a test control unit (13) for performing a test on a test area selected from the plurality of neurons (3) in a test mode; - multiplexers (11), which are connected to input-side neurons of the test area and which are controllable by the test control unit (13) in order to apply input test data (TE) to input-side neurons of the test area, depending on the presence of the test operation; - demultiplexers (12) connected to output side neurons (3) of the test area and controllable by the test control unit (13) to provide output test data (TA) to the test control unit (3) depending on the existence of the test operation; wherein the test control unit (13) is adapted to compare the output test data (TA) with test maintenance data associated with the test input data (TE) and to detect an error in the event of a deviation. Device after Claim 1 in which the multiplexer (11) is further connected to an input of the neural network (1) or to neuron outputs of at least one further neuron (3), depending on the existence of the test operation, either input data of the neural network or calculation results of further neurons (3 ) of the neural network or the input test data (TE) to the input side neurons (3). Device after Claim 1 or 2 , wherein the demultiplexers (12) are further connected to neuron inputs of further neurons (3) of the neural network (1) or an output of the neural network, depending on the presence of the test operation either computational results to the output of the neural network or additional neurons (3) of the neural network or as output test data (TA) to the test control unit (13) to create. Device according to one of Claims 1 to 3 , wherein the test area is selected such that it is self-contained between the input-side neurons (3) of the test area and the output-side neurons (3) of the test area, in particular the remaining neurons (3) outside the test area having no connections to neuron inputs of neurons (3) within the test area and each of the neurons (3) in the test area is connected to its neuron outputs with neuron inputs of one or more further neurons (3) of the test area or demultiplexers (12). Device according to one of Claims 1 to 4 wherein the test control unit (13) is arranged to stop the calculation in the neural network (1) and to store intermediate results and calculation results before the test operation, and in particular after the test operation, the calculation based on the stored intermediate results and calculation results continue. Device according to one of Claims 1 to 5 wherein the test control unit (13) is designed to change neuron parameters of neurons (3) in the test area before the test operation. Device after Claim 6 wherein the test control unit (13) is arranged to change neuron parameters for the test operation so that calculation paths are defined within the test area such that upon detection of an error from the calculation path, it is identified as an error in neurons (3) of the calculation path. Device after Claim 7 in that the test control unit (13) is designed to change the calculation paths for a plurality of test passes such that, in a plurality of test runs of the test operation, each of the neurons (3) performs at least one calculation. Device after Claim 7 wherein the test control unit (13) is arranged to change the calculation paths for a plurality of test runs of the test operation so that, when an error is detected in two of the calculation paths, the error is assigned to one of the neurons jointly contained in both calculation paths. A neural network (1) comprising: a plurality of hardware-coupled, coupled neurons (3), a portion of the neurons forming a test area, and a device according to any one of Claims 1 to 9 , Method for testing a neural network (1) with a device according to one of the Claims 1 to 9 , with the following steps: - Setting a test operation; - applying input test data (TE) to input-side neurons of the test area by means of the multiplexers (11); - reading out output test data using the demultiplexer (12); - Determining an error depending on a comparison of the output test data (TA) with given tester maintenance data. Computer program adapted to follow all steps of the procedure Claim 11 perform. Electronic storage medium on which a computer program is based Claim 12 is stored.

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