EP3289445A4 - Floating point computation apparatus and method - Google Patents

Floating point computation apparatus and method Download PDF

Info

Publication number
EP3289445A4
EP3289445A4 EP16802335.6A EP16802335A EP3289445A4 EP 3289445 A4 EP3289445 A4 EP 3289445A4 EP 16802335 A EP16802335 A EP 16802335A EP 3289445 A4 EP3289445 A4 EP 3289445A4
Authority
EP
European Patent Office
Prior art keywords
floating point
computation apparatus
point computation
floating
point
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP16802335.6A
Other languages
German (de)
French (fr)
Other versions
EP3289445A1 (en
EP3289445B1 (en
Inventor
Huong HO
Michel KAFROUNI
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huawei Technologies Co Ltd
Original Assignee
Huawei Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Publication of EP3289445A1 publication Critical patent/EP3289445A1/en
Publication of EP3289445A4 publication Critical patent/EP3289445A4/en
Application granted granted Critical
Publication of EP3289445B1 publication Critical patent/EP3289445B1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/483—Computations with numbers represented by a non-linear combination of denominational numbers, e.g. rational numbers, logarithmic number system or floating-point numbers
    • G06F7/485—Adding; Subtracting
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/50—Adding; Subtracting
    • G06F7/505—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination
    • G06F7/506—Adding; Subtracting in bit-parallel fashion, i.e. having a different digit-handling circuit for each denomination with simultaneous carry generation for, or propagation over, two or more stages
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/506—Indexing scheme relating to groups G06F7/506 - G06F7/508
    • G06F2207/5063—2-input gates, i.e. only using 2-input logical gates, e.g. binary carry look-ahead, e.g. Kogge-Stone or Ladner-Fischer adder

Landscapes

  • Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Analysis (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Computing Systems (AREA)
  • Mathematical Optimization (AREA)
  • General Engineering & Computer Science (AREA)
  • Nonlinear Science (AREA)
  • Logic Circuits (AREA)
  • Complex Calculations (AREA)
EP16802335.6A 2015-05-29 2016-02-15 Floating point computation apparatus and method Active EP3289445B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US14/726,246 US9836278B2 (en) 2015-05-29 2015-05-29 Floating point computation apparatus and method
PCT/CN2016/073816 WO2016192412A1 (en) 2015-05-29 2016-02-15 Floating point computation apparatus and method

Publications (3)

Publication Number Publication Date
EP3289445A1 EP3289445A1 (en) 2018-03-07
EP3289445A4 true EP3289445A4 (en) 2018-05-30
EP3289445B1 EP3289445B1 (en) 2020-02-05

Family

ID=57397078

Family Applications (1)

Application Number Title Priority Date Filing Date
EP16802335.6A Active EP3289445B1 (en) 2015-05-29 2016-02-15 Floating point computation apparatus and method

Country Status (4)

Country Link
US (1) US9836278B2 (en)
EP (1) EP3289445B1 (en)
CN (1) CN107533462B (en)
WO (1) WO2016192412A1 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4488252A (en) * 1982-02-22 1984-12-11 Raytheon Company Floating point addition architecture
US20040225706A1 (en) * 2003-05-05 2004-11-11 Harris David L. Parallel prefix networks that make tradeoffs between logic levels, fanout and wiring racks

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GB8910960D0 (en) 1989-05-12 1989-06-28 Secr Defence Digital processor for two's complement computations
US5339447A (en) 1989-11-17 1994-08-16 Texas Instruments Incorporated Ones counting circuit, utilizing a matrix of interconnected half-adders, for counting the number of ones in a binary string of image data
JP3502302B2 (en) 1999-07-16 2004-03-02 日本電信電話株式会社 Frequency synthesizer
US6665698B1 (en) 2000-05-12 2003-12-16 Hewlett-Packard Development Company, L.P. High speed incrementer/decrementer
EP1296223A3 (en) 2001-09-24 2005-09-14 Broadcom Corporation Adder incrementer circuit
US6591286B1 (en) * 2002-01-18 2003-07-08 Neomagic Corp. Pipelined carry-lookahead generation for a fast incrementer
DE10216240A1 (en) 2002-04-12 2003-10-30 Infineon Technologies Ag Method and device for calculating an iterated state of a feedback shift register arrangement
US7308471B2 (en) 2003-03-28 2007-12-11 Arithmatica Limited Method and device for performing operations involving multiplication of selectively partitioned binary inputs using booth encoding
US7475301B2 (en) 2003-05-09 2009-01-06 Hewlett-Packard Development Company, L.P. Increment/decrement circuit for performance counter
CN1591824A (en) 2003-08-26 2005-03-09 中国科学院微电子中心 Structure of realizing 40 bit fast accumulation subtraction apparatus circuit with roundoff function
US7447727B2 (en) * 2004-06-28 2008-11-04 Intel Corporation Recursive carry-select topology in incrementer designs
US7743308B2 (en) 2005-02-09 2010-06-22 Adaptec, Inc. Method and system for wire-speed parity generation and data rebuild in RAID systems
US8214416B2 (en) 2008-07-28 2012-07-03 Agere Systems Inc. Floating-point addition acceleration
US8316071B2 (en) * 2009-05-27 2012-11-20 Advanced Micro Devices, Inc. Arithmetic processing unit that performs multiply and multiply-add operations with saturation and method therefor
CN102243577A (en) * 2010-05-10 2011-11-16 上海华虹集成电路有限责任公司 Circuit for rapidly realizing floating-point addition
GB201111035D0 (en) * 2011-06-29 2011-08-10 Advanced Risc Mach Ltd Floating point adder
CN102707931A (en) 2012-05-09 2012-10-03 刘大可 Digital signal processor based on parallel data channel

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4488252A (en) * 1982-02-22 1984-12-11 Raytheon Company Floating point addition architecture
US20040225706A1 (en) * 2003-05-05 2004-11-11 Harris David L. Parallel prefix networks that make tradeoffs between logic levels, fanout and wiring racks

Non-Patent Citations (4)

* Cited by examiner, † Cited by third party
Title
BEAUMONT-SMITH A ET AL: "REDUCED LATENCY IEEE FLOATING-POINT STANDARD ADDER ARCHITECTURES", PROCEEDINGS 14TH IEEE SYMPOSIUM ON COMPUTER ARITHMETIC. ADELAIDE, AU, APRIL 14 - 16, 1999; [IEEE SYMPOSIUM ON COMPUTER ARITHMETIC], LOS ALAMITOS, CA : IEEE COMP. SOC. PRESS, US, 14 April 1999 (1999-04-14), pages 35 - 42, XP000876405, ISBN: 978-0-7803-5609-2, DOI: 10.1109/ARITH.1999.762826 *
BRENT R P ET AL: "A REGULAR LAYOUT FOR PARALLEL ADDERS", IEEE TRANSACTIONS ON COMPUTERS, IEEE, USA, vol. C-31, no. 3, 1 March 1982 (1982-03-01), pages 260 - 264, XP000561905, ISSN: 0018-9340 *
DAVIDE DOZZA ET AL: "A 3.5 NS, 64 BIT, CARRY-LOOKAHEAD ADDER", PROCEEDINGS - IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - CIRCUITS AND SYSTEMS CONNECTING THE WORLD, 1 January 1996 (1996-01-01), XP055468126, Retrieved from the Internet <URL:https://ieeexplore.ieee.org/ielx3/3834/11196/00541705.pdf?tp=&arnumber=541705&isnumber=11196> [retrieved on 20180418] *
See also references of WO2016192412A1 *

Also Published As

Publication number Publication date
WO2016192412A1 (en) 2016-12-08
US20160350073A1 (en) 2016-12-01
CN107533462B (en) 2020-07-24
US9836278B2 (en) 2017-12-05
EP3289445A1 (en) 2018-03-07
EP3289445B1 (en) 2020-02-05
CN107533462A (en) 2018-01-02

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