EP3274832A1 - Byte level granularity buffer overflow detection for memory corruption detection architectures - Google Patents
Byte level granularity buffer overflow detection for memory corruption detection architecturesInfo
- Publication number
- EP3274832A1 EP3274832A1 EP16769192.2A EP16769192A EP3274832A1 EP 3274832 A1 EP3274832 A1 EP 3274832A1 EP 16769192 A EP16769192 A EP 16769192A EP 3274832 A1 EP3274832 A1 EP 3274832A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- memory
- mcd
- processor
- contiguous
- data
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/073—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment in a memory management context, e.g. virtual memory or cache management
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0751—Error or fault detection not based on redundancy
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0766—Error or fault reporting or storing
- G06F11/0772—Means for error signaling, e.g. using interrupts, exception flags, dedicated error registers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/079—Root cause analysis, i.e. error or fault diagnosis
Definitions
- Memory corruption can be a major resource issue leading to system malfunctions and can negatively impact a performance of a system.
- Memory corruption can arise from a variety of causes, including: programming errors, out-of-bound accesses, dangling pointers, and malicious attacks on memory.
- Use of corrupted memory contents in a computer program may cause the computer program to crash or to act abnormally.
- Software solutions may be used for memory corruption detection, such as debugging tools. However, the software solutions may cause a computer program to run significantly slower and can be difficult to use in debugging the computer program.
- FIG. 1 illustrates a memory corruption detection (MCD) system according to one embodiment.
- FIG. 2 illustrates an architecture of an MCD system with a system memory and a MCD table according to one embodiment.
- FIG. 3 depicts a flow diagram of a method for associating one or more memory blocks of a memory object with memory allocation information of a MCD meta-data word according to one embodiment.
- FIG. 4A illustrates a MCD meta-data word associated with a memory block according to one embodiment.
- FIG. 6A is a block diagram illustrating an in-order pipeline and a register renaming stage, out-of-order issue/execution pipeline according to one embodiment.
- FIG. 6B is a block diagram illustrating a micro-architecture for a processor that implements secure memory repartitioning according to one embodiment.
- FIG. 7 illustrates a block diagram of the micro-architecture for a processor that includes logic circuits to perform secure memory repartitioning according to one embodiment.
- FIG. 8 is a block diagram of a computer system according to one implementation.
- FIG. 9 is a block diagram of a computer system according to another
- FIG. 10 is a block diagram of a system-on-a-chip according to one implementation.
- FIG. 11 illustrates another implementation of a block diagram for a computing system.
- Memory corruption can occur when the contents of a memory location are accessed. The contents in the memory location can be unintentionally accessed because of programming errors or intentionally modified because of a malicious attack.
- One cause of memory corruption can be a coding error, where an application erroneously writes into or reads unintended memory blocks of a system memory.
- Another cause of memory corruption can be when an application uses an invalid pointer to write data into a memory block that has been freed.
- Another cause of memory corruption can be when an application attempts to write data into a memory block header (or other restricted or reserved memory regions) that may be managed by the operating system (OS).
- OS operating system
- MCD Memory Corruption Detection
- N bytes such as 64 byte blocks
- B N bytes
- architecture may use performance or memory overheads that limit a use of the traditional MCD to debug or pre-production uses.
- Heap memory is an area of reserved memory that a program or application can use to store data in a variable amount that may be used when a program is running.
- an application may receive different amounts or types of input data for processing (such as from different users) and store the input data in heap memory.
- the application can process the different amounts or types of input data as the application may be running.
- An allocation library executed by a processor can be used for memory allocations, freeing of memory, and memory corruption detection (MCD) data management.
- MCD memory corruption detection
- a processing system or processor may be operable to validate pointers produced by memory access instructions of applications being executed by the processing system or processor.
- the processing system may maintain a meta-data table that stores identifiers for different allocated buffers (e.g., memory allocations) including one or more contiguous memory blocks of a system memory.
- the contiguous memory blocks of the system memory can be a same pre-defined size, such as 64 bytes (B) or 32B.
- the contiguous memory blocks of the system memory can different sizes.
- a unique identifier may be generated and associated with one or more contiguous memory blocks that can store data written to the memory object.
- the unique identifiers for the contiguous memory blocks may be MCD unique identifiers or MCD color designations.
- contiguous memory blocks allocated for a memory object can be assigned a MCD color value, such as a 6 bit meta-data value.
- the MCD unique identifiers for different memory objects may be stored in one or more MCD table entries of a MCD table that correspond to the contiguous memory blocks being allocated for the memory objects.
- An MCD unique identifier may also be stored in one or more bits (e.g., upper bits) of a pointer that can be returned by a memory allocation routine to an application that has requested a memory allocation.
- the processor may compare a MCD unique identifier retrieved from the MCD table to a MCD unique identifier extracted from the pointer specified by the memory access instruction. When the MCD unique identifiers do not match, a fault may be generated.
- FIG. 1 illustrates a MCD system 100 according to one embodiment.
- the MCD system 100 can include pointers 102 and a system memory 104.
- the pointers 102 can include a MCD unique ID field or a MCD color value field 110 and a memory address field.
- pointer 106 can include a MCD unique ID 110 and a memory address 112
- pointer 108 can include a MCD unique ID 114 and a memory address 118.
- the MCD unique IDs 110 and 114 can be stored in one or more bits (such as upper bits, which may not be part of a linear address) of the pointers 106 and 108, respectively.
- the memory addresses 112 and 118 can reference beginning address locations of memory objects 138 and 140 in the system memory 104.
- memory address 112 can reference an address location to contiguous memory block 128 and memory address 118 can reference an address location to contiguous memory block 132.
- the memory objects 138 and 140 can include one or more contiguous memory blocks.
- memory object 138 can include contiguous memory blocks 128 and 130 and memory object 140 can include contiguous memory blocks 132, 134, and 136.
- a memory allocation routine e.g., by a calloc routine, a malloc routine, or a realloc routine
- MCD unique IDs 120 and 124 may be associated with the contiguous memory blocks 128-130 and 130-136, respectively.
- the MCD system 100 may receive a memory access instruction from an application requesting object data of a contiguous memory block.
- MCD system 100 may receive a memory access instruction, where the memory access instruction includes the pointer 106 with a memory address 112 indicating a beginning location of the object data 122 at contiguous memory block 128.
- the MCD system 100 can compare the MCD unique ID 110 of the pointer 106 with the MCD unique ID 120 associated with the contiguous memory block 128. When the MCD unique ID 110 matches the MCD unique ID 120, the MCD system 100 may communicate the object data 122 to the requesting application.
- FIG. 2 illustrates an architecture of an MCD system 200 with a system memory 104 and a MCD table 202 according to one embodiment.
- the MCD system 200 includes a pointer 106 that includes an MCD unique ID 110 and a memory address 112 referencing a memory object 138.
- the memory object 138 can include contiguous memory blocks 122A-122N.
- the MCD table 202 may include MCD unique IDs 120A-120N and MCD border values 121A- 121N associated with the contiguous memory blocks 122A-122N, respectively.
- the MCD unique IDs 120A-120N and the MCD border values 121A-121N can be stored at offsets derived from the base addresses of the corresponding contiguous memory blocks 122A-122N.
- FIG. 3 depicts a flow diagram of a method 300 for associating one or more memory blocks of a memory object with memory allocation information of a MCD meta-data word.
- Method 300 may be performed by a computer system that may comprise hardware (e.g., circuitry, dedicated logic, and/or programmable logic), software (e.g., instructions executable on a computer system to perform hardware simulation), or a combination thereof.
- Method 300 and/or each of its functions, routines, subroutines, or operations may be performed by one or more physical processors of the computer system executing the method. Two or more functions, routines, subroutines, or operations of method 300 may be performed in parallel or in an order which may differ from the order described above.
- method 300 may be performed by a single processing thread. Alternatively, method 300 may be performed by two or more processing threads, each thread executing one or more individual functions, routines, subroutines, or operations of the method. In an illustrative example, the processing threads implementing method 300 may be synchronized (e.g., using semaphores, critical sections, and/or other thread synchronization mechanisms). Alternatively, the processing threads implementing method 300 may be executed asynchronously with respect to each other.
- the method 300 may begin with a processor or software library
- the processor can receive the allocation request when the application begins or may be initiated (e.g., an initial allocation request of memory from the application).
- the Drocessor or software library can receive the allocation request while the application may be running (e.g., a subsequent allocation request of memory from the application).
- the method can further include, determining, by the processor or software library, a size of the memory object requested by the allocation request, such as an amount of bytes (N bytes) of memory (block 320).
- the memory can be broken down into fixed block sizes of memory (e.g., contiguous memory blocks).
- the memory blocks can be 64 bytes (B) of contiguous memory.
- the memory block size of 64B is not intended to be limiting and the memory block sizes can be any size set by an allocation library of the processor or a MCD system.
- the software library can determine a size of memory being requested based on allocation size information included in the allocation request.
- the method can include allocating, by a processor or software library, the one or more contiguous memory blocks for the memory object in view of a size of the memory object requested (block 330).
- the method can also include writing, into a MCD table, a MCD meta-data word (step 340).
- a MCD meta-data word may be written into the MCD table for each block.
- the MCD meta-data word can include: a MCD unique ID associated and a MCD border value with the one or more contiguous memory blocks.
- the MCD border value can indicate a size of a used (legal) memory region or an unused (illegal) memory region of a memory block.
- the method can include determining a location of a MCD border based on the MCD border value, as discussed in the proceeding paragraphs.
- each memory block of a memory block can be 64B, e.g., consecutive bytes from 1 to 64 bytes.
- the MCD meta-data word can include 6 bits (b) for the MCD border value.
- the MCD border value can be log 2 (total memory block size) bits to describe the size of the legal or illegal memory region.
- the MCD meta-data word can be a number of MCD unique ID bits plus a number of MCD border value bits, e.g., MCD unique ID bits + MCD border value bits.
- the method can also include creating a pointer (block 350).
- the pointer can include a memory address indicating a location of the memory object in the memory.
- the pointer can include a second MCD unique ID associated with the memory object.
- the method can also include sending, to the application, the pointer (block 360).
- FIG. 4A illustrates a MCD meta-data word 406 associated with a memory block 416 accordins to one embodiment.
- the memory block 416 can be 64B (e.g., 0B-63B) and the MCD meta-data word can be IB in size.
- the memory block 416 can include a legal access portion of memory 412 that can be a first length 418 and an illegal access portion of memory 414 that can be a second length 420, where the first length 418 plus the second length 420 can be a length of 64 bytes.
- the MCD meta-data word 406 can include a MCD unique ID 402 that can be a third length 408 and MCD border value 404 that can be a fourth length 410.
- the third length 408 can be 2b (stored in bits 0-1 in MCD meta-data word 406) in length and the fourth length 410 can be 6b (stored in bits 2-7 in MCD meta-data word 406) in length.
- the MCD border value 404 can indicate a size of the illegal access portion of memory 414.
- the processor or the software library can determine a location of a MCD border between the legal access portion of memory 412 and the illegal access portion of memory 414 by subtracting a size of the illegal access portion of memory 414 from the last byte of the memory block. For example, to determine the MCD border for a 64 bytes memory block, the processor or the software library can subtract the
- MCD border value 404 from the byte 63, e.g., the last byte in a 64 bytes memory block.
- the MCD border value 404 is 24 bytes for a memory block 416 that may be 64 bytes
- the legal access portion of memory 412 is 40 bytes
- the illegal access portion of memory 414 is 24 bytes (e.g., for a total of a 64 byte memory block).
- the MCD border value 404 is 0 bytes
- the legal access portion of memory 412 is 64 bytes and the illegal access portion of memory 414 is 0 bytes (e.g., for a total of 64 bytes).
- the MCD border value 404 can indicate a size of the legal access portion of memory 412.
- the processor or software library can determine a location of a MCD border between the legal access portion of memory 412 and the illegal access portion of memory 414 by adding a size of the legal access portion of memory 414 from a first byte of the memory block.
- the processor or software library can determine can add the MCD border value 404 to byte 0, the first byte in a 64 byte memory block. For example, when the MCD border value 404 is 20 bytes for a memory block
- the legal access portion of memory 412 is 20 bytes and the illegal access portion of memory 414 is 44 bytes (e.g., for a total of 64 bytes).
- the MCD border value 404 is lb
- the legal access portion of memory 412 is 1 bytes and the illegal access portion of memory 414 is 63 bytes (e.g., for a total of 64 bytes).
- the memory block size and/or the MCD meta-data word size are not intended to be limiting and the memory block size and/or the MCD meta-data word size can be any size set by the software library of the Drocessor or a MCD system. [0032] FIG.
- the memory block 416 can be 64 bytes (e.g., from byte 0 to byte 63) and the MCD meta-data word 430 can be 2 bytes in size.
- the memory block 416 can include a legal access portion of memory 412 that can be a first length 418 and an illegal access portion of memory 414 that can be a second length 420, where the first length 418 plus the second length 420 can be a length of 64 bytes.
- the MCD meta-data word 406 can include: a MCD unique ID 402 that can be a third length 408; a MCD border value 404 that can be a fourth length 410; a first reserved bit 422 that can be a fifth length 424, where the first reserved bit 422 can be located between the MCD unique ID 402 and the MCD border value 404; and a second reserved bit 426 that can be a sixth length 426, where the second reserved bit 426 can be located after the MCD border value 404.
- the MCD word 430 can be 16 bits in length, where the third length 408 can be 6 bits (located in bits 0-5) in length, the fifth length 424 can be 2 bits (located in bits 6-7) in length, the fourth length 410 can be 6 bits (located in bits 8-13) in length, and the sixth length 428 can be 2 bits (located in bits 14-15) in length.
- the total number of used bits in the MCD meta-data word 430 is the size of the MCD Unique ID 402, of length 408, plus the size of the MCD border value 404, of length 410. In this illustration, the lengths sum to a total of 12 bits.
- the 12 used bits may be padded with reserved bits (e.g., 4 reserved bits).
- the reserved bits can be reserved bits 422 of length 424, and reserved bits 426 of length 428.
- the arrangement of the bits and the size of the MCD meta-data word 430 are not intended to be limiting and the reserved bits can be any size set by an allocation library of the processor or the MCD system.
- the MCD border value 404 can indicate a size of the illegal access portion of memory 414.
- the processor or allocation library can determine a location of a MCD border between the legal access portion of memory 412 and the illegal access portion of memory 414 by subtracting a size of the illegal access portion of memory 414 from the last byte of the memory block 416.
- the processor or allocation library can determine the location of a MCD border by subtracting the MCD border value from the byte 63, the last byte in a 64 bytes memory block 416.
- the MCD border value 404 can indicate a size of the legal access portion of memory 412.
- the processor or allocation library can determine a location of a MCD border between the legal access portion of memory 412 and the illegal access portion of memory 414 bv addins a size of the lesal access portion of memory 414 to the first byte of the memory block. For example, the processor or allocation library can determine the location of a MCD border by adding the border from byte 0, the first byte in a 64 byte memory block 416.
- the memory block size and/or the MCD meta-data word size are not intended to be limiting and the memory block size and/or the MCD meta-data word size can be any size set by the software library of the processor or a MCD system.
- FIG. 5A illustrates a first memory block 540 and a second memory block 562 allocated for a memory object 560 according to one embodiment.
- FIG. 5A illustrates a first memory block 540 and a second memory block 562 allocated for a memory object 560 according to one embodiment.
- an application can request a 100b memory object 560, where the memory object 560 can include a first memory block 540 and a second memory block 562.
- the memory object 560 can include a first memory block 540 and a second memory block 562.
- the first memory block 540 and the second memory block 562 can each be 64 bytes.
- a first MCD meta-data word 530 can be associated with the first memory block 540 and a second MCD meta-data word 562 can be associated with the second memory block 562.
- the processor or allocation library can allocate all of the memory (64 bytes) of the first memory block 540 to be used to store data.
- the first MCD meta-data word 530 associated with the first memory block 540, can have a first MCD Border value 504 of 0, indicating that all of the bytes (64 bytes) the first memory block 540 may be legal (e.g., usable).
- the second MCD meta-data word 550 associated with the second memory block 562, can have a second MCD border value 546 of 28.
- the second MCD border value 546 of 28 can indicate the first 36 contiguous bytes of the memory block 562 can be legal and the last 28 contiguous bytes can be illegal.
- the memory block size and/or the MCD meta-data word size are not intended to be limiting and the memory block size and/or the MCD meta-data word size can be any size set by the software library of the processor or a MCD system.
- FIG. 5B depicts a flow diagram of a method 500 for checking for out-of-bound memory accesses in a memory according to one embodiment.
- Method 500 may be performed by a computer system that may comprise hardware (e.g., circuitry, dedicated logic, and/or programmable logic), software (e.g., instructions executable on a computer system to perform hardware simulation), or a combination thereof.
- Method 500 and/or each of its functions, routines, subroutines, or operations may be performed by one or more physical processors of the computer system executing the method. Two or more functions, routines, subroutines, or operations of method 500 may be performed in parallel or in an order which may differ from the order described above.
- method 300 may be performed by a single processing thread.
- method 500 may be performed by two or more processing threads, each thread executing one or more individual functions, routines, subroutines, or operations of the method.
- the processing threads implementing method 500 may be synchronized (e.g., using semaphores, critical sections, and/or other thread synchronization mechanisms).
- the processing threads implementing method 500 may be executed asynchronously with respect to each other.
- the method 500 may begin with a processor or software library receiving, from an application, a memory access request to access data of a memory object with a contiguous memory block (block 570).
- the memory access request can include a pointer indicating a location of a beginning of the memory object the application may be requesting to access.
- the pointer can also include a first MCD unique ID for the memory object.
- the method can include the processor or software library retrieving data (e.g., MCD meta-data) stored in the contiguous memory block based on the location indicated by the pointer (block 572).
- the method can include retrieving, from the MCD table, allocation information associated with the contiguous memory block (block 574).
- the allocation information can include a second MCD unique identifier associated with the contiguous memory block and a MCD border value indicating a size of the first memory region of the contiguous memory block.
- the method can include the processor or software library comparing the first MCD unique ID to the second MCD unique ID to determine when the retrieved data is from the memory object indicated by the pointer (block 576).
- the method can include the processor or software library determining when the retrieved data is from the usable region of memory based on the allocation information (block 578).
- the method can include the processor or software library sending, to the application, a fault message when a fault event associated with the retrieved data occurs based on the allocation information (block 580).
- the fault event can include: a mismatch between the first MCD unique ID and the second MCD unique ID or an access to an illegal region within a memory block of the memory object.
- Each memory block of a memory can have a different MCD unique ID.
- an application can perform a memory block access underflow when storing or reading data in a memory (e.g., an out of bound access before the beginning of a current memory block). When the application underflows the memory block, the processor or software library can detect the underflow when a first MCD unique ID of the current memory block mismatches a second MCD unique ID of a previous memory block.
- an application can perform a memory block access overflow when storing or reading data in a memory (e.g., an out of bound access after a current memory block). When the application overflows the memory block, the processor or software library can detect the overflow.
- the processor or software library can determine that the access is in the illegal access region based on a MCD border value associated with a last memory block of the memory object (as discussed in the preceding paragraphs). For example, in FIG. 5A the processor or software library can use the MCD border value 546 to determine that the illegal access region is between byte 35 and byte 63. In this example, when the application attempts to access any byte between byte 35 and byte 63, the processor or software library can determine that the application has overflowed into the illegal access region 534.
- the processor or software library can determine that the application has overflowed into a next memory object based on a mismatch between the first MCD unique ID of the current memory block and a third MCD unique ID of the next memory block. For example, in FIG. 5A the when the application attempts to access memory beyond 63B of the memory block 562, the processor or software library can determine that the application has overflowed because the first MCD unique ID 542 of the memory block 562 may not match the third MCD unique ID of the next memory block.
- An advantage of the processor or software library detecting the underflow or overflow as discussed in the preceding paragraphs is to enable the processor or software library to detect an underflow or overflow as small as 1- byte.
- the access can enable the software to access any canonical pointer.
- a non-MCD pointer can access any data in the memory.
- An advantage of a non-MCD pointer accessing any data in the memory can be to avoid altering behavior of a legacy program (e.g., a program not configured for the MCD architecture).
- FIG. 6A is a block diagram illustrating a micro-architecture for a processor 600 that implements secure memory repartitioning according to one embodiment.
- processor 600 depicts an in-order architecture core and a register renaming logic, out-of-order issue/execution losic to be included in a processor according to at least one embodiment of the disclosure.
- the embodiments of the page additions and content copying can be implemented in processor 600.
- Processor 600 includes a front end unit 630 coupled to an execution engine unit 650, and both are coupled to a memory unit 670.
- the processor 600 may include a reduced instruction set computing (RISC) core, a complex instruction set computing (CISC) core, a very long instruction word (VLIW) core, or a hybrid or alternative core type.
- processor 600 may include a special-purpose core, such as, for example, a network or communication core, compression engine, graphics core, or the like.
- processor 600 may be a multi-core processor or may be part of a multi-processor system.
- the front end unit 630 includes a branch prediction unit 632 coupled to an instruction cache unit 634, which is coupled to an instruction translation lookaside buffer (TLB) 636, which is coupled to an instruction fetch unit 638, which is coupled to a decode unit 660.
- the decode unit 660 (also known as a decoder) may decode instructions, and generate as an output one or more micro-operations, micro-code entry points,
- the decoder 660 may be implemented using various different mechanisms. Examples of suitable mechanisms include, but are not limited to, look-up tables, hardware implementations, programmable logic arrays (PLAs), microcode read only memories (ROMs), etc.
- the instruction cache unit 634 is further coupled to the memory unit 670.
- the decode unit 660 is coupled to a rename/allocator unit 652 in the execution engine unit 650.
- the execution engine unit 650 includes the rename/allocator unit 652 coupled to a retirement unit 654 and a set of one or more scheduler unit(s) 656.
- the scheduler unit(s) 656 represents any number of different schedulers, including reservations stations (RS), central instruction window, etc.
- the scheduler unit(s) 656 is coupled to the physical register file(s) unit(s) 658.
- Each of the physical register file(s) units 658 represents one or more physical register files, different ones of which store one or more different data types, such as scalar integer, scalar floating point, packed integer, packed floating point, vector integer, vector floating point, etc., status (e.g., an instruction pointer that is the address of the next instruction to be executed), etc.
- the physical register file(s) unit(s) 658 is overlapped by the retirement unit 654 to illustrate various ways in which register renaming and out-of-order execution may be implemented (e.g., using a reorder buffer(s) and a retirement register file(s), using a future file(s), a history buffer(s), and a retirement register file(s); using a register maps and a pool of resisters; etc.).
- the architectural registers are visible from the outside of the processor or from a programmer's perspective.
- the registers are not limited to any known particular type of circuit. Various different types of registers are suitable as long as they are capable of storing and providing data as described herein.
- suitable registers include, but are not limited to, dedicated physical registers, dynamically allocated physical registers using register renaming, combinations of dedicated and dynamically allocated physical registers, etc.
- the retirement unit 654 and the physical register file(s) unit(s) 658 are coupled to the execution cluster(s) 660.
- the execution cluster(s) 660 includes a set of one or more execution units 662 and a set of one or more memory access units 664.
- the execution units 662 may perform various operations (e.g., shifts, addition, subtraction, multiplication) and operate on various types of data (e.g., scalar floating point, packed integer, packed floating point, vector integer, vector floating point).
- scheduler unit(s) 656, physical register file(s) unit(s) 658, and execution cluster(s) 660 are shown as being possibly plural because certain embodiments create separate pipelines for certain types of
- data/operations e.g., a scalar integer pipeline, a scalar floating point/packed integer/packed floating point/vector integer/vector floating point pipeline, and/or a memory access pipeline that each have their own scheduler unit, physical register file(s) unit, and/or execution cluster - and in the case of a separate memory access pipeline, certain embodiments are implemented in which only the execution cluster of this pipeline has the memory access unit(s) 664). It should also be understood that where separate pipelines are used, one or more of these pipelines may be out-of-order issue/execution and the rest in-order.
- the set of memory access units 664 is coupled to the memory unit 670, which may include a data prefetcher 680, a data TLB unit 672, a data cache unit (DCU) 674, and a level 2 (L2) cache unit 676, to name a few examples.
- DCU 674 is also known as a first level data cache (LI cache).
- the DCU 674 may handle multiple outstanding cache misses and continue to service incoming stores and loads. It also supports maintaining cache coherency.
- the data TLB unit 672 is a cache used to improve virtual address translation speed by mapping virtual and physical address spaces.
- the memory access units 664 may include a load unit, a store address unit, and a store data unit, each of which is coupled to the data TLB unit 672 in the memory unit 670.
- the L2 cache unit 676 mav be couDled to one or more other levels of cache and eventually to a main memory.
- the data prefetcher 680 speculatively loads/prefetches data to the DCU 674 by automatically predicting which data a program is about to consume.
- Prefetching may refer to transferring data stored in one memory location (e.g., position) of a memory hierarchy (e.g., lower level caches or memory) to a higher- level memory location that is closer (e.g., yields lower access latency) to the processor before the data is actually demanded by the processor. More specifically, prefetching may refer to the early retrieval of data from one of the lower level caches/memory to a data cache and/or prefetch buffer before the processor issues a demand for the specific data being returned.
- a memory hierarchy e.g., lower level caches or memory
- prefetching may refer to the early retrieval of data from one of the lower level caches/memory to a data cache and/or prefetch buffer before the processor issues a demand for the specific data being returned.
- the processor 600 may support one or more instructions sets (e.g., the x86 instruction set (with some extensions that have been added with newer versions); the MIPS instruction set of MIPS Technologies of Sunnyvale, CA; the ARM instruction set (with optional additional extensions such as NEON) of ARM Holdings of Sunnyvale, CA).
- the x86 instruction set (with some extensions that have been added with newer versions); the MIPS instruction set of MIPS Technologies of Sunnyvale, CA; the ARM instruction set (with optional additional extensions such as NEON) of ARM Holdings of Sunnyvale, CA).
- the core may support multithreading (executing two or more parallel sets of operations or threads), and may do so in a variety of ways including time sliced multithreading, simultaneous multithreading (where a single physical core provides a logical core for each of the threads that physical core is simultaneously multithreading), or a combination thereof (e.g., time sliced fetching and decoding and simultaneous multithreading thereafter such as in the Intel® Hyperthreading technology).
- register renaming is described in the context of out-of-order execution, it should be understood that register renaming may be used in an in-order architecture.
- the illustrated embodiment of the processor also includes a separate instruction and data cache units and a shared L2 cache unit, alternative embodiments may have a single internal cache for both instructions and data, such as, for example, a Level 1 (LI) internal cache, or multiple levels of internal cache.
- the system may include a combination of an internal cache and an external cache that is external to the core and/or the processor.
- all of the cache may be external to the core and/or the processor.
- FIG. 6B is a block diagram illustrating an in-order pipeline and a register renaming stage, out-of-order issue/execution pipeline implemented by processor 600 of FIG. 6A according to some embodiments of the disclosure.
- the solid lined boxes in FIG. 6B illustrate an in-order pipeline, while the dashed lined boxes illustrates a register renaming, out-of-order issue/execution pipeline.
- a processor pipeline 600 includes a fetch stage 602, a length decode stage 604, a decode stage 606, an allocation stage 608, a renaming stage 610, a scheduling (also known as a dispatch or issue) stage 612, a register read/memory read stage
- stages 602-624 may be different than illustrated and are not limited to the specific ordering shown in FIG. 6B.
- FIG. 7 illustrates a block diagram of the micro-architecture for a processor 700 that includes logic circuits to perform secure memory repartitioning according to one embodiment.
- an instruction in accordance with one embodiment can be
- the in-order front end 701 is the part of the processor 700 that fetches instructions to be executed and prepares them to be used later in the processor pipeline.
- the embodiments of the page additions and content copying can be implemented in processor 700.
- the front end 701 may include several units.
- the instruction pref etcher 716 fetches instructions from memory and feeds them to an instruction decoder 718 which in turn decodes or interprets them.
- the decoder decodes a received instruction into one or more operations called "micro-instructions" or “micro-operations” (also called micro op or uops) that the machine can execute.
- the decoder parses the instruction into an opcode and corresponding data and control fields that are used by the micro-architecture to perform operations in accordance with one embodiment.
- the trace cache 730 takes decoded uops and assembles them into program ordered sequences or traces in the uop queue 734 for execution.
- the microcode ROM 732 provides the uops needed to complete the operation.
- Some instructions are converted into a single micro-op, whereas others need several micro-ops to complete the full operation.
- the decoder 718 accesses the microcode ROM 732 to do the instruction.
- an instruction can be decoded into a small number of micro ops for processing at the instruction decoder 718.
- an instruction can be stored within the microcode ROM 732 should a number of micro-ops be needed to accomplish the operation.
- the trace cache 730 refers to an entry point
- the out-of-order execution engine 703 is where the instructions are prepared for execution.
- the out-of-order execution logic has a number of buffers to smooth out and reorder the flow of instructions to optimize performance as they go down the pipeline and get scheduled for execution.
- the allocator logic allocates the machine buffers and resources that each uop needs in order to execute.
- the register renaming logic renames logic registers onto entries in a register file.
- the allocator also allocates an entry for each uop in one of the two uop queues, one for memory operations and one for non-memory operations, in front of the instruction schedulers: memory scheduler, fast scheduler 702, slow/general floating point scheduler 704, and simple floating point scheduler 706.
- the uop schedulers 702, 704, 706, determine when a uop is ready to execute based on the readiness of their dependent input register operand sources and the availability of the execution resources the uops need to complete their operation.
- the fast scheduler 702 of one embodiment can schedule on each half of the main clock cycle while the other schedulers can only schedule once per main processor clock cycle.
- the schedulers arbitrate for the dispatch ports to schedule uops for execution.
- Register files 708, 710 sit between the schedulers 702, 704, 706, and the execution units 712, 714, 716, 718, 710, 712, 714 in the execution block 711.
- Each register file 708, 710 also includes a bypass network that can bypass or forward just completed results that have not yet been written into the register file to new dependent uops.
- the integer register file 708 and the floating point register file 710 are also capable of communicating data with the other.
- the integer register file 708 is split into two separate register files, one register file for the low order 32 bits of data and a second register file for the high order 32 bits of data.
- the floating point register file 710 of one embodiment has 128 bit wide entries because floating point instructions typically have operands from 64 to 128 bits in width.
- the execution block 711 contains the execution units 712, 714, 716, 718, 710, 712, 714, where the instructions are actually executed.
- This section includes the register files 708, 710, that store the integer and floating point data operand values that the micro-instructions need to execute.
- the processor 700 of one embodiment is comprised of a number of execution units: address generation unit (AGU) 712, AGU 714, fast ALU 716, fast ALU 718, slow ALU 710, floating point ALU 712, floating point move unit 714.
- AGU address generation unit
- the floating point execution blocks 712, 714 execute floating point, MMX, SEVID, and SSE, or other oDerations.
- the floatins Doint ALU 712 of one embodiment includes a 64 bit by 64 bit floating point divider to execute divide, square root, and remainder micro-ops. For
- instructions involving a floating point value may be handled with the floating point hardware.
- the ALU operations go to the high-speed ALU execution units 716, 718.
- the fast ALUs 716, 718, of one embodiment can execute fast operations with an effective latency of half a clock cycle.
- most complex integer operations go to the slow ALU 710 as the slow ALU 710 includes integer execution hardware for long latency type of operations, such as a multiplier, shifts, flag logic, and branch processing.
- Memory load/store operations are executed by the AGUs 712, 714.
- the integer ALUs 716, 718, 710 are described in the context of performing integer operations on 64 bit data operands. In alternative embodiments, the ALUs 716, 718, 710, can be
- the floating point units 712, 714 can be implemented to support a range of operands having bits of various widths.
- the floating point units 712, 714 can operate on 128 bits wide packed data operands in conjunction with SEVID and multimedia instructions.
- the uops schedulers 702, 704, 706, dispatch dependent operations before the parent load has finished executing.
- the processor 700 also includes logic to handle memory misses. If a data load misses in the data cache, there can be dependent operations in flight in the pipeline that have left the scheduler with temporarily incorrect data.
- a replay mechanism tracks and re-executes instructions that use incorrect data. Only the dependent operations need to be replayed and the independent ones are allowed to complete.
- the schedulers and replay mechanism of one embodiment of a processor are also designed to catch instruction sequences for text string comparison operations.
- the processor 700 also includes logic to implement secure memory repartitioning according to one embodiment.
- the execution block 711 of processor 700 may include MCU 115, to perform secure memory repartitioning according to the description herein.
- registers may refer to the on-board processor storage locations that are used as part of instructions to identify operands. In other words, registers may be those that are usable from the outside of the processor (from a programmer's perspective). However, the registers of an embodiment should not be limited in meaning to a particular type of circuit.
- a register of an embodiment is capable of storing and providing data, and performing the functions described herein.
- the registers described herein can be implemented by circuitry within a processor using any number of different techniques, such as dedicated physical registers, dynamically allocated physical registers using register renaming, combinations of dedicated and dynamically allocated physical registers, etc.
- integer registers store thirty-two bit integer data.
- a register file of one embodiment also contains eight multimedia SIMD registers for packed data.
- the registers are understood to be data registers designed to hold packed data, such as 64 bits wide MMXTM registers (also referred to as 'mm' registers in some instances) in microprocessors enabled with MMX technology from Intel Corporation of Santa Clara, California. These MMX registers, available in both integer and floating point forms, can operate with packed data elements that accompany SIMD and SSE instructions. Similarly, 128 bits wide XMM registers relating to SSE2, SSE3, SSE4, or beyond (referred to generically as "SSEx”) technology can also be used to hold such packed data operands.
- SSEx 128 bits wide XMM registers relating to SSE2, SSE3, SSE4, or beyond
- the registers do not need to differentiate between the two data types.
- integer and floating point are either contained in the same register file or different register files.
- floating point and integer data may be stored in different registers or the same registers.
- multiprocessor system 800 is a point-to-point interconnect system, and includes a first processor 870 and a second processor 880 coupled via a point-to-point interconnect 850.
- processors 870 and 880 may be multicore processors, including first and second processor cores (i.e., processor cores 874a and 874b and processor cores 884a and 884b), although potentially many more cores may be present in the processors.
- the processors each may include hybrid write mode logics in accordance with an embodiment of the present.
- the embodiments of the page additions and content copying can be implemented in the processor 870, processor 880, or both.
- processors 870, 880 While shown with two processors 870, 880, it is to be understood that the scope of the present disclosure is not so limited. In other implementations, one or more additional processors may be present in a given processor.
- Processors 870 and 880 are shown including integrated memory controller units 882 and 882, respectively.
- Processor 870 also includes as part of its bus controller units point-to- point (P-P) interfaces 876 and 888; similarly, second processor 880 includes P-P interfaces 886 and 888.
- Processors 870, 880 may exchange information via a point-to-point (P-P) interface 850 usins P-P interface circuits 888, 888.
- P-P point-to-point
- IMCs 882 and 882 couple the processors to respective memories, namely a memory 832 and a memory 834, which may be portions of main memory locally attached to the respective processors.
- Processors 870, 880 may each exchange information with a chipset 890 via individual P-P interfaces 852, 854 using point to point interface circuits 876, 894, 886, 898.
- Chipset 890 may also exchange information with a high-performance graphics circuit 838 via a high-performance graphics interface 839.
- a shared cache (not shown) may be included in either processor or outside of both processors, yet connected with the processors via P-P interconnect, such that either or both processors' local cache information may be stored in the shared cache if a processor is placed into a low power mode.
- Chipset 890 may be coupled to a first bus 816 via an interface 896.
- first bus 816 may be a Peripheral Component Interconnect (PCI) bus, or a bus such as a PCI Express bus or another third generation IO interconnect bus, although the scope of the present disclosure is not so limited.
- PCI Peripheral Component Interconnect
- various IO devices 814 may be coupled to first bus 816, along with a bus bridge 818 which couples first bus 816 to a second bus 820.
- second bus 820 may be a low pin count (LPC) bus.
- Various devices may be coupled to second bus 820 including, for example, a keyboard and/or mouse 822, communication devices 827 and a storage unit 828 such as a disk drive or other mass storage device which may include instructions/code and data 830, in one embodiment.
- an audio IO 824 may be coupled to second bus 820.
- a system may implement a multi-drop bus or other such architecture.
- FIG. 9 shown is a block diagram of a third system 900 in accordance with an embodiment of the present invention. Like elements in FIGS. 8 and 9 bear like reference numerals, and certain aspects of FIG. 8 have been omitted from FIG. 9 in order to avoid obscuring other aspects of FIG. 9.
- FIG. 9 illustrates that the processors 970, 980 may include integrated memory and
- IO control logic (“CL") 972 and 982, respectively.
- CL IO control logic
- the CL 972 the CL 972
- CL integrated memory controller units
- FIG. 9 illustrates that the memories 932, 934 are coupled to the CL 972, 982, and that IO devices 914 are also coupled to the control logic 972,
- FIG. 10 is an exemplary system on a chip (SoC) that may include one or more of the cores 1002.
- SoC system on a chip
- DSPs digital signal processors
- an interconnect unit(s) 1002 is coupled to: an application processor 1010 which includes a set of one or more cores 1002A-N and shared cache unit(s) 1006; a system agent unit 1010; a bus controller unit(s) 1016; an integrated memory controller unit(s) 1014; a set or one or more media processors 1020 which may include integrated graphics logic 1008, an image processor 1024 for providing still and/or video camera functionality, an audio processor 1026 for providing hardware audio acceleration, and a video processor 1028 for providing video encode/decode acceleration; a static random access memory (SRAM) unit 1030; a direct memory access (DMA) unit 1032; and a display unit 1040 for coupling to one or more external displays.
- the embodiments of the pages additions and content copying can be implemented in SoC 1000.
- SoC 1100 is included in user equipment (UE).
- UE refers to any device to be used by an end-user to communicate, such as a hand-held phone, smartphone, tablet, ultra-thin notebook, notebook with broadband adapter, or any other similar communication device.
- a UE may connect to a base station or node, which can correspond in nature to a mobile station (MS) in a GSM network.
- MS mobile station
- the embodiments of the page additions and content copying can be implemented in SoC 1100.
- SoC 1100 includes 2 cores— 1106 and 1107. Similar to the discussion above, cores 1106 and 1107 may conform to an Instruction Set Architecture, such as a processor having the Intel® Architecture CoreTM, an Advanced Micro Devices, Inc. (AMD) processor, a
- Interconnect 1111 includes an on-chip interconnect, such as an IOSF, AMBA, or other interconnects discussed above, which can implement one or more aspects of the described disclosure.
- Interconnect 1111 provides communication channels to the other components, such as a Subscriber Identity Module (SIM) 1130 to interface with a SIM card, a boot ROM 1135 to hold boot code for execution by cores 1106 and 1107 to initialize and boot SoC 1100, a SDRAM controller 1140 to interface with external memory (e.g. DRAM 1160), a flash controller 1145 to interface with non-volatile memory (e.g. Flash 1165), a peripheral control 1150 (e.g. Serial Peripheral Interface) to interface with peripherals, video codecs 1120 and Video interface 1125 to display and receive input (e.g. touch enabled input), GPU 1115 to perform graphics related computations, etc. Any of these interfaces may incorporate aspects of the embodiments described herein.
- SIM Subscriber Identity Module
- boot ROM 1135 to hold boot code for execution by cores 1106 and 1107 to initialize and boot SoC 1100
- SDRAM controller 1140 to interface with external memory (e.g. DRAM 1160)
- flash controller 1145 to
- the system illustrates peripherals for communication, such as a Bluetooth module 1170, 3G modem 1175, GPS 1180, and Wi-Fi 1185.
- a UE includes a radio for communication.
- these peripheral communication modules may not all be included.
- some form of a radio for external communication should be included.
- FIG. 12 illustrates a diagrammatic representation of a machine in the exemplary form of a computer system 1200 within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein, may be executed.
- the machine may be connected (e.g., networked) to other machines in a LAN, an intranet, an extranet, or the Internet.
- the machine may operate in the capacity of a server or a client machine in a client-server network environment, or as a peer machine in a peer-to-peer (or distributed) network environment.
- the machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a Personal Digital Assistant (PDA), a cellular telephone, a web appliance, a server, a network router, switch or bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by that machine.
- PC personal computer
- PDA Personal Digital Assistant
- STB set-top box
- WPA Personal Digital Assistant
- a cellular telephone a web appliance
- server a server
- network router switch or bridge
- the exemplary computer system 1200 includes a processing device (processor) 1202, a main memory 1204 (e.g., read-only memory (ROM), flash memory, dynamic random access memorv (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), a static memory 1206 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device 1218, which communicate with each other via a bus 1230.
- a processing device e.g., a main memory 1204
- main memory 1204 e.g., read-only memory (ROM), flash memory, dynamic random access memorv (DRAM) such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.
- DRAM dynamic random access memorv
- SDRAM synchronous DRAM
- RDRAM Rambus DRAM
- static memory 1206 e.g., flash memory, static random access memory (SRAM), etc.
- SRAM static random access memory
- Processor 1202 represents one or more general-purpose processing devices such as a microprocessor, central processing unit, or the like. More particularly, the processor 1202 may be a complex instruction set computing (CISC) microprocessor, reduced instruction set computing (RISC) microprocessor, very long instruction word (VLIW) microprocessor, or a processor implementing other instruction sets or processors implementing a combination of instruction sets. The processor 1202 may also be one or more special-purpose processing devices such as an application specific integrated circuit (ASIC), a field programmable gate array (FPGA), a digital signal processor (DSP), network processor, or the like. The processor 1202 is configured to execute instructions 1226 for performing the operations and steps discussed herein.
- ASIC application specific integrated circuit
- FPGA field programmable gate array
- DSP digital signal processor
- the computer system 1200 may further include a network interface device 1222.
- the computer system 1200 also may include a video display unit 1208 (e.g., a liquid crystal display (LCD), a cathode ray tube (CRT), or a touch screen), an alphanumeric input device 1210 (e.g., a keyboard), a cursor control device 1214 (e.g., a mouse), and a signal generation device 1216 (e.g., a speaker).
- a video display unit 1208 e.g., a liquid crystal display (LCD), a cathode ray tube (CRT), or a touch screen
- an alphanumeric input device 1210 e.g., a keyboard
- a cursor control device 1214 e.g., a mouse
- a signal generation device 1216 e.g., a speaker
- the data storage device 1218 may include a computer-readable storage medium 1224 on which is stored one or more sets of instructions 1226 (e.g., software) embodying any one or more of the methodologies or functions described herein.
- the instructions 1226 may also reside, completely or at least partially, within the main memory 1204 and/or within the processor 1202 during execution thereof by the computer system 1200, the main memory 1204 and the processor 1202 also constituting computer-readable storage media.
- the instructions 1226 may further be transmitted or received over a network 1220 via the network interface device 1234.
- computer-readable storage medium 1224 is shown in an exemplary implementation to be a single medium, the term “computer-readable storage medium” should be taken to include a single medium or multiple media (e.g., a centralized or distributed database, and/or associated caches and servers) that store the one or more sets of instructions.
- the term “computer-readable storage medium” shall also be taken to include any medium that is capable of storing, encoding or carrying a set of instructions for execution by the machine and that cause the machine to perform any one or more of the methodologies of the present disclosure.
- the term “computer-readable storage medium” shall accordingly be taken to include, but not be limited to, solid-state memories, optical media, and magnetic media. The following examples pertain to further embodiments.
- Example 1 is a processor, including: 1) a memory to store data from an application, where the memory includes a memory corruption detection (MCD) table a memory object; and 2) a processor core coupled to the memory, where the processing core is to: a) receive, from an application, a memory access request to access data of the memory object with a contiguous memory block, where the memory access request includes: i) a pointer indicating a location in the memory of the memory object; and ii) a first MCD unique identifier (ID); b) retrieve data stored in the contiguous memory block of the memory object based on the location indicated by the pointer; c) retrieve, from the MCD table, allocation information associated with the contiguous memory block, where the allocation information includes: i) a second MCD unique identifier associated with the contiguous memory block; and ii) a MCD border value indicating a size of the first memory region of the contiguous memory block; and d) send, to the application, a fault
- MCD
- Example 2 the processor of Example 1 where the contiguous memory block comprises: 1) a usable memory region and an unusable memory region; and 2) the first memory region is the usable memory region or the unusable memory region.
- Example 3 the processor of Examples 1-2 where the processor core is further to: 1) compare the first MCD unique ID to the second MCD unique ID to determine when the retrieved data is from the memory object indicated by the pointer; and 2) determine when the retrieved data is from the usable region of memory based on the allocation information.
- Example 4 the processor of Examples 1-3 where the fault event occurs when: 1) the first MCD unique ID does not match the second MCD unique ID; or 2) the memory access is within the unusable memory region.
- Example 5 the processor of Examples 1-4 where the processor core is further to determine the usable memory region by: 1) subtracting the MCD border value from a size value of the contiguous memory block to obtain a border location value; and 2) identifying a MCD border location in the contiguous memory block based on border location value, where the MCD border location indicates a boundary between the usable memory region and the unusable memory region.
- Example 6 the processor of Examples 1-5 where the size of the contiguous memory block is 64 bytes.
- Example 7 the processor of Examples 1-6 where the entire contiguous memory block is the usable memory region when the MCD border value is zero.
- Example 8 is a processor, including: 1) a memory to store data from an application, where the memory includes a memory corruption detection (MCD) table; and 2) a processor core coupled to the memory, where the processing core is to: a) receive, from the application, an allocation request for an allocation of a memory object with one or more contiguous memory blocks in the memory; b) allocate the one or more contiguous memory blocks for the memory object in view of a size of the memory object requested, where a contiguous memory block of the one or more contiguous memory blocks include a first memory region and a second memory region; and c) write, into the MCD table, a MCD metadata word, where the MCD meta-data word includes: i) a first MCD unique identifier associated with the contiguous memory block; and ii) a MCD border value indicating a size of the first memory region of the contiguous memory block.
- MCD memory corruption detection
- Example 9 the processor of Example 8 where the first memory region is a used portion of the contiguous memory block.
- Example 10 the processor of Examples 8-9 where the first memory region is an unused portion of the contiguous memory block.
- Example 11 the processor of Examples 8-10 where the processor core is further to: 1) create a pointer with a memory address of the memory object and a second MCD unique identifier associated with the memory object; and 2) send, to the application, the pointer.
- Example 12 the processor of Examples 8-11 where the contiguous memory block is 64 bytes in size.
- Example 13 the processor of Examples 8-12 where the MCD meta-data word is 2 bytes in size, and where: 1) the MCD unique ID is 1 byte of the MCD meta-data word, and 2) the MCD border value is 1 byte of the MCD meta-data word.
- SoC system on a chip
- a processor including: 1) a processor; 2) a memory device, coupled to the processor, to store data from an application, wherein the memory comprises a memory corruption detection (MCD) table and a memory object; and 3) a memory controller coupled to the memory device, the memory controller to: a) receive, from an application, a memory access request to access data of the memory object with a contiguous memory block, where the memory access request includes: i) a pointer indicating a location in the memory of the memory object; and ii) a first MCD unique identifier (ID); b) retrieve data stored in the contiguous memory block based on the location indicated by the pointer; c) retrieve, from the MCD table, allocation information associated with the contiguous memory block, where the allocation information includes: i) a second MCD unique identifier associated with the contiguous memory block; and ii) a MCD border value indicating a size of the first memory region of the contiguous memory block
- Example 15 the SoC of Example 14 where the contiguous memory block comprises: 1) a usable memory region and an unusable memory region; and 2) the first memory region is the usable memory region or the unusable memory region.
- Example 16 the SoC of Examples 14-15 where the entire contiguous memory block is the usable memory region when the MCD border value is zero.
- Example 17 the SoC of Examples 14-16 where the memory controller is further to compare the first MCD unique ID to the second MCD unique ID to determine when the retrieved data is from the memory object indicated by the pointe.
- Example 18 the SoC of Examples 14-17 the memory controller is further to send, to the application, a fault message when a fault event associated with the retrieved data occurs, where the fault event occurs when: 1) the first MCD unique ID does not match the second MCD unique ID; or 2) the memory access is within the unusable memory region.
- Example 19 the SoC of Examples 14-18 where the memory controller is further to determine the usable memory region by: 1) subtracting the MCD border value from a size value of the contiguous memory block to obtain a border location value; and 2) identifying a MCD border location in the contiguous memory block based on border location value, where the MCD border location indicates a boundary between the usable memory region and the unusable memory region.
- Example 20 the SoC of Examples 14-19 where the size of the contiguous memorv block is 64 bvtes.
- Various embodiments may have different combinations of the structural features described above. For instance, all optional features of the processors and methods described above may also be implemented with respect to a system described herein and specifics in the examples may be used anywhere in one or more embodiments.
- Embodiments of the present invention may be provided as a computer program product or software which may include a machine or computer-readable medium having stored thereon instructions which may be used to program a computer (or other electronic devices) to perform one or more operations according to embodiments of the present invention.
- operations of embodiments of the present invention might be performed by specific hardware components that contain fixed-function logic for performing the operations, or by any combination of programmed computer components and fixed- function hardware components.
- Instructions used to program logic to perform embodiments of the invention can be stored within a memory in the system, such as DRAM, cache, flash memory, or other storage.
- a machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer), but is not limited to, floppy diskettes, optical disks, Compact Disc, Read-Only Memory (CD-ROMs), and magneto-optical disks, Read-Only Memory (ROMs), Random Access Memory (RAM),
- EPROM Erasable Programmable Read-Only Memory
- the computer-readable medium includes any type of tangible machine-readable medium suitable for storing or transmitting electronic instructions or information in a form readable by a machine (e.g., a computer).
- a design may go through various stages, from creation to simulation to fabrication.
- Data representing a design may represent the design in a number of manners.
- the hardware may be represented using a hardware description language or another functional description language.
- a circuit level model with logic and/or transistor gates may be produced at some stages of the design process.
- most designs, at some stage reach a level of data representing the physical placement of various devices in the hardware model.
- the data representing the hardware model may be the data specifying the presence or absence of various features on different mask layers for masks used to produce the integrated circuit.
- the data may be stored in any form of a machine readable medium.
- a memory or a magnetic or optical storage such as a disc may be the machine readable medium to store information transmitted via optical or electrical wave modulated or otherwise generated to transmit such information.
- an electrical carrier wave indicating or carrying the code or design is transmitted, to the extent that coDvins. bufferins. or re-transmission of the electrical signal is performed, a new copy is made.
- a communication provider or a network provider may store on a tangible, machine-readable medium, at least temporarily, an article, such as information encoded into a carrier wave, embodying techniques of embodiments of the present invention.
- a module as used herein refers to any combination of hardware, software, and/or firmware.
- a module includes hardware, such as a micro-controller, associated with a non-transitory medium to store code adapted to be executed by the micro-controller. Therefore, reference to a module, in one embodiment, refers to the hardware, which is specifically configured to recognize and/or execute the code to be held on a non-transitory medium. Furthermore, in another embodiment, use of a module refers to the non-transitory medium including the code, which is specifically adapted to be executed by the
- module in this example, may refer to the combination of the microcontroller and the non-transitory medium. Often module boundaries that are illustrated as separate commonly vary and potentially overlap. For example, a first and a second module may share hardware, software, firmware, or a combination thereof, while potentially retaining some independent hardware, software, or firmware.
- use of the term logic includes hardware, such as transistors, registers, or other hardware, such as programmable logic devices.
- Use of the phrase 'configured to,' in one embodiment, refers to arranging, putting together, manufacturing, offering to sell, importing and/or designing an apparatus, hardware, logic, or element to perform a designated or determined task.
- an apparatus or element thereof that is not operating is still 'configured to' perform a designated task if it is designed, coupled, and/or interconnected to perform said designated task.
- a logic gate may provide a 0 or a 1 during operation.
- a logic gate 'configured to' provide an enable signal to a clock does not include every potential logic gate that may provide a 1 or 0. Instead, the logic gate is one coupled in some manner that during operation the 1 or 0 output is to enable the clock. Note once again that use of the term
- 'configured to' does not require operation, but instead focus on the latent state of an apparatus, hardware, and/or element, where in the latent state the apparatus, hardware, and/or element is designed to perform a particular task when the apparatus, hardware, and/or element is operating.
- use of the phrases 'to,' 'capable of/to,' and or 'operable to,' in one embodiment refers to some apparatus, logic, hardware, and/or element designed in such a wav to enable use of the aDparatus, logic, hardware, and/or element in a specified manner.
- use of to, capable to, or operable to, in one embodiment refers to the latent state of an apparatus, logic, hardware, and/or element, where the apparatus, logic, hardware, and/or element is not operating but is designed in such a manner to enable use of an apparatus in a specified manner.
- a value includes any known representation of a number, a state, a logical state, or a binary logical state. Often, the use of logic levels, logic values, or logical values is also referred to as l's and 0's, which simply represents binary logic states. For example, a 1 refers to a high logic level and 0 refers to a low logic level.
- a storage cell such as a transistor or flash cell, may be capable of holding a single logical value or multiple logical values.
- the decimal number ten may also be represented as a binary value of 1010 and a hexadecimal letter A. Therefore, a value includes any known representation of a number, a state, a logical state, or a binary logical state. Often, the use of logic levels, logic values, or logical values is also referred to as l's and 0's, which simply represents binary logic states. For example, a 1 refers to a high logic level and 0 refers to a low logic level
- states may be represented by values or portions of values.
- a first value such as a logical one
- a second value such as a logical zero
- reset and set in one embodiment, refer to a default and an updated value or state, respectively.
- a default value potentially includes a high logical value, i.e. reset
- an updated value potentially includes a low logical value, i.e. set.
- any combination of values may be utilized to represent any number of states.
- a non-transitory machine-accessible/readable medium includes any mechanism that provides (i.e., stores and/or transmits) information in a form readable by a machine, such as a computer or electronic system.
- a non-transitory machine- accessible medium includes random-access memory (RAM), such as static RAM (SRAM) or dynamic RAM (DRAM); ROM; magnetic or optical storage medium; flash memory devices; electrical storage devices; optical storage devices; acoustical storage devices; other form of storage devices for holding information received from transitory (propagated) signals (e.g., carrier waves, infrared signals, digital signals); etc., which are to be distinguished from the non-transitory mediums that may receive information there from.
- RAM random-access memory
- SRAM static RAM
- DRAM dynamic RAM
- ROM magnetic or optical storage medium
- flash memory devices electrical storage devices
- optical storage devices e.g., optical storage devices
- acoustical storage devices other form of storage devices for holding information received from transitory (propagated) signals (e.g., carrier waves, infrared signals, digital signals); etc., which are to be distinguished from the non-transitory mediums that may receive information there from.
- Instructions used to program logic to perform embodiments of the invention may be stored within a memorv in the system, such as DRAM, cache, flash memory, or other storage. Furthermore, the instructions can be distributed via a network or by way of other computer readable media.
- a machine-readable medium may include any mechanism for storing or transmitting information in a form readable by a machine (e.g., a computer), but is not limited to, floppy diskettes, optical disks, Compact Disc, Read-Only Memory (CD-ROMs), and magneto-optical disks, Read-Only Memory (ROMs), Random Access Memory (RAM), Erasable Programmable Read-Only Memory (EPROM), Electrically Erasable Programmable Read-Only Memory (EEPROM), magnetic or optical cards, flash memory, or a tangible, machine-readable storage used in the transmission of information over the Internet via electrical, optical, acoustical or other forms of propagated signals (e.g., carrier waves, infrared signals, digital signals, etc.).
- the computer-readable medium includes any type of tangible machine-readable medium suitable for storing or transmitting electronic instructions or information in a form readable by a machine (e.g., a computer)
- Dhvsical quantities usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, transferred, combined, compared and otherwise manipulated. It has proven convenient at times, principally for reasons of common usage, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers or the like.
- the blocks described herein can be hardware, software, firmware or a combination thereof.
- example or “exemplary” are used herein to mean serving as an example, instance or illustration. Any aspect or design described herein as “example' or “exemplary” is not necessarily to be construed as preferred or advantageous over other aspects or designs. Rather, use of the words “example” or “exemplary” is intended to present concepts in a concrete fashion.
- the term “or” is intended to mean an inclusive “or” rather than an exclusive “or.” That is, unless specified otherwise, or clear from context, "X includes A or B” is intended to mean any of the natural inclusive permutations. That is, if X includes A; X includes B; or X includes both A and B, then "X includes A or B" is satisfied under any of the foregoing instances.
Abstract
Description
Claims
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US10191791B2 (en) | 2016-07-02 | 2019-01-29 | Intel Corporation | Enhanced address space layout randomization |
US10540261B2 (en) | 2017-04-07 | 2020-01-21 | International Business Machines Corporation | Problem diagnosis technique of memory corruption based on regular expression generated during application compiling |
CN108038014B (en) * | 2017-11-30 | 2021-06-04 | 中国人民解放军国防科技大学 | Image compression multi-core parallel fault-tolerant method, computer and processor |
EP3502898A1 (en) * | 2017-12-20 | 2019-06-26 | Vestel Elektronik Sanayi ve Ticaret A.S. | Devices and methods for determining possible corruption of data stored in a memory of an electronic device |
US20230044942A1 (en) * | 2021-08-03 | 2023-02-09 | Kioxia Corporation | Conditional update, delayed lookup |
US11467970B1 (en) | 2021-08-03 | 2022-10-11 | Kioxia Corporation | Metadata management in non-volatile memory devices using in-memory journal |
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GB9323096D0 (en) * | 1993-11-09 | 1994-01-05 | Lucas Ind Plc | Memory device,manufacture of such a device and a method of simulating a contiguous memory |
JP2001273794A (en) * | 2000-03-28 | 2001-10-05 | Ando Electric Co Ltd | Pre-fail information obtaining circuit, and its obtaining method |
US7930491B1 (en) * | 2004-04-19 | 2011-04-19 | Cisco Technology, Inc. | Memory corruption detection system and method using contingency analysis regulation |
CN101814324A (en) * | 2009-02-23 | 2010-08-25 | 南亚科技股份有限公司 | Method for reducing leakage current of memory and memory access method |
US8621337B1 (en) * | 2010-09-30 | 2013-12-31 | Juniper Networks, Inc. | Detecting memory corruption |
US8549379B2 (en) * | 2010-11-19 | 2013-10-01 | Xilinx, Inc. | Classifying a criticality of a soft error and mitigating the soft error based on the criticality |
US8930657B2 (en) * | 2011-07-18 | 2015-01-06 | Infineon Technologies Ag | Method and apparatus for realtime detection of heap memory corruption by buffer overruns |
US8751736B2 (en) * | 2011-08-02 | 2014-06-10 | Oracle International Corporation | Instructions to set and read memory version information |
KR20130078973A (en) * | 2012-01-02 | 2013-07-10 | 삼성전자주식회사 | Method for managing bed storage space in memory device and storage device using method thereof |
US10123187B2 (en) * | 2012-04-17 | 2018-11-06 | Qualcomm Incorporated | Methods and apparatus for multiplexing application identifiers for peer-to-peer discovery systems |
US9043559B2 (en) * | 2012-10-23 | 2015-05-26 | Oracle International Corporation | Block memory engine with memory corruption detection |
CN103839591A (en) * | 2014-03-05 | 2014-06-04 | 福州瑞芯微电子有限公司 | Automatic fault detection and fault-tolerant circuit of memory as well as control method |
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