CN108038014B - Image compression multi-core parallel fault-tolerant method, computer and processor - Google Patents
Image compression multi-core parallel fault-tolerant method, computer and processor Download PDFInfo
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- G06—COMPUTING; CALCULATING OR COUNTING
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- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0706—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment
- G06F11/0721—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU]
- G06F11/0724—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation the processing taking place on a specific hardware platform or in a specific software environment within a central processing unit [CPU] in a multiprocessor or a multi-core unit
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/0703—Error or fault processing not based on redundancy, i.e. by taking additional measures to deal with the error or fault not making use of redundancy in operation, in hardware, or in data representation
- G06F11/0793—Remedial or corrective actions
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
- G06T1/00—General purpose image data processing
- G06T1/20—Processor architectures; Processor configuration, e.g. pipelining
Abstract
The invention belongs to the technical field of hardware transient fault detection and repair, and discloses an image compression multi-core parallel fault-tolerant method, a computer and a processor, wherein an image parallel compression module is constructed, and a single-core image processing program is used for transplanting and optimizing on a multi-core processor; determining a non-binding asynchronous redundancy fault-tolerant model according to the existing core-level redundancy fault-tolerant characteristics; and adding a redundancy fault-tolerant function into the image compression system by combining an image parallel compression module according to the unbound asynchronous redundancy fault-tolerant model. The invention realizes the parallel work of multiple cores in the main core design management layer, and can be flexibly and conveniently transplanted to different hardware; the situations that a core is idle and waits for data transmission and the comparison is finished in synchronous redundant fault tolerance are avoided; performing calculation twice and then comparing results; the extra expense caused by data transmission is avoided, and the memory access pressure of the system can be reduced because the two operations are not overlapped in time.
Description
Technical Field
The invention belongs to the technical field of hardware transient fault detection and repair, and particularly relates to an image compression multi-core parallel fault-tolerant method, a computer and a processor.
Background
The space detection activity investment is large, the risk is high, and the calculation reliability is extremely high. The main factor affecting the safety of space detectors is the radiation of cosmic rays, because there are a lot of high energy particles including electrons, protons, particles and heavy ions in the cosmic environment, and when the cosmic rays composed of these particles bombard the semiconductor circuits of space computers, the transient change of the stored charge in the PN structure may occur, and this transient fault is also commonly referred to as single Event effect (see). Although the single event effect generally does not cause permanent damage to hardware equipment, the normal operation of the system can be affected by changing transmission signals, storage unit values and other modes, and even the system is crashed when the system is serious, so that the single event effect is one of the most main threats faced by the aerospace computer. Modern processors gradually adopt deep submicron manufacturing processes, the performance of the modern processors is greatly improved, the processors become more and more sensitive to various noise interferences which can cause transient faults, and meanwhile, the number of transistors integrated by a single chip is exponentially increased, so that the overall transient fault rate of the chip is rapidly increased. Currently, processor reliability issues caused by transient faults have become an increasingly hot spot of interest in the industry, following performance and power consumption. The concrete representation of the influence of the hardware transient fault on the system reliability can be divided into data flow errors and control flow errors. Data stream errors mainly refer to data and the like in registers and memories used by application programs and affected by faults; the control flow error means that a fault changes a normal execution track of a program, for example, a storage instruction is tampered into a branch instruction by an SEE, a target address of an unconditional jump instruction is temporarily modified in a space environment by a transient fault, and in order to prevent the influence of space radiation, an aerospace computer generally uses an anti-radiation device which is designed and processed by a special hardware process. The radiation-resistant device realizes fault tolerance through hardware redundancy, has high reliability, and can effectively solve the problem of hardware transient fault caused by space radiation. However, The anti-radiation device is very complex in design, long in development period, small in industrial scale and production, very expensive, and generally has performance behind that of Commercial Off-The-Shelf (COTS) of The same era for many generations. In general, the implementation cost is too high for fault tolerance technology based on hardware implementation, or the hardware architecture needs to be modified, or special equipment with error detection capability needs to be developed and configured. For data stream errors, a current software fault-tolerant method generally inserts a redundant thread into a normal instruction stream of a program at an instruction granularity or a long check point granularity to realize redundant computation of program instructions so as to ensure the correctness of the data stream. One thread is an instruction sequence which is sequentially executed in sequence, the operation steps from a previous node to a next node in the image compression program are included, the result comparison step is added after the main thread and the redundant thread finish the calculation, if the detection is passed, the current node state is stored, and the processing flow of the next node is entered; if the detection fails, the backup data of the previous node is loaded, and the operation process of the node is executed again. At present, a software-implemented unbounded asynchronous redundancy fault-tolerant model includes forms of single-core multithreading, multi-core single-thread and the like from the hardware perspective; the original data input of the node comprises direct copy transfer, buffer sharing, shared memory and the like; outputting and comparing the instruction granularity and the long check point instruction granularity; the relationship between the thread and the core comprises the forms of gold-Tai binding, dynamic binding and the like. However, in general, several unbounded asynchronous redundancy fault-tolerant models of the mainstream mainly use a main core and a redundant core to synchronously execute an operation based on a data stream error detection method implemented by software. In the synchronous non-binding asynchronous redundancy fault-tolerant model, between every two check points, redundancy result data transmission needs to be carried out between a redundancy core and a main core, and the main core carries out comparison operation once. In the two-step flow, for the master core and the slave core, one core is in an idle waiting state in the period, the utilization rate of hardware performance is not high, and performance waste is caused. Therefore, through a multi-task allocation scheduling mechanism, a non-binding asynchronous redundancy fault-tolerant model is designed to solve the problem of low hardware performance utilization rate in synchronous redundancy fault tolerance, and the core-level redundancy fault tolerance can be realized under any core quantity. Especially, the core-level redundancy fault tolerance mainly has the following problems at present: (1) the existence of idle in redundancy results in wasted performance: a core which completes a calculation task between the main core and the redundant core needs to wait for the completion of another core; (2) performance waste exists during result verification: when the main core executes the result checking operation, the redundant core needs to be idle to wait for the result checking operation to be completed, so that performance waste is caused; (3) the binding mechanism between the main core and the redundant core is not flexible: no matter static binding or dynamic binding, the main core and the redundant core work in pairs, which is not flexible enough, inconvenient to expand and not suitable for the working state of the odd cores.
In summary, the problems of the prior art are as follows: the existing core-level redundancy fault tolerance has idle redundancy, so that the performance is wasted; performance waste exists during result verification; the binding mechanism between the main core and the redundant core is not flexible. The main reason for the problem is that the previously adopted multi-core parallel mechanism cannot completely meet the fault-tolerant requirement, and a suitable multi-core parallel system meeting the fault-tolerant requirement needs to be designed by selecting a proper multi-combination parallel mechanism.
Disclosure of Invention
Aiming at the problems in the prior art, the invention provides an image compression multi-core parallel fault-tolerant method, a computer and a processor.
The invention is realized in such a way, the image compression multi-core parallel fault-tolerant method constructs an image parallel compression module, and a single-core image processing program is used for transplanting and optimizing on a multi-core processor; determining a non-binding asynchronous redundancy fault-tolerant model according to the existing core-level redundancy fault-tolerant characteristics; the invention relates to an image compression multi-core parallel fault-tolerant method, which is characterized in that a redundancy fault-tolerant function is added into an image compression system according to a non-binding asynchronous redundancy fault-tolerant model and by combining an image parallel compression module, so that the occurrence of core idle states is reduced, the utilization rate of hardware resources is improved, and the flexibility of the whole system is enhanced to adapt to the operation requirements under different environments; the fault-tolerant function has strong expansibility and portability, and can be simplified or expanded on the basis of the following description according to one of the most common application scenarios.
Further, the image compression multi-core parallel fault-tolerant method comprises the following steps:
determining an image compression parallelization module based on a multi-core DSP;
secondly, performing fault-tolerant design based on a parallel image compression module, and determining an asynchronous non-binding asynchronous redundancy fault-tolerant model NBAR;
and step three, adjusting the original parallel image compression system according to the designed unbound asynchronous redundancy fault-tolerant model, and adding a fault-tolerant function.
Further, the first step specifically includes:
(1) the method comprises the following steps of (1) stripping external data of a single-core image processing program from a control interaction function (a solid line frame part) and a compression function (a dashed line frame part);
(2) the management layer runs on a single main core, improves and optimizes an external control and data information interaction function in an original single-core program to adapt to a multi-core hardware environment and manages the compression slave cores, the compression layer runs on a plurality of compression slave cores, and the compression function can realize an image compression task without adjusting the compression function; through adjustment of a system model and a framework and improvement of original functions and functions, the compression system can smoothly run in a multi-core environment, interaction with external data and control information is completed in a software updating mode on the basis of avoiding modification of other external hardware equipment to the maximum extent, and an image compression task is completed by fully utilizing multi-core hardware resources.
(3) And adding and optimizing a management function of the management layer to the compression layer and a response function of the compression layer to ensure that bottleneck is not generated inside the management layer and the compression layer to influence the performance of the whole system.
Further, the second step specifically includes:
(1) analyzing an existing unbound asynchronous redundancy fault-tolerant model;
(2) determining an asynchronous unbundled asynchronous redundancy fault-tolerant model;
(3) and integrating the dual-mode redundancy model and the triple-mode redundancy model to optimize the asynchronous non-binding asynchronous redundancy fault-tolerant model.
Further, the third step specifically includes:
(1) determining a fault-tolerant function according to the unbound asynchronous redundancy fault-tolerant model;
(2) carrying out fault-tolerant adaptability adjustment on the original parallel image compression system;
(3) the fault-tolerant function is added to the original parallel image compression system.
Fault tolerance function: and the compression system realizes the fault-tolerant function based on the asynchronous non-binding asynchronous redundancy fault-tolerant model designed in the step two. The main realization principle is that a management layer copies an image compression instruction, sends the image compression instruction for multiple times and repeatedly sends the image compression instruction to different compression layer cores, no binding relation exists between the image compression instruction and the compression layer cores and between the compression layer cores receiving the image compression instruction, the image compression instruction is asynchronously executed by the compression layer cores, image compression result comparison is carried out after the image compression instructions are completely finished for multiple times, if the results are consistent, a plurality of image compression instructions are bundled into a single instruction to enter the next link, and if not, the image compression instructions return to the starting point of the link. Therefore, the system fault tolerance function is realized.
Furthermore, the image parallel compression module comprises a management layer and a compression layer which share a memory area;
the management layer performs control and data information interaction with the outside and sends an instruction to the compression layer through a control instruction;
after receiving the instruction, the compression layer calculates a calculation area on the memory area by decoding the control instruction, executes a compression program on the image of the area, and informs the management layer of completing the task after the completion of the compression program, and the management layer completes the subsequent flow.
Further, the unbundling asynchronous redundancy fault-tolerant model comprises:
inputting, inheriting the result of the previous node as the to-be-processed data of the stage, wherein the result is also a fault-tolerant recovery node;
step two, processing, namely performing data processing work of crash, wherein the processing can be performed for 2 to 3 times according to the condition of a comparison process;
thirdly, comparing, namely comparing the results obtained by processing, and selecting direct output or adding third processing or returning to the last input node;
and fourthly, outputting and outputting a detection result.
Another object of the present invention is to provide a computer using the image compression multi-core parallel fault-tolerant method.
Another object of the present invention is to provide a processor using the image compression multi-core parallel fault-tolerant method.
Compared with the existing core-level redundancy fault-tolerant method, the method has the following advantages:
(1) the invention is a pure software method, and does not need to modify the hardware of a bottom layer machine; the invention realizes the parallel work of multiple cores in the main core design management layer, and can be flexibly and conveniently transplanted to different hardware.
(2) The Non-binding Asynchronous Redundancy (NBAR) fault-tolerant model in the invention adopts an Asynchronous Redundancy fault-tolerant flow to asynchronously execute the Redundancy calculation and the first calculation. The operation of each step is executed by the newly applied core, and is released immediately after the operation is finished, so that the operation of other cores is not required to be finished, and the first operation and the core for redundant operation do not have a binding relationship; and each step of flow has no data interactive operation with the former and latter flows, the redundancy operation between every two check points is logically kept in parallel, and the synchronous operation is carried out asynchronously in a serial mode in actual operation, so that the situations that a core is idle to wait for data transmission and the comparison is finished in synchronous redundancy fault tolerance are avoided.
(3) The NBAR redundancy mode combines the characteristics of dual-mode redundancy and triple-mode redundancy, firstly, dual-mode redundancy is realized, namely, the results are compared after two times of calculation, and if the results are consistent, one complete operation is completed; if the comparison results are inconsistent, switching to a triple modular redundancy mode, adding a redundancy calculation, then carrying out result comparison again, if the results are consistent, completing a complete operation, and if the results are inconsistent, returning to the previous operation node.
(4) The input of the NBAR adopts a shared storage form, when the first operation and the redundant operation are carried out, the core directly accesses the same address data so as to avoid the extra overhead caused by data transmission, and the memory access pressure of the system can be reduced because the two operations are not overlapped in time. For the output comparison part of NBAR, since the operation result is not processed as soon as possible in the first time, the result is temporarily stored in the memory until the comparison result is output as consistent or discarded as inconsistent. Therefore, NBAR requires a larger memory space to store relatively more temporary result data.
Drawings
Fig. 1 is a flowchart of an image compression multi-core parallel fault-tolerant method according to an embodiment of the present invention.
Fig. 2 is a schematic diagram of an image parallel compression system according to an embodiment of the present invention.
FIG. 3 is a schematic diagram of an unbundled asynchronous redundancy fault tolerance model according to an embodiment of the present invention.
Fig. 4 is a schematic diagram of a non-binding asynchronous redundancy fault-tolerant flow provided by an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the present invention is further described in detail with reference to the following embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.
The history of computer development shows that many methods originally realized by hardware can also be realized by software, and on a COTS microprocessor, the defect of the fault-tolerant capability of a COTS device can be made up by realizing a software fault-tolerant technology oriented to hardware transient faults. Many experimental studies have been carried out at home and abroad to apply the COTS processor in the space environment, and the results show that: the software fault-tolerant method for hardware faults can effectively improve the reliability of a space computer based on a COTS device, can well cope with the influence of space radiation, and simultaneously, the performance of the COTS device realized by the software fault-tolerant method can be one order of magnitude higher than that of an anti-irradiation device, while the cost is reduced by one order of magnitude. Therefore, with the great abundance of computer hardware resources, it has become possible to trade off partial performance for higher reliability, and the software fault-tolerant method has great advantages in terms of cost, power consumption and flexibility.
The following detailed description of the principles of the invention is provided in connection with the accompanying drawings.
The image compression multi-core parallel fault-tolerant method provided by the embodiment of the invention is designed and realized on a hardware platform taking a C6678 multi-core DSP of TMS320 series of Texas instruments as a core, the hardware platform uses PowerPC as an upper computer of the multi-core DSP to provide original image data for the multi-core DSP, receives, temporarily stores and outputs an image compression result, and simultaneously uses an FPGA chip as an auxiliary control chip of the hardware platform to complete other auxiliary functions in the chip selection and compression process of a system circuit.
As shown in fig. 1, the image compression multi-core parallel fault-tolerant method provided by the embodiment of the present invention includes the following steps:
s101: determining an image compression parallelization module based on a multi-core DSP aiming at a multi-core processor;
s102: performing fault-tolerant design based on a parallel image compression module, and determining an asynchronous non-binding asynchronous redundancy fault-tolerant model;
s103: and adjusting the original parallel image compression system according to the designed unbound asynchronous redundant fault-tolerant model, and adding a fault-tolerant function.
In a preferred embodiment of the present invention, step S101 specifically includes:
(1) separating the external data and the control interaction function of the single-core image processing program from the compression function;
(2) designing a management layer and a compression layer, wherein the management layer runs on a single main core of C6678, improves and optimizes an external control and data information interaction function in an original single-core program to adapt to interaction requirements of C6678 and PowerPC under a multi-core hardware environment, and manages compression slave cores, the compression layer runs on a plurality of compression slave cores of C6678, and the compression function can realize an image compression task without adjustment on a compression function; (3) and a management function of the management layer and a response function of the compression layer are added and optimized, so that the bottleneck generated inside the C6678 management layer and the compression layer is prevented from influencing the overall system performance.
In a preferred embodiment of the present invention, step S102 specifically includes:
(1) analyzing the existing unbound asynchronous redundancy fault-tolerant model, summarizing and inducing the characteristics and development trend of the existing unbound asynchronous redundancy fault-tolerant model;
(2) designing an asynchronous non-binding asynchronous redundancy fault-tolerant model according to the actual requirements of an application scene;
(3) optimizing an asynchronous non-binding asynchronous redundancy fault-tolerant model, and fusing the characteristics of a dual-mode redundancy model and a triple-mode redundancy model;
in a preferred embodiment of the present invention, step S103 specifically includes:
(1) designing a fault-tolerant function according to the designed unbound asynchronous redundancy fault-tolerant model;
(2) carrying out fault-tolerant adaptability adjustment on the original parallel image compression system;
(3) the fault-tolerant function is added to the original parallel image compression system.
The application of the principles of the present invention will now be described in further detail with reference to the accompanying drawings.
As shown in fig. 2, the image parallel compression module includes two layers, i.e., a management layer and a compression layer, which share a memory area, the management layer performs control and data information interaction with the outside, sends an instruction to the compression layer via a control instruction, the compression layer receives the instruction, then decodes the control instruction to calculate a calculation area on the memory area, executes a compression program on an image in the area, and then notifies the management layer of completion of a task, and the management layer completes a subsequent process.
The optimization and improvement of external control and data information interaction functions mainly aim at functions ask New Img () and return result () in a single-core environment, and because only one image is processed at a time, the two functions in the single-core environment only have the functions of simply requesting a new original image and returning a compression result, and when waiting for data input and output, a core is in an idle waiting state. In a multi-core environment, because the sequence of the original image input and the compression result is not in one-to-one correspondence, and a plurality of buffer areas are used for temporarily storing the image and the result data, the function ask New Img () needs to record the corresponding relation between the input original image and the buffer areas and tends to fill all empty buffer areas, the return result () needs to add image number information into output information according to the corresponding relation when returning the compression result, and simultaneously, the buffer areas, the related areas and the flag bit cleaning work are well done, and the compression result tends to be completely transmitted. The two functions run in the management layer, and when the two functions are executed, the operation of the compression layer is not influenced.
As shown in FIG. 3, the unbundled asynchronous redundancy fault tolerance model includes the following 4 stages:
the first step is to input and inherit the result of the previous node as the data to be processed in the stage, which is also a fault-tolerant recovery node.
And in the second step, processing, namely performing the data processing work of crash, wherein the processing is performed for 2 to 3 times according to the condition of the comparison process.
And thirdly, comparing, namely comparing the results obtained by processing, and selecting to directly output or add third processing or return to the last input node.
And fourthly, outputting and outputting a detection result.
As shown in fig. 4, the original parallel image compression module is a schematic flow diagram after adding a fault-tolerant function according to an unbundled asynchronous redundancy fault-tolerant model.
And each budget, including data processing and result comparison, is executed by the management layer by selecting the idle compression slave core of the compression layer, and the compression slave core is released immediately after completing the distributed task to wait for the next task distribution.
Firstly, carrying out primary operation, then sequentially carrying out redundancy operation and result comparison, and entering a next check point or adding additional redundancy operation or adding additional result comparison according to a result comparison result.
The above description is only for the purpose of illustrating the preferred embodiments of the present invention and is not to be construed as limiting the invention, and any modifications, equivalents and improvements made within the spirit and principle of the present invention are intended to be included within the scope of the present invention.
Claims (9)
1. The image compression multi-core parallel fault-tolerant method is characterized in that an image compression multi-core parallel fault-tolerant method constructs an image parallel compression module, and a single-core image processing program is used for transplanting and optimizing on a multi-core processor; determining a non-binding asynchronous redundancy fault-tolerant model according to the existing core-level redundancy fault-tolerant characteristics; according to the unbound asynchronous redundancy fault-tolerant model, a redundancy fault-tolerant function is added into an image compression system by combining an image parallel compression module;
the redundancy fault-tolerant function is that the management layer copies an image compression instruction, sends the image compression instruction for multiple times and repeatedly sends the image compression instruction to different compression layer cores, binding relations do not exist between the image compression instruction and the compression layer cores and between the compression layer cores receiving the image compression instruction, the image compression instruction is asynchronously executed by the compression layer cores, image compression result comparison is carried out after the image compression instructions are completely finished for multiple times, if the results are consistent, a plurality of image compression instructions are converged into a single instruction to enter the next link, and if not, the image compression instructions return to the starting point of the link.
2. The image compression multi-core parallel fault tolerant method according to claim 1, comprising the steps of:
determining an image compression parallelization module based on a multi-core DSP;
secondly, performing fault-tolerant design based on a parallel image compression module, and determining an asynchronous non-binding asynchronous redundancy fault-tolerant model;
and step three, adjusting the original parallel image compression system according to the designed unbound asynchronous redundancy fault-tolerant model, and adding a fault-tolerant function.
3. The image compression multi-core parallel fault-tolerant method according to claim 2, wherein the first step specifically comprises:
(1) separating the external data and the control interaction function of the single-core image processing program from the compression function;
(2) the management layer runs on a single main core, exchanges external control and data information and manages the compression slave cores, and the compression layer runs on a plurality of compression slave cores to realize an image compression task;
(3) and adding and optimizing a management function of a management layer to ensure that the whole system performance is not influenced by the bottleneck generated in the management layer.
4. The image compression multi-core parallel fault-tolerant method according to claim 2, wherein the second step specifically comprises:
(1) analyzing an existing unbound asynchronous redundancy fault-tolerant model;
(2) determining an asynchronous unbundled asynchronous redundancy fault-tolerant model;
(3) and integrating the dual-mode redundancy model and the triple-mode redundancy model to optimize the asynchronous non-binding asynchronous redundancy fault-tolerant model.
5. The image compression multi-core parallel fault-tolerant method according to claim 2, wherein the third step specifically comprises:
(1) determining a fault-tolerant function according to the unbound asynchronous redundancy fault-tolerant model;
(2) carrying out fault-tolerant adaptability adjustment on the original parallel image compression system;
(3) the fault-tolerant function is added to the original parallel image compression system.
6. The image compression multi-core parallel fault-tolerant method of claim 1, wherein the image parallel compression module comprises two layers, namely a management layer and a compression layer, which share a memory area;
the management layer performs control and data information interaction with the outside and sends an instruction to the compression layer through a control instruction;
after receiving the instruction, the compression layer calculates a calculation area on the memory area by decoding the control instruction, executes a compression program on the image of the area, and informs the management layer of completing the task after the completion of the compression program, and the management layer completes the subsequent flow.
7. The image compression multi-core parallel fault-tolerant method of claim 1, wherein the unbundled asynchronous redundancy fault-tolerant model comprises:
inputting, inheriting the result of the previous node as the to-be-processed data of the stage, wherein the result is also a fault-tolerant recovery node;
step two, processing, namely performing data processing work of crash, wherein the processing can be performed for 2 to 3 times according to the condition of a comparison process;
thirdly, comparing, namely comparing the results obtained by processing, and selecting direct output or adding third processing or returning to the last input node;
and fourthly, outputting and outputting a detection result.
8. A computer using the image compression multi-core parallel fault-tolerant method according to any one of claims 1 to 7.
9. A processor using the image compression multi-core parallel fault-tolerant method of any one of claims 1 to 7.
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