EP3255553A4 - Transmission control method and device for direct memory access - Google Patents

Transmission control method and device for direct memory access Download PDF

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Publication number
EP3255553A4
EP3255553A4 EP16817186.6A EP16817186A EP3255553A4 EP 3255553 A4 EP3255553 A4 EP 3255553A4 EP 16817186 A EP16817186 A EP 16817186A EP 3255553 A4 EP3255553 A4 EP 3255553A4
Authority
EP
European Patent Office
Prior art keywords
control method
transmission control
memory access
direct memory
direct
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP16817186.6A
Other languages
German (de)
French (fr)
Other versions
EP3255553B1 (en
EP3255553A1 (en
Inventor
Hao Chen
Huifeng XU
Haitao Guo
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Huawei Technologies Co Ltd
Original Assignee
Huawei Technologies Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Huawei Technologies Co Ltd filed Critical Huawei Technologies Co Ltd
Publication of EP3255553A1 publication Critical patent/EP3255553A1/en
Publication of EP3255553A4 publication Critical patent/EP3255553A4/en
Application granted granted Critical
Publication of EP3255553B1 publication Critical patent/EP3255553B1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
    • G06F13/30—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal with priority control
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/74—Selecting or encoding within a word the position of one or more bits having a specified value, e.g. most or least significant one or zero detection, priority encoders
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
    • G06F7/78—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data for changing the order of data flow, e.g. matrix transposition or LIFO buffers; Overflow or underflow handling therefor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
    • G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
    • G06F9/5038—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering the execution order of a plurality of tasks, e.g. taking priority or time dependency constraints into consideration
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/28—DMA
    • G06F2213/2802—DMA using DMA transfer descriptors
EP16817186.6A 2015-06-29 2016-06-22 Transmission control method and device for direct memory access Active EP3255553B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201510372004.7A CN106294233B (en) 2015-06-29 2015-06-29 A kind of transfer control method and device of direct memory access
PCT/CN2016/086758 WO2017000822A1 (en) 2015-06-29 2016-06-22 Transmission control method and device for direct memory access

Publications (3)

Publication Number Publication Date
EP3255553A1 EP3255553A1 (en) 2017-12-13
EP3255553A4 true EP3255553A4 (en) 2018-01-24
EP3255553B1 EP3255553B1 (en) 2019-02-06

Family

ID=57607860

Family Applications (1)

Application Number Title Priority Date Filing Date
EP16817186.6A Active EP3255553B1 (en) 2015-06-29 2016-06-22 Transmission control method and device for direct memory access

Country Status (4)

Country Link
US (1) US10120820B2 (en)
EP (1) EP3255553B1 (en)
CN (1) CN106294233B (en)
WO (1) WO2017000822A1 (en)

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KR102447465B1 (en) * 2017-09-08 2022-09-27 삼성전자주식회사 Storage device temporarily suspending internal operation to provide short read response time for read request from host
CN109727114A (en) * 2018-05-14 2019-05-07 网联清算有限公司 Method for processing business and system
CN109379296A (en) * 2018-10-25 2019-02-22 盛科网络（苏州）有限公司 A kind of chip realizes the method and device of upper CPU protocol massages stratification flow control
CN111240813A (en) * 2018-11-29 2020-06-05 杭州嘉楠耘智信息科技有限公司 DMA scheduling method, device and computer readable storage medium
CN109857686B (en) * 2019-03-26 2020-12-29 北京简约纳电子有限公司 Method for converting synchronous transmission of DMA data into asynchronous transmission
CN110532205B (en) * 2019-07-17 2021-04-06 浙江大华技术股份有限公司 Data transmission method, data transmission device, computer equipment and computer readable storage medium
US11099966B2 (en) * 2020-01-09 2021-08-24 International Business Machines Corporation Efficient generation of instrumentation data for direct memory access operations
CN112286856B (en) * 2020-10-29 2023-03-14 维沃移动通信有限公司 Control method and electronic device
CN113709056B (en) * 2021-08-26 2022-09-09 无锡沐创集成电路设计有限公司 Memory flow control method and device, storage medium and electronic equipment
CN114124690A (en) * 2021-08-30 2022-03-01 济南浪潮数据技术有限公司 Alarm configuration method, system and related device for data center
CN115563038B (en) * 2022-10-24 2023-11-07 苏州雄立科技有限公司 Data processing system, method and data processing equipment based on DMA controller
CN116756066B (en) * 2023-08-21 2024-01-02 北京紫光芯能科技有限公司 Direct memory access control method and controller

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US20140325114A1 (en) * 2013-04-26 2014-10-30 Core Logic Inc. Multi-channel direct memory access controller and control method thereof

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GB2283596B (en) * 1993-11-01 1998-07-01 Ericsson Ge Mobile Communicat Multiprocessor data memory sharing
JPH1040211A (en) * 1996-04-30 1998-02-13 Texas Instr Inc <Ti> Method for directly assigning memory access priority in packeted data communication interface equipment and dma channel circuit
JP2003006003A (en) * 2001-06-18 2003-01-10 Mitsubishi Electric Corp Dma controller and semiconductor integrated circuit
US6775717B1 (en) * 2001-08-31 2004-08-10 Integrated Device Technology, Inc. Method and apparatus for reducing latency due to set up time between DMA transfers
DE102004046822A1 (en) * 2004-09-27 2006-03-30 Infineon Technologies Ag Method for transferring data between a memory and a plurality of peripheral units by means of a direct memory access control and corresponding direct memory access control device
US7546391B2 (en) * 2005-05-13 2009-06-09 Texas Instruments Incorporated Direct memory access channel controller with quick channels, event queue and active channel memory protection
US20070162643A1 (en) * 2005-12-19 2007-07-12 Ivo Tousek Fixed offset scatter/gather dma controller and method thereof
US20080126600A1 (en) * 2006-08-31 2008-05-29 Freescale Semiconductor, Inc. Direct memory access device and methods
US8516163B2 (en) * 2007-02-27 2013-08-20 Integrated Device Technology, Inc. Hardware-based concurrent direct memory access (DMA) engines on serial rapid input/output SRIO interface
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Title
See also references of WO2017000822A1 *

Also Published As

Publication number Publication date
WO2017000822A1 (en) 2017-01-05
EP3255553B1 (en) 2019-02-06
US10120820B2 (en) 2018-11-06
CN106294233A (en) 2017-01-04
EP3255553A1 (en) 2017-12-13
CN106294233B (en) 2019-05-03
US20180052789A1 (en) 2018-02-22

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