EP3159816A4 - Method and device for chip integration and storage medium - Google Patents

Method and device for chip integration and storage medium Download PDF

Info

Publication number
EP3159816A4
EP3159816A4 EP14896824.1A EP14896824A EP3159816A4 EP 3159816 A4 EP3159816 A4 EP 3159816A4 EP 14896824 A EP14896824 A EP 14896824A EP 3159816 A4 EP3159816 A4 EP 3159816A4
Authority
EP
European Patent Office
Prior art keywords
storage medium
chip integration
integration
chip
medium
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP14896824.1A
Other languages
German (de)
French (fr)
Other versions
EP3159816A1 (en
Inventor
Qing Zhang
Chongxing GAO
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanechips Technology Co Ltd
Original Assignee
Sanechips Technology Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanechips Technology Co Ltd filed Critical Sanechips Technology Co Ltd
Publication of EP3159816A1 publication Critical patent/EP3159816A1/en
Publication of EP3159816A4 publication Critical patent/EP3159816A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2111/00—Details relating to CAD techniques
    • G06F2111/04—Constraint-based CAD
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2115/00—Details relating to the type of the circuit
    • G06F2115/02—System on chip [SoC] design
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00—Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0038—System on Chip

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Stored Programmes (AREA)
EP14896824.1A 2014-06-30 2014-11-18 Method and device for chip integration and storage medium Withdrawn EP3159816A4 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CN201410309541.2A CN105278938A (en) 2014-06-30 2014-06-30 Chip integration method and apparatus
PCT/CN2014/091416 WO2016000388A1 (en) 2014-06-30 2014-11-18 Method and device for chip integration and storage medium

Publications (2)

Publication Number Publication Date
EP3159816A1 EP3159816A1 (en) 2017-04-26
EP3159816A4 true EP3159816A4 (en) 2017-07-19

Family

ID=55018388

Family Applications (1)

Application Number Title Priority Date Filing Date
EP14896824.1A Withdrawn EP3159816A4 (en) 2014-06-30 2014-11-18 Method and device for chip integration and storage medium

Country Status (6)

Country Link
US (1) US20170140087A1 (en)
EP (1) EP3159816A4 (en)
JP (1) JP6489558B2 (en)
KR (1) KR101885488B1 (en)
CN (1) CN105278938A (en)
WO (1) WO2016000388A1 (en)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110442929B (en) * 2019-07-18 2023-08-01 上海磐启微电子有限公司 Method for realizing automatic instantiation of chip system top layer based on perl
CN112528577A (en) * 2019-09-02 2021-03-19 深圳市中兴微电子技术有限公司 Management method and device of clock reset circuit and computer storage medium
CN111859827B (en) * 2020-06-29 2022-06-17 山东云海国创云计算装备产业创新中心有限公司 Chip IP integration method and device, electronic equipment and storage medium
CN112464591B (en) * 2020-11-19 2022-10-18 苏州浪潮智能科技有限公司 Multi-port nested model connection analysis method and medium
CN114510452B (en) * 2022-01-10 2024-09-03 杭州未名信科科技有限公司 SOC (system on chip) integration method and device and electronic equipment
CN114818553B (en) * 2022-05-10 2023-06-06 无锡众星微系统技术有限公司 Chip integrated design method
CN117313651B (en) * 2023-11-30 2024-02-09 沐曦集成电路(上海)有限公司 Chip function feature setting method, electronic device and medium

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US6477691B1 (en) * 2000-04-03 2002-11-05 International Business Machines Corporation Methods and arrangements for automatic synthesis of systems-on-chip
US6996799B1 (en) * 2000-08-08 2006-02-07 Mobilygen Corporation Automatic code generation for integrated circuit design

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US5960184A (en) * 1996-11-19 1999-09-28 Unisys Corporation Method and apparatus for providing optimization parameters to a logic optimizer tool
US6026220A (en) * 1996-11-19 2000-02-15 Unisys Corporation Method and apparatus for incremntally optimizing a circuit design
US6263483B1 (en) * 1998-02-20 2001-07-17 Lsi Logic Corporation Method of accessing the generic netlist created by synopsys design compilier
GB0002174D0 (en) * 2000-01-31 2000-03-22 Sgs Thomson Microelectronics Design flow checker
US6721937B2 (en) * 2000-06-06 2004-04-13 Fujitsu Network Communications, Inc. Method and system for automated processor register instantiation
GB2380818B (en) * 2001-10-06 2003-11-19 3Com Corp ASIC design technique
US7146302B2 (en) * 2003-04-28 2006-12-05 International Business Machines Corporation Method, system and program product that utilize a configuration database to configure a hardware digital system having an arbitrary system size and component set
US7168061B2 (en) * 2003-04-28 2007-01-23 International Business Machines Of Corporation Method, system and program product for implementing a read-only dial in a configuration database of a digital design
US7162404B2 (en) * 2003-04-28 2007-01-09 International Business Machines Corporation Method, system and program product for configuring a simulation model of a digital design
US7266489B2 (en) * 2003-04-28 2007-09-04 International Business Machines Corporation Method, system and program product for determining a configuration of a digital design by reference to an invertible configuration database
US7134098B2 (en) * 2003-04-28 2006-11-07 International Business Machines Corporation Method, system and program product for specifying a configuration for multiple signal or dial instances in a digital system
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US8065128B1 (en) * 2003-10-23 2011-11-22 Altera Corporation Methods and apparatus for automated testbench generation
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US6996797B1 (en) 2004-11-18 2006-02-07 International Business Machines Corporation Method for verification of resolution enhancement techniques and optical proximity correction in lithography
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CN103413796B (en) * 2013-07-16 2016-01-06 中国科学院计算技术研究所 The large port interconnection class chip that a kind of substrate multi-chip is integrated and implementation method
CN103577653A (en) * 2013-11-20 2014-02-12 中国电子科技集团公司第五十四研究所 Method for arranging large number of relevant units of chip
JP2016110205A (en) * 2014-12-02 2016-06-20 株式会社ソシオネクスト Design method and program for semiconductor device

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5892682A (en) * 1996-06-17 1999-04-06 Motorola, Inc. Method and apparatus for generating a hierarchical interconnection description of an integrated circuit design and using the description to edit the integrated circuit design
US6477691B1 (en) * 2000-04-03 2002-11-05 International Business Machines Corporation Methods and arrangements for automatic synthesis of systems-on-chip
US6996799B1 (en) * 2000-08-08 2006-02-07 Mobilygen Corporation Automatic code generation for integrated circuit design

Non-Patent Citations (3)

* Cited by examiner, † Cited by third party
Title
DEEPAK KUMAR TALA: "Verilog HDL Syntax And Semantics Part-II", 30 July 2013 (2013-07-30), pages 1 - 8, XP055377455, Retrieved from the Internet <URL:https://web.archive.org/web/20130730131652/http://www.asic-world.com/verilog/syntax2.html> [retrieved on 20170531] *
MOONEYIII V J ET AL: "Automated Bus Generation for Multiprocessor SoC Design", IEEE TRANSACTIONS ON COMPUTER AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, IEEE SERVICE CENTER, PISCATAWAY, NJ, US, vol. 23, no. 11, 11 November 2004 (2004-11-11), pages 1531 - 1549, XP011121381, ISSN: 0278-0070, DOI: 10.1109/TCAD.2004.835119 *
See also references of WO2016000388A1 *

Also Published As

Publication number Publication date
US20170140087A1 (en) 2017-05-18
KR101885488B1 (en) 2018-08-03
JP2017520062A (en) 2017-07-20
JP6489558B2 (en) 2019-03-27
CN105278938A (en) 2016-01-27
KR20170019412A (en) 2017-02-21
EP3159816A1 (en) 2017-04-26
WO2016000388A1 (en) 2016-01-07

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