Classifications

• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
  • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
  • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
  • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
  • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
  • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
  • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
  • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
  • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
  • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
  • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
  • G11C11/409—Read-write [R-W] circuits 
  • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
  • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
  • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
  • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
  • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
  • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C5/00—Details of stores covered by group G11C11/00
  • G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
  • G11C5/025—Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device
• • G—PHYSICS
  • G11—INFORMATION STORAGE
  • G11C—STATIC STORES
  • G11C5/00—Details of stores covered by group G11C11/00
  • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B10/00—Static random access memory [SRAM] devices
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10B—ELECTRONIC MEMORY DEVICES
  • H10B10/00—Static random access memory [SRAM] devices
  • H10B10/12—Static random access memory [SRAM] devices comprising a MOSFET load element

Definitions

• the present invention in some embodiments thereof, relates to a gain cell with internal feedback and, more particularly, but not exclusively, to a four-transistor gain cell with internal feedback.
• Modern microprocessors and other VLSI systems-on-chip (SoCs) implemented in aggressively scaled CMOS technologies are characterized by high leakage currents, and require an increasing amount of embedded memory [ref. 1].
• embedded memory typically implemented as 6-transistor (6T)-bitcell SRAM macrocells, not only consume an ever growing share of the total silicon area but also significantly contributes to the leakage power of the system. (The leakage power is a large share of the total power budget in deeply scaled CMOS nodes.)
• 6T SRAM bitcell is relatively large, exhibits several leakage paths, and has dramatically increased failure rates under voltage scaling.
• Gain-Cell embedded DRAM [refs. 2-5] circumvents the limitations of SRAM while remaining fully compatible with standard digital CMOS technologies. Furthermore, GC-eDRAMs exhibit low static leakage currents, are suitable for 2-port memory implementations, and provide non-ratioed circuit operation. The main drawback of GC-eDRAMs is the need for periodic, power-hungry refresh cycles to ensure data retention.
• the Data Retention Time (DRT) of GC-eDRAMs is the maximum time interval from writing a data level into the bitcell to still being able to correctly read out the written level.
• the DRT is primarily limited by the level set by the initial charge stored in the bitcell and the leakage currents that degrade this level.
• Gain cell implementations in mature technology nodes such as 180 nm, have been shown to exhibit high DRTs of tens to hundreds of milliseconds [ref. 4,5].
• conventional 2T gain cells in newer technology nodes, such as 65nm display much lower DRTs of only tens of microseconds [ref. 6].
• the lower DRT is a direct consequence of the substantially higher leakage currents which result in a much faster deterioration of the stored levels [ref. 5].
• WT write transistor
• one of the data levels has a much higher retention time than the other (e.g. data T for a PMOS WT and data '0' for a NMOS WT) [ref. 6].
• WBL write bitline
• Embodiments herein present a four-transistor gain cell, optionally for use in scaled CMOS nodes characterized by high leakage currents.
• the gain cell protects the "weak" data level with relatively fast decay by a conditional, cell-internal feedback path. The feedback is disabled for the "strong" data level with relatively slow decay.
• the feedback path is optionally implemented by a retention element which includes two switching elements.
• One switching element is controlled by the write line trigger to provide a buffer effect between the write and read transistors during data retention (standby).
• the second switching element opens a path to a constant voltage (or ground) when the "weak" data level is retained at the storage node.
• a write transistor which includes a first diffusion connection, a gate connection, and a second diffusion connection.
• the first diffusion connection is connected to the write bit line input and the gate connection is connected to the write trigger input;
• a read transistor which includes a first diffusion connection, a gate connection and a second diffusion connection.
• the first diffusion connection is connected to the read bit line output and the second diffusion connection is connected to the read trigger input;
• G a retention element associated with the write transistor and the read transistor.
• the retention element buffers between the second diffusion connection of the write transistor and the gate connection of the read transistor during data retention, connects the second diffusion connection of the write transistor to a constant voltage during retention of a first data level at the gate connection of the read transistor, and disconnects the second diffusion connection of the write transistor from the constant voltage during retention of a second data level at the gate connection of the read transistor.
• the retention element connects the second diffusion connection of the write transistor to the gate connection of the read transistor during a write bit operation, and disconnects the second diffusion connection of the write transistor from the gate connection of the read transistor during data retention.
• the retention element includes:
• A) a buffer switch having a buffer input, a buffer output and a buffer control input; and B) a feedback switch associated with the buffer switch, having a feedback input, a feedback output and a feedback control input, wherein the feedback input is connected to a constant voltage.
• the buffer input is connected to the second diffusion connection of the write transistor and to the feedback switch output.
• the buffer switch output is connected to the gate connection of the read transistor and to the feedback control input, and the write control input is connected to the write trigger input.
• the buffer switch connects the buffer input to the buffer output when the write trigger is on and disconnects the buffer input from the buffer output when the write trigger is off.
• the feedback switch connects the feedback input to the feedback output when the feedback control input is at the first data level and disconnects the feedback input from the feedback output when the feedback control input is at the second data level.
• the retention element includes:
• the first diffusion connection of the buffer transistor is connected to the second diffusion connection of the write transistor and to the second diffusion connection of the feedback transistor.
• the second diffusion connection of the buffer transistor is connected to the gate connection of the read transistor and to the gate connection of the feedback transistor.
• the feedback transistor is a p- type transistor and the constant voltage is a low data voltage level.
• the feedback transistor is an n-type transistor and the constant voltage is a high data voltage level.
• the gain cell further includes a capacitor between the gate connection of the read transistor and ground.
• a memory array which includes a plurality of gain cells as embodied herein. Respective write bit lines inputs of the gain cells are connected to form a common write bit line, and respective read bit line outputs of the gain cells are connected to form a common read bit line output.
• a write transistor comprising a first diffusion connection, a gate connection, and a second diffusion connection.
• the first diffusion connection is connected to the write bit line input and the gate connection is connected to the write trigger input;
• a read transistor comprising a first diffusion connection, a gate connection and a second diffusion connection, the first diffusion connection is connected to the read bit line output and the second diffusion connection is connected to the read trigger input;
• H a feedback transistor, having a first diffusion connection, a gate connection, and a second diffusion connection, wherein the first diffusion connection is connected to a constant voltage;
• the first diffusion connection of the buffer transistor is connected to the second diffusion connection of the write transistor and to the second diffusion connection of the feedback transistor.
• the second diffusion connection of the buffer transistor is connected to the gate connection of the read transistor and to the gate connection of the feedback transistor.
• the write transistor, the buffer transistor the feedback transistor and the read transistor are p-type transistors.
• the write transistor, the buffer transistor, the feedback transistor and the read transistor are n-type transistors.
• the write transistor, the buffer transistor and the feedback transistor are p-type transistors and the read transistor is an n-type transistor.
• the write transistor, the buffer transistor and the feedback transistor are n-type transistors and the read transistor is a p- type transistor.
• a memory array which includes a plurality of gain cells as embodied herein. Respective write bit line inputs of the gain cells are connected to form a common write bit line input, and respective read bit line outputs of the gain cells are connected to form a common read bit line output.
• a data processor such as a computing platform for executing a plurality of instructions.
• the data processor includes a volatile memory for storing instructions and/or data and/or a non- volatile storage, for example, a magnetic hard-disk and/or removable media, for storing instructions and/or data.
• a network connection is provided as well.
• a display and/or a user input device such as a keyboard or mouse are optionally provided as well.
• FIGURES 1A and IB illustrate a prior art 2T PMOS gain cell during retention of a high data level and a low data level respectively;
• FIGURE 2 shows storage node degradation of a prior art 2T PMOS gain cell following a write operation under the two worst-case biasing situations
• FIGURE 3 is a simplified block diagram of a gain cell, according to embodiments of the invention.
• FIGURE 4 is a simplified block diagram of a retention element, according to embodiments of the invention.
• FIGURE 5 is a simplified diagram of a gain cell which includes four p-type transistors, according to embodiments of the invention.
• FIGURE 6 is a simplified diagram of a gain cell which includes four n-type transistors, according to embodiments of the invention.
• FIGURE 7 is a simplified diagram of a gain cell which includes three p-type transistors and one n-type transistor, according to embodiments of the invention.
• FIGURE 8 is a simplified diagram of a gain cell which includes three n-type transistors and one p-type transistor, according to embodiments of the invention.
• FIGURE 9 is a simplified block diagram of a memory array, according to embodiments of the invention.
• FIGURE 10 is a timing diagram demonstrating 4T PMOS gain cell operation, according to embodiments of the invention.
• FIGURE 11 shows storage node degradation of a 4T PMOS gain cell following a write operation under the worst-case WBL bias conditions, according to embodiments of the invention
• FIGURES 12A-12C are simplified cell structure diagrams of a 6T SRAM, 2T1C gain cell and 2T gain cell respectively;
• FIGURE 13 shows a simplified layout of an exemplary four-transistor GC- eDRAM memory. DESCRIPTION OF SPECIFIC EMBODIMENTS OF THE INVENTION
• the present invention in some embodiments thereof, relates to a gain cell with internal feedback and, more particularly, but not exclusively, to a four-transistor gain cell with internal feedback.
• Embodiments herein present a gain cell that selectively protects a weaker data level by means of a feedback loop.
• the feedback loop decreases the required refresh frequency and reduces refresh power consumption.
• Figs. 1A and IB illustrate a prior art 2T all- PMOS gain cell during retention of a high data level and a low data level respectively.
• the PMOS 2T gain cell [ref. 2] is composed of a write transistor (PW), a read transistor (PR), and a storage node (SN).
• PW write transistor
• PR read transistor
• SN storage node
• This circuit displays asymmetric retention characteristics with highly advantageous retention of data T over data ' ⁇ ' .
• the worst-case biasing during retention of a T occurs when write bitline (WBL) is grounded and subthreshold (sub-Vx) leakage discharges SN, as illustrated in Fig. 1A.
• Fig. 2 presents simulation results of storage node degradation for a PMOS 2T gain cell following a write operation under the two worst-case biasing situations.
• the data shown in Fig. 2 was obtained from 1024 Monte Carlo simulations.
• Fig. 2 shows the superiority of the data T level in the PMOS 2T gain cell relative to the data '0' level.
• Fig. 2 also demonstrates the degraded retention times at scaled technologies, with an estimated DRT of only approximately 200 ⁇ , measured at the earliest intersection between the '0' and T samples.
• Embodiments herein diminish the worse-case data level decay by inserting retention element between the read and write transistors.
• the retention element forms a buffer node (BN) within the gain cell, and provides a feedback effect which maintains the voltage level at BN when the "weak" data level is being retained at SN.
• BN buffer node
• Gain cell 300 includes write transistor 310, retention element 320 and read transistor 330.
• the Dl diffusion input of write transistor 310 is connected to the write bit line (WBL) and the gate G is connected to write line (WWL).
• WWL serves as a write trigger similarly its function in the 2T gain cell.
• Diffusion connection Dl of read transistor 330 connects to the read bit line output (RBL) and diffusion connection D2 of read transistor 330 connects to the read trigger line (also denoted herein RWL and read word line).
• Retention element 320 is connected between the write transistor D2 diffusion connection and the gate of read transistor 330.
• a buffer node (BN) is formed between retention element 320 and the write transistor D2 diffusion connection.
• Retention element 320 also connects to a constant voltage, which may be a low data level (or ground) or a high data level depending on the transistor type as described below.
• Retention element 320 serves a dual purpose:
• Retention element 320 connects and disconnects the buffer node (BN) and the storage node (SN), based on the state of WWL.
• retention element 310 connects BN and SN so that the voltage levels at both nodes are equal.
• voltage retention e.g. standby
• retention element 310 disconnects BN from SN.
• Retention element 320 also provides a feedback mechanism which is controlled by the voltage level at SN during voltage retention.
• the write transistor diffusion connection D2 is connected to the constant voltage, which slows the decay of the voltage level at BN.
• the write transistor diffusion connection D2 is disconnected from the constant voltage, and the voltage at BN decays relatively slowly due to self-limiting effects (similarly to the 2T gain cell).
• gain cell 300 further includes capacitor C SN 340, between SN and ground.
• Reference element 400 includes two switching elements, 410 and 420.
• Switch 410 connects and disconnects BN and SN according to the WWL level.
• Switch 420 connects and disconnects BN from the constant voltage according to the voltage level at SN.
• switches 410 and 420 operate in a complementary manner, meaning that when one of the switches is “on” the other switch is “off” and vice versa.
• switching elements 410 and 420 are transistors, with the control signal input (e.g. WWL and/or SN level) being input to the respective transistor gate.
• control signal input e.g. WWL and/or SN level
• 4T gain cell Four-transistor (4T) gain cell
• Embodiments herein present a four-transistor gain cell that utilizes an internal feedback mechanism to significantly increase the data retention time in scaled CMOS technologies.
• the resulting gain cell displays a large reduction in retention power, with a reduction in bitcell area (as compared to a standard 6T SRAM).
• FIG. 5 is a simplified diagram of a four- transistor gain cell, according to embodiments of the invention.
• 4T gain cell 500 (also denoted herein a 4T PMOS gain cell) includes four p-type transistors, and optionally capacitor C SN 540.
• WBL connects to a diffusion connection write transistor 510 (PW).
• Feedback transistor 522 (PF) and buffer transistor 521 (PB) together serve as a retention element 520 between storage node SN and write transistor 510 (PW).
• Gain cell 500 includes two nodes, buffer node BN (at the junction of PW 510, PB 521 and PF
• Feedback transistor 522 conditionally discharges the BN node according to level at the SN node.
• Buffer transistor 522 separates the stored data level at SN from the BN level to ensure extended retention time.
• the gate of read transistor 530 (PR) connects to
• Optional combinations of transistor types for a 4T gain cell include: A) Write transistor, feedback transistor, buffer transistor and read transistor are all p-type transistors;
• Write transistor, feedback transistor, buffer transistor and read transistor are all n-type transistors (e.g. Fig. 6);
• Write transistor, feedback transistor, buffer transistor are p-type transistors, and the read transistor is n-type (e.g. Fig. 7);
• D) Write transistor, feedback transistor and buffer transistor are n-type transistors, and the read transistor is p-type (see Fig. 8).
• the 4T gain cell includes n-type transistors and the voltage levels and cell operation are adapted to the transistor type, as known in the art.
• gain cell 500 includes four standard threshold-voltage (V T ) transistors and is fully compatible with standard CMOS processes.
• V T threshold-voltage
• PMOS transistors are used. PMOS transistors have lower sub-Vx and gate leakages relative to NMOS transistor, which may provide longer retention times while maintaining a small cell area. Detailed cell operation is explained hereafter.
• all of the transistors in gain cell 500 are of the same type. In other embodiments, not all of the transistors in gain cell 500 are of the same type, but rather each transistor is implemented in a respective type which may vary.
• a non-limiting list of transistor types which may be included in gain cell 500 includes:
• FIG. 6 is a simplified diagram of a four- transistor gain cell, according to embodiments of the invention.
• 4T gain cell 600 includes four n-type transistors, and optionally capacitor C SN 640.
• Write transistor (NW) 610, feedback transistor (NF) 622, buffer transistor (NB) 621 and read transistor (NR) 630 are connected similarly to the p-type embodiment of Fig. 5.
• Feedback transistor 622 (NF) and buffer transistor 621 (NB) together serve as a retention element 620 between storage node SN and write transistor 610 (NW).
• the constant voltage input into feedback transistor 622 is V DD , as required for n-type transistor operation.
• the RBL is pre-charged and RWL is discharged (in contrast with the p-type transistor embodiment of Fig. 5, in which during the read operation RBL is pre-discharged and RWL is charged (see Fig. 10).
• Fig. 7 is a simplified diagram of a four- transistor gain cell, according to embodiments of the invention.
• 4T gain cell 700 includes three p-type transistors (PW, PB and PF), and optionally capacitor C SN - Read transistor (NR) is n-type.
• Write transistor PW, feedback transistor PW, buffer transistor PB and read transistor NR are connected similarly to the four p-type embodiment of Fig.
• Feedback transistor PF and buffer transistor PB together serve as a retention element 720 between storage node SN and write transistor PW.
• Feedback transistor PF and buffer transistor PB together serve as a retention element between storage node SN and write transistor PW.
• the constant voltage input into feedback transistor PF is connected to ground.
• FIG. 8 is a simplified diagram of a four- transistor gain cell, according to embodiments of the invention.
• 4T gain cell 800 includes three n-type transistors (NW, NB and NF), and optionally capacitor C SN - Read transistor (PR) is p-type.
• Write transistor NW, feedback transistor NW, buffer transistor NB and read transistor PR are connected similarly to the four n-type embodiment of Fig.
• Feedback transistor NF and buffer transistor NB together serve as a retention element 820 between storage node SN and write transistor PW.
• Feedback transistor PF and buffer transistor PB together serve as a retention element between storage node SN and write transistor NW.
• the constant voltage input into feedback transistor NF is connected to V DD - PMQS four-transistor (4T) gain cell
• Write transistor 510 PW
• buffer transistor 521 PB
• feedback transistor 522 PF
• read transistor 540 PR
• the write word line (WWL) which is connected to the gates of both PW 510 and PB 521, is pulsed to a negative voltage in order to enable a full discharge of SN (when writing a ⁇ ').
• Readout is performed by pre-discharging the read bit line (RBL) to ground and subsequently charging the read word line (RWL) to V DD - RBL is then conditionally charged if the storage node is low, and otherwise remains discharged.
• RBL read bit line
• RWL read word line
• V DD - RBL V DD - RBL
• a simple sense inverter is used on the readout path to save area and power.
• other conventional sense amplifiers are used for improved read performance.
• the increased retention time of 4T gain cell 500 occurs during standby periods, when the internal feedback mechanisms come into play. During hold, PW 510 and PB
• V SG of PF 522 is in deep cutoff, such that its effect on the circuit is almost negligible.
• V SG of PF 522 is equal to the voltage at BN (V BN )- This is much higher than the negative V SG of PB 521, and therefore any charge that leaks through PW 510 to BN will be discharged through PF 522 and not degrade the '0' level at SN. In this way, the worst-case condition of the 2T cell is eliminated and retention time is significantly increased.
• the feedback path protects the weak '0' level on the SN by pulling
• Fig. 9 is a simplified block diagram of a memory array, according to embodiments of the invention.
• Memory array 900 includes an array of 4T gain cells 910.1 to 910.n, with respective write trigger inputs (WWLlto WWLN) and read trigger outputs (RWL1 to RWLN).
• the write bit lines inputs (WBLs) of the 4T cells in the array are connected together to form a common write bit line (CWBL).
• the read bit line outputs (RBLs) of the 4T cells are connected together to form a common read bit line output (CRBL).
• the type of 4T gain cells forming the array may be any one of the embodiments described herein.
• Embodiments herein present a DRAM 4T gain cell which may be used for scaled CMOS nodes characterized by high leakage currents, which may be embedded in a GC- eDRAM.
• the gain cell design protects the weak data level by a conditional, cell-internal feedback path, while the feedback is disabled for the strong data level.
• the gain cell embodiments require low retention power and improved worst case retention time. This is achieved with a small cell area relative to a 6T SRAM in the same technology, making the embodiments herein an appealing high-density, low-leakage alternative.
• transistor is intended to include all such new technologies a priori.
• compositions, method or structure may include additional ingredients, steps and/or parts, but only if the additional ingredients, steps and/or parts do not materially alter the basic and novel characteristics of the claimed composition, method or structure.
• a compound or “at least one compound” may include a plurality of compounds, including mixtures thereof.
• range format is merely for convenience and brevity and should not be construed as an inflexible limitation on the scope of the invention. Accordingly, the description of a range should be considered to have specifically disclosed all the possible subranges as well as individual numerical values within that range. For example, description of a range such as from 1 to 6 should be considered to have specifically disclosed subranges such as from 1 to 3, from 1 to 4, from 1 to 5, from 2 to 4, from 2 to 6, from 3 to 6 etc., as well as individual numbers within that range, for example, 1, 2, 3, 4, 5, and 6. This applies regardless of the breadth of the range.
• Fig. 10 is a timing diagram demonstrating 4T PMOS gain cell operation through subsequent write and read operations.
• a '0' is written to SN by pulsing WWL to a negative voltage (-700 mV), thereby discharging SN through WBL.
• a read operation is performed by pre- discharging RBL by pulsing the PC control signal (not shown), and subsequently charging RWL.
• RBL is driven high through PR.
• WBL is driven high in order to write a T to SN.
• the pre-discharged RBL remains low, as the stored T level blocks the discharge path through PR 530.
• Fig. 11 shows storage node degradation of a 4T PMOS gain cell following a write operation under the worst-case WBL bias conditions.
• the results of Fig. 11 may be compared to those presented in Fig. 2 for the 2T PMOS gain cell. 1024 Monte Carlo samples were simulated in a 65 nm CMOS process with a 700 mV supply, driving WBL to the opposite voltage of that stored on SN (similarly to Fig. 2).
• the level degradation seen in Fig. 11 is not only much more balanced than the extremely asymmetric degradation of the 2T PMOS cell, but it is also more than an order of magnitude higher.
• the estimated DRT is 8.29 ms at 27 C° and 3.98 ms at 85 C°. This is over 3 times higher than the best retention time reported so far in a 65 nm CMOS node [ref. 9].
• the symmetric behavior of the two data states is more appropriate for differentiating between data '0' and data T levels, easing the design of a specific readout circuit and potentially further enhancing the actual retention time (i.e. latest successful read) compared to the 2T PMOS cell.
• Table 1 clearly emphasizes the benefits of the 4T PMOS gain cell, which achieves much lower power usage due to its increased retention time.
• Performance of the proposed 4T cell is summarized in Table 2.
• the active refresh energy is 6.89 fj/bit, composed of 5.88 fj/bit for read and 1.01 fj/bit for write.
• the 4T PMOS gain cell has a read delay of 2.32 ns (using a slow but small sense inverter) and a write delay of 0.4 ns (with and underdrive of -700mV).
• a conventional 2T gain-cell was measured to have a 0.29 ns write delay, which is the same order of magnitude as the proposed cell.
• Fig. 13 shows a simplified layout of an exemplary four-transistor GC-eDRAM memory.
• the marked dimensions are of a single 4T PMOS gain cell. It is seen that the cell area is 0.92 ⁇ by 0.77 ⁇ .
• simulations of an exemplary embodiment of a four-transistor (4T) GC-eDRAM memory show a threefold increase in retention time, as compared to the best previously proposed gain cell in the same 65 nanometer node technology, or using the same Production Design Kit (PDK) for simulations and/or manufacturing [ref. 7] .
• the improved retention time results in a factor of ten decrease in retention power (static plus refresh power) as compared to the static power of a 65 nm 6T SRAM [ref. 8] .
• the improved performance is achieved with a gain cell that is 40% smaller than a 6T SRAM cell in the same technology. This enables the creation of a high density memory array with low power integration.

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