EP3105762A1

EP3105762A1 - Method for customizing thin film electronic circuits

Info

Publication number: EP3105762A1
Application number: EP15704513.9A
Authority: EP
Inventors: Kris Jef Ria MYNY; Gerwin Gelinck; Jan Genoe
Original assignee: Interuniversitair Microelektronica Centrum vzw IMEC; Nederlandse Organisatie voor Toegepast Natuurwetenschappelijk Onderzoek TNO
Current assignee: Interuniversitair Microelektronica Centrum vzw IMEC; Nederlandse Organisatie voor Toegepast Natuurwetenschappelijk Onderzoek TNO
Priority date: 2014-02-11
Filing date: 2015-02-11
Publication date: 2016-12-21
Also published as: JP6496742B2; TWI632553B; WO2015121298A1; CN105981106A; JP2017510017A; TW201546814A; CN105981106B

Abstract

Method for customizing thin film electronic circuits A method for manufacturing a thin-film circuit is provided, the method comprising: (a) obtaining a thin-film circuit comprising at least one logic gate circuit having an output, the at least one logic gate circuit comprising a plurality of drive transistors and a plurality of load elements, at least one load element being electrically connected to the output; (b) sequentially providing a series of predetermined voltage patterns to the plurality of drive transistors, a voltage pattern comprising a set of voltages to be applied respectively between a gate and a source of a respective drive transistor; (c) measuring a series of output voltage values of the at least one logic gate circuit corresponding to the series of predetermined voltage patterns; (d) comparing the series of output voltage values with a series of respective predetermined reference output voltage values; (e) in case an output voltage value does not match the respective predetermined reference output voltage value, adapting the number of load elements electrically connected to the output; and (f) repeating steps (b) to (e) until the series of output voltage values matches the series of predetermined reference output voltage values.

Description

METHOD FOR CUSTOMIZING THIN FILM ELECTRONIC CIRCUITS

BACKGROUND

Technological Field

[1 ] The disclosed technology relates to methods for customizing thin-film electronic circuits, such as organic semiconductor based circuits or metal oxide semiconductor based circuits, after circuit fabrication. The disclosed technology relates to methods for transforming a general, multi-purpose thin-film electronic circuit after its fabrication into a specific-purpose thin-film electronic circuit.

[2] The disclosed technology relates to methods for customizing or modifying thin-film logic gate circuits comprising a plurality of thin-film transistors, such as organic semiconductor based logic gate circuits or metal oxide semiconductor based logic gate circuits, after transistor fabrication. More in particular, the disclosed technology relates to methods for matching a pull-up current with a pull-down current of such logic gate circuits after transistor fabrication. Description of the Related Technology

[3] Printing has been proposed as a technology for realizing low-cost thin-film electronic circuits, e.g. using roll-to-roll printing. It is a disadvantage of this approach that the resolution is low, hence the circuits are large and the yield is very low. As a result, the projected low cost could not be achieved.

[4] There is a need for thin-film electronic circuits that can be provided at low cost and in large production volumes.

[5] In US 2006/0190917 a process for manufacturing custom printed circuit boards on substrates pre-provided with electronic devices is described. The user designs the custom printed circuit board using a design tool to perform one or more specific electronic functions, based on the pre-provided electronic devices and/or custom designed and direct printed devices. The custom printed circuit board is then created by direct printing of one or more conductive paths between the pre-provided devices. It is an advantage of this approach that substrates pre-provided with electronic devices can be fabricated in large production volumes, which may lead to a cost reduction.

[6] For thin-film circuits, such as organic circuits and metal oxide semiconductor circuits, it is known that the transistor fabrication process may lead to a large spread of technology parameters, such as for example a large spread in carrier mobilities or in transistor threshold voltages. In ηη-Thickness 64-Channel Surface Electromyogram Measurement Sheet with 2V Organic Transistors for Prosthetic Hand Control", ISSCC 2013, Hiroshi Fuketa et al propose a method for transistor mismatch reduction of an organic amplifier array. A post- fabrication select and connect method is proposed, using two groups of N parallel transistors. First the IV-characteristics of each transistor are measured, requiring 2N measurements. Then, taking into account these characteristics, transistors are selected from each group of N transistors based on a calculation to minimize the mismatch. The selected transistors are then connected by inkjet printed interconnects. It is a disadvantage of this approach that the characteristics of all transistors need to be measured.

SUMMARY OF CERTAIN INVENTIVE ASPECTS

[7] Certain inventive aspects relate to methods for customizing thin-film electronic circuits, such as organic semiconductor based circuits or metal oxide semiconductor based circuits, after circuit fabrication. Certain inventive aspects relate to methods for transforming a general, multi-purpose thin-film electronic circuit after its fabrication into a specific-purpose thin film electronic circuit.

[8] Certain inventive aspects relate to methods for modifying thin-film logic gate circuits, such as organic semiconductor based logic gate circuits or metal oxide semiconductor based logic gate circuits, after transistor fabrication. Certain inventive aspects relate to methods for matching a pull-up current with a pull-down current of such logic gate circuits after transistor fabrication. The skilled person knows what is meant with a pull-up current and a pull-down current of a logic gate circuit.

[9] A method for manufacturing a thin-film circuit according to the present disclosure comprises:

(a) obtaining a thin-film circuit comprising at least one logic gate circuit having an output, the at least one logic gate circuit comprising a plurality of drive transistors and a plurality of load elements, at least one load element being electrically connected to the output;

(b) sequentially providing a series of predetermined voltage patterns (test patterns) to the plurality of drive transistors, a voltage pattern comprising a set of voltages to be applied respectively between a gate and a source of a respective drive transistor;

(c) measuring a series of output voltage values of the at least one logic gate circuit corresponding to the series of predetermined voltage patterns; (d) comparing the series of output voltage values with a series of respective predetermined reference output voltage values;

(e) in case an output voltage value does not match the respective predetermined reference output voltage value, adapting the number of load elements electrically connected to the output; and

(f) repeating steps (b) to (e) untill the series of output voltage values matches the series of predetermined reference output voltage values.

[10] For instance, a matching between a measured output voltage value and a respective predetermined reference output voltage value can mean that both correspond to (or are interpreted as) a same logical level. For example, both are interpreted as a logical 1 or both are interpreted as a logical 0. Not matching then means that both are interpreted as a different logic level.

[1 1 ] The predetermined reference output voltage values correspond to the output voltage values which are expected when the logic gate circuit is working correctly and is fed with the series of predetermined voltage patterns (test patterns). Thus, when the series of output voltage values matches the series of predetermined reference output voltage values, the logic gate circuit works properly, and is finalised.

[12] In embodiments of the present disclosure, a predetermined part (subset) of the plurality of drive transistors has a drain electrically connected to the output of the at least one logic gate circuit. The remaining drive transistors are electrically disconnected from (not electrically connected to) the output. All drive transistors may have their drain electrically connected to the output, or a predetermined selection from the plurality of drive transistors may have their drain electrically connected to the output, or none of the plurality of drive transistors may have a drain electrically connected to the output.

[13] It is an advantage of a method of the present disclosure that a predetermined

(expected, anticipated) functionality of a thin-film circuit can be obtained, despite variations and potentially large spreads in technology parameters and/or transistor parameters, by adapting the circuit after thin-film transistor fabrication. It is an advantage of a method of the present disclosure that adapting the circuit after thin-film transistor fabrication is based on a characterization of the functionality of the circuit, without a need for measuring the characteristics of each transistor individually. The functionality of the circuit is characterized by measuring a series of output voltage values for an applied series of predetermined voltage patterns. [14] In a method of the present disclosure, the step of adapting the number of load elements electrically connected to the output preferably comprises electrically connecting a single additional load element to the output or electrically disconnecting a single load element from the output. In such embodiment, the number of load elements connected to the output is adapted one by one, until the series of output voltage values matches the series of predetermined reference output voltage values. By adapting one by one, the risk of connecting or disconnecting too many load elements may be avoided.

[15] In a method of the present disclosure the plurality of load elements may be load transistors, with at least one load transistor having a source electrically connected to the output.

[16] The thin-film circuit may comprise a plurality of logic gate circuits.

[17] For example, the plurality of logic gate circuits may be part of a Write Once Read Many Memory. Sequentially providing the series of predetermined voltage patterns between a gate and a source of the plurality of drive transistors may comprise sequentially turning ON only one of the plurality of drive transistors, subsequently for each of the plurality of drive transistors. Measuring a series of the output voltage values then comprises reading out data stored in the memory.

[18] The Write Once Read Many Memory may for example be part of an instruction generator circuit, wherein the Write Once Read Many Memory stores instructions for a general purpose microprocessor.

[19] The Write Once Read Many Memory may for example be part of a customized code generator of an RFID circuit, wherein the Write Once Read Many Memory stores an identification code. Providing a series of predetermined voltage patterns between a gate and a source of the plurality of drive transistors may be initiated by powering the RFID circuit. Measuring a series of output voltage values then comprises reading out the identification code.

[20] A method of the present disclosure may further comprise, after obtaining the thin-film circuit and before providing the series of predetermined voltage patterns: estimating the number of load elements required to match a pull-up current with a pull-down current of the at least one logic gate circuit, based on statistical data; and adapting the number of load elements electrically connected to the output of the at least one logic gate circuit to have the estimated number of load elements connected to the output.

[21 ] The statistical data may for example comprise measures of parameters selected from a transistor threshold voltage, a transistor threshold voltage spread, a carrier mobility, a carrier mobility spread, a gate capacitance, a gate capacitance spread, a gate width, a gate width spread, a gate length and a gate length spread. These data may for example be measured during or just after fabrication of the thin-film transistors.

[22] In embodiments of the present disclosure, adapting the number of load elements electrically connected to the output of the at least one logic gate circuit may comprise connecting an additional load element to the output of the at least one logic gate circuit. Connecting an additional load element to the output may comprise printing an electrical connection between the load element and the output, such as for example inkjet printing an electrically conductive material.

[23] In embodiments of the present disclosure, adapting the number of load elements electrically connected to the output of the at least one logic gate circuit may comprise disconnecting a load element from the output of the at least one logic gate circuit, for example by interrupting an electrical connection between the load element and the output using laser processing (e.g. laser cutting).

[24] In embodiments of the present disclosure a load element may for example be selected from an n-type depletion-load thin-film transistor, an n-type enhancement-load thin-film transistor, a p-type depletion-load thin-film transistor, a p-type enhancement-load thin-film transistor and a resistor, the present disclosure not being limited thereto.

[25] The present disclosure provides a method for post-fabrication configuration of thin-film electronic circuits, the method comprising: fabricating a multi-purpose thin-film electronic circuit comprising a plurality of electronic devices and a plurality of electrical connections, and afterwards transforming the multi-purpose circuit into a predetermined specific-purpose thin-film circuit with an anticipated/envisaged/required circuit performance by establishing at least one additional electrical connection and/or by removing at least one electrical connection.

[26] In embodiments of the present disclosure, the general-purpose circuit may comprise redundant electronic elements, such as for example redundant electronic input devices and/or redundant electronic output devices.

[27] In embodiments of the present disclosure, transforming the multi-purpose thin-film circuit into a predetermined specific-purpose thin-film circuit is preferably done using relatively cheap equipment, materials and processes. For example, establishing at least one additional electrical connection may be done by printing, e.g. inkjet printing, of a metal containing ink. For example, removing at least one electrical connection may be done by means of a laser (laser cutting). However, the present disclosure is not limited thereto and other suitable methods may be used for establishing and/or for removing electrical connections.

[28] A method of the present disclosure may advantageously be used to optimize circuit performance and to reduce yield loss due to a large parameter spread. It is an advantage of a method of the present disclosure that it may result in an increased robustness with respect to large device parameter spreads.

[29] It is an advantage of a method of the present disclosure that a well-established technology for large volume manufacturing of thin-film transistors may be used to fabricate thin-film circuits in large volumes and with high yield, and that simultaneously customization of the thin-film electronic circuits is achieved. It is an advantage of this approach that low- cost manufacturing can be achieved because of the very large production volumes, larger than the volume of each individualized function or specific-purpose circuit.

[30] It is an advantage of embodiments of the present disclosure that product definition (customization, realization of a specific-purpose thin-film circuit) can be done at a late stage of the manufacturing process using a cheap method such as for example local inkjet printing of a metal containing ink.

[31 ] Certain objects and advantages of various inventive aspects have been described herein above. Of course, it is to be understood that not necessarily all such objects or advantages may be achieved in accordance with any particular embodiment of the disclosure. Thus, for example, those skilled in the art will recognize that the disclosure may be embodied or carried out in a manner that achieves or optimizes one advantage or group of advantages as taught herein without necessarily achieving other objects or advantages as may be taught or suggested herein. Further, it is understood that this summary is merely an example and is not intended to limit the scope of the disclosure. The disclosure, both as to organization and method of operation, together with features and advantages thereof, may best be understood by reference to the following detailed description when read in conjunction with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[32] Figure 1 (a) shows a block diagram of a P²ROM instruction generator chip and a zoom of a unipolar n-type printable WORM memory.

[33] Figure 1 (b) shows a zoom of a column of 16 select transistors and the possibility to add 5 load transistors for a NOR gate, e.g. by inkjet printing (UP) of a conductive ink, in accordance with a method of the present disclosure. [34] Figure 2(a) shows V_out versus V_in simulation curves for a 16-bit NOR gate with a single depletion-load load transistor.

[35] Figure 2(b) shows V_out versus V_in simulation curves for a 16-bit NOR gate with multiple load transistors.

[36] Figure 3(a) shows output characteristics of typical solution-processed oxide n-type transistors.

[37] Figure 3(b) shows output characteristics of typical evaporated pentacene p-type transistors.

[38] Figure 3(c) shows inverter characteristics of a hybrid complementary technology at different power supply voltages.

[39] Figure 4 shows a detailed layout of a P²ROM instruction generator with connections printed after circuit fabrication, in accordance with a method of the present disclosure.

[40] Figure 5 shows measured signals of a P²ROM instruction generator when configured (post-fabrication printed in accordance with the present disclosure), to execute a running averager algorithm.

[41 ] Figure 6 shows measured signals of both the P²ROM and processor core chips while executing a running averager algorithm. The pulses in the top part of the figure correspond to the command "store in output register".

[42] Figure 7 schematically shows a block diagram of a 64 bit code generator of an RFID transponder chip.

[43] In the different drawings, the same reference signs refer to the same or analogous elements.

DETAILED DESCRIPTION OF CERTAIN ILLUSTRATIVE EMBODIMENTS

[44] In the following detailed description, numerous specific details are set forth in order to provide a thorough understanding of the disclosure and how it may be practiced in particular embodiments. However, it will be understood that the present disclosure may be practiced without these specific details. In other instances, well-known methods, procedures and techniques have not been described in detail, so as not to obscure the present disclosure. While the present disclosure will be described with respect to particular embodiments and with reference to certain drawings, the disclosure is not limited hereto. The drawings included and described herein are schematic and are not limiting the scope of the disclosure. It is also noted that in the drawings, the size of some elements may be exaggerated and, therefore, not drawn to scale for illustrative purposes. [45] The present disclosure will be described with respect to particular embodiments and with reference to certain drawings but the disclosure is not limited thereto but only by the claims. The drawings described are only schematic and are non-limiting. In the drawings, the size of some of the elements may be exaggerated and not drawn on scale for illustrative purposes. The dimensions and the relative dimensions do not necessarily correspond to actual reductions to practice of the disclosure.

[46] Moreover, the terms top, bottom, over, under and the like in the description and the claims are used for descriptive purposes and not necessarily for describing relative positions. It is to be understood that the terms so used are interchangeable under appropriate circumstances and that the embodiments of the disclosure described herein are capable of operation in other orientations than described or illustrated herein.

[47] In the context of the present disclosure, "post-fabrication" or "after circuit fabrication" means after fabrication of thin-film semiconductor devices such as thin-film transistors.

[48] In the context of the present disclosure, "Write Once Read Many Memory" refers to a memory wherein information is written after its fabrication, and wherein once written, the information is not modified anymore and the memory can be read out many times. The writing of the information does not need to be done in a single writing step. It can also be done in several subsequent writing steps.

[49] The present disclosure provides a method for post-fabrication configuration of thin-film electronic circuits, such as for example organic semiconductor based thin-film electronic circuits or metal oxide semiconductor based thin-film circuits, the present disclosure not being limited thereto. A method according to the present disclosure comprises: fabricating a multi-purpose thin-film electronic circuit comprising a plurality of electronic devices and a plurality of electrical connections, e.g. between electronic devices, and afterwards transforming the multi-purpose circuit into a predetermined specific-purpose thin-film circuit by establishing at least one additional electrical connection and/or by removing at least one electrical connection. In embodiments of the present disclosure, the general-purpose circuit may comprise redundant electronic elements, such as for example redundant electronic input devices and/or redundant electronic output devices.

[50] The present disclosure provides a method for customizing thin film logic gate circuits, such as organic semiconductor based logic gate circuits or metal oxide semiconductor based logic gate circuits, after transistor fabrication. More in particular, the present disclosure provides a method for matching a pull-up current with a pull-down current of such logic gate circuits after circuit fabrication. [51 ] A method in accordance with the present disclosure is further described in the context of some specific examples, wherein the possibility to control the ratio of the number of load transistors versus the number of drive transistors in unipolar NOR gates is shown. The method is illustrated for an example of a productized instruction generator for a general purpose chip set, but the present disclosure is not limited thereto. The method could also be used for other applications such as for example for a customized code generator for RFID systems, the present disclosure not being limited thereto. The method of the present disclosure can be used in other configurations and for other applications.

[52] Figure 1 (a) shows a block diagram of a P²ROM (Print Programmable Read Only Memory) instruction generator chip 100 and a zoom 201 of a unipolar n-type printable

WORM (Write Once Read Many) memory 200. The memory 200 comprises a fixed pull-up network 210 comprising load transistors (Opc(0), Opc(1 ),...) and a programmable pull-down network 220 for each data line 300, 301 . In the example shown, the pull-up network is based on zero-V_GS-load connected n-type transistors. However, in alternative approaches other loads may be used such as for example resistor loads, diode-connected n-type transistors or p-type transistors. Also p-type implementations and complementary implementations are possible.

[53] Programming the printable WORM memory 200 (i.e. writing data in the memory) may be done by providing for predetermined select transistors (SelO, Sell ) an electrical connection between the select transistor and a data line 300, 301 and by leaving other select transistors disconnected from a data line. Providing an electrical connection may be done by inkjet printing an electrically conductive material between the predetermined select transistor and a data line. Printing the electrically conductive material may for example be done in a region labeled 'UP' in FIG. 1 (a).

[54] In another approach (not shown in the drawings), all select transistors may be connected to a data line after fabrication and the memory may be programmed by removing predetermined connections (i.e. disconnecting predetermined select transistors), e.g. by laser patterning.

[55] Figure 1 (b) illustrates an example wherein the ratio of the number of load transistors (Opc) versus the number of drive transistors or select transistors in a unipolar NOR gate 10 can be adapted after circuit fabrication, using a method according to the present disclosure. In Figure 1 (b) a general circuit layout of a NOR gate 10 is shown. Specifically in the example shown, select transistors SelO, ... Sell 5 may for example be initially electrically disconnected from a data line 300 (corresponding to an output of the gate 10), and a predetermined number of these transistors may be electrically connected to the circuit (to the data line 300), e.g. by locally printing, e.g. inkjet printing, an electrically conductive material 40, after circuit fabrication. If the logic gate 10 is part of a memory (as in Fig 1 (a)), the connection of predetermined select transistors or drive transistors to the output corresponds to programming the memory, i.e. writing data in the memory. The local printing (indicated in Figure 1 (b) by 'UP', meaning 'ink jet printing') is preferably done in areas that have a planar configuration of electrodes on a dielectric surface. In case no conductive material is provided, the select transistor remains electrically disconnected.

[56] In a method according to the present disclosure, a similar inkjet printing step can be applied to at least part of the load transistors Opc. The ratio of connected load transistors versus connected drive transistors (select transistors) determines the performance of a NOR gate. As shown in FIG. 1 (b), in embodiments of the present disclosure the pull-up network is not fixed but for each data line 300 a plurality of load transistors (Opc) is provided (up to six load transistors in the example shown). After transistor fabrication, only one load transistor (as shown in FIG 1 (b)) or a limited number of load transistors is connected to a data line 300. In a method of the present disclosure additional load transistors can be connected to the data line 300, e.g. by inkjet printing.

[57] In an alternative embodiment, the select transistors and/or the load transistors may be initially electrically connected to the circuit and a predetermined number of these transistors may be disconnected by means of a method that cuts metal wiring, such as for example laser cutting. In other embodiments, part of the transistors may be initially electrically connected to the circuit and another part of the transistors may be initially disconnected.

[58] The ratio of connected load transistors versus connected drive transistors may be changed using a method in accordance with the present disclosure, by connecting and/or disconnecting dedicated transistors after circuit fabrication.

[59] In a method of the present disclosure, the active load (pull-up network) is not fixed but it may be adapted or modified after transistor fabrication. Such post-fabrication modification may significantly reduce the effect of variations in the technology (and corresponding parameter variations in the select transistors) on the functionality of the circuit. Variations in the technology affect for example the leakage current of the transistors and therefore these variations influence the pull-down current of a memory data bit line 300 when the pull-down is not active, i.e. when the drive transistors are OFF. Such post-fabrication modification may for example aim at matching the pull-up current with the pull-down current such that the output can be pulled up sufficiently fast when the pull-down is not active. [60] Parameter variations in the select transistors (SelO, Sell , ...) and the number of select transistors connected to the output line (e.g. as determined by the application, e.g. a specific code in the memory) both influence the pull-down current of a memory data bit line. As a consequence of these influences the active pull-down current is not known upfront (i.e. at the design stage of the circuit), and therefore the pull-up current cannot be easily matched to the pull-down current at the design stage of the circuit. Using a method according to the present disclosure, the pull-up current can be matched to the pull-down current after circuit design and after transistor fabrication, by changing the number of connected load transistors.

[61 ] Figure 2 shows simulation curves that illustrate the importance of controlling the load/driver ratio of a NOR gate. Figure 2(a) shows V_out versus V_in simulation curves (transfer characteristics) for a 16-bit NOR gate with a single depletion-load load transistor, for one to sixteen inputs (one to sixteen select transistors). Figure 2(b) shows V_out versus V_in simulation curves (transfer characteristics) for a 16-bit NOR gate with 16 inputs and multiple (1 to 6) load transistors. For a 16-input NOR gate, with only one depletion-load load transistor, the NOR gate loses its functionality from 12 inputs on (Figure 2(a)). Figure 2(b) demonstrates what happens when more (1 to 6) load thin film transistors are provided. The Voltage Transfer Curve recovers for 16 inputs, which makes this circuit more robust.

[62] In a method of the present disclosure the pull-up current of a logic gate circuit is matched to the pull-down current after fabrication of the transistors, based on a

measurement of the functionality of the circuit and/or based on a characterization of the technology and the design. Matching the pull-up current to the pull-down current is done by connecting (e.g. by inkjet printing) or disconnecting (e.g. by laser cutting) a required number of load transistors to the data line (output of the logic gate).

[63] In a method according to the present disclosure, a thin-film circuit is fabricated, the thin- film circuit comprising at least one logic gate circuit having an output. The at least one logic gate circuit comprises a plurality of drive transistors that may or may not have a drain electrically connected to the output and it further comprises a plurality of load elements. At least one load element is electrically connected to the output of the logic gate. The remaining (i.e. non-connected) load elements are redundant load elements, that may be connected to the output of the logic gate if needed for obtaining a predetermined

performance (predetermined functionality) of the logic gate circuit.

[64] In a method of the present disclosure, e.g. in order to check the functionality of the thin- film circuit, an series of predetermined voltage patterns (input voltage patterns) is provided to the plurality of drive transistors, i.e. a voltage pattern is applied between a gate and a source of the plurality of drive transistors. The series of predetermined voltage patterns can comprise a single input voltage combination for the plurality of drive transistors or it can comprise a sequence of input voltage combinations for the plurality of drive transistors.

[65] Next, a series of output voltage values corresponding to the series of predetermined voltage patterns is measured for the at least one logic gate circuit and the measured series of output voltage values is compared with the series of predetermined reference output voltage values (i.e. with the output voltage values expected based on the required functionality of the circuit).

[66] In case the measured series of output voltage values corresponds to, i.e. matches, the series of predetermined reference output voltage values, no further actions are taken. In case the measured series of output voltage values is different from, i.e. does not match, the series of predetermined reference output voltage values, the number of load elements electrically connected to the output is adapted, i.e. increased or decreased.

[67] Preferably a single load element is additionally connected to or disconnected from the output. With this adapted circuit configuration the steps of providing a series of

predetermined voltage patterns, measuring a series of output voltage values and comparing the series of measured output voltage values with the expected output voltage values (series of predetermined reference output voltage values) are repeated. Then again, depending on the outcome of this comparison, a single load element may be additionally connected or disconnected. These steps are repeated till the series of measured output voltage values corresponds to, i.e. matches, the predetermined output voltage values, i.e. untill the required functionality of the circuit is obtained.

[68] For example, if the logic gate circuit is part of a memory comprising data bits, after the transistor fabrication process the data bits may first be printed in the memory by inkjet printing, thereby connecting predetermined drive transistors to the output. Next, a series of predetermined voltage patterns is applied and a series of output voltage values is measured in accordance with a method of the present disclosure. This corresponds to reading out the data stored in the memory. Some bits may e.g. be read-out as a logical zero (measured as low) where a high value (logical one) would have been expected. This may be due to the active load not providing sufficient pull-up current to obtain a high value at the output. In this case additional load transistors are connected (e.g. by inkjet printing) to the data line till a high output is obtained. [69] As an alternative to the inkjet printing based implementation, after transistor fabrication all data bits may be entered in the memory by laser patterning, e.g. laser cutting.

Subsequently all memory bits are read out and verified in accordance with a method of the present disclosure. Some bits may be read-out as a logical one (measured as high) where a low value (logical zero) would have been expected. This may be due to the active load providing too much pull-up current. Connections between load transistors and the data line may then be removed by laser patterning until the required low output is obtained.

[70] In embodiments of the present disclosure, after fabrication of the circuit and before measuring its functionality by applying a series of predetermined voltage patterns and measuring a series of output voltage values, the required number of load transistors needed to match a pull-up current with a pull-down current may be estimated based on statistical data, and this estimated number of load transistors may be connected to the output of the logic gate circuit before testing its functionality. Statistical data that may be taken into account are for example (a measure of a parameter selected from) transistor threshold voltage, a transistor threshold voltage spread, a carrier mobility, a carrier mobility spread, a gate capacitance, a gate capacitance spread, a gate width, a gate width spread, a gate length and a gate length spread, the present disclosure not being limited thereto.

[71 ] In this approach, after or during the production process of the thin-film circuit the technology parameters and their local variations are measured. Based on these measured values and on the knowledge of the required data in the memory (i.e. the number of connected drive transistors), the non-active pull-down current is calculated, i.e. the pulldown current when the drive transistors are OFF. From this non-active pull-down current the matching pull-up current can be derived. Subsequently, the matching pull-up transistor configuration is realized using inkjet printing or laser patterning. Next, the pull-up transistor configuration of the logic gate circuit may further be adapted based on an assessment of its functionality as described above.

[72] The description above is related to a unipolar n-type TFT technology. However, the present disclosure is not limited thereto and a method of the present disclosure may for example also be used in case of a unipolar p-type TFT technology. In that case the pull-up connection and the pull-down connection are interchanged as compared to the case of a unipolar n-type TFT technology.

[73] In embodiments of the present disclosure, a specific layout may be used for establishing the electrical connections by local (inkjet) printing. A planar configuration of comb-shaped electrodes 20 (schematically shown in Figure 1 (b)) may advantageously be used. This allows an efficient use of area. The electrodes 20 are preferably provided on a nonconducting layer or surface. Optionally, a well 30 may be formed by providing a layer of dielectric material, such as e.g. a layer of a negative photoresist, and locally removing this layer of dielectric material in a predetermined area, thereby forming a well structure 30 in the predetermined area. This is in particular advantageous in embodiments wherein the surface on which the conductive material, e.g. conductive ink, is to be printed is ink-repellant. The presence of a well structure 30 in a predetermined area helps to confine the electrically conductive ink into that area. Figure 1 (b) also shows a zoom of a well structure 30 and comb-shaped electrodes 20 before providing an electrically conductive ink, and after providing an electrically conductive ink 40. In the example shown the pattern of the well 30 has a square shape and the pattern of the electrically conductive ink 40 has a circular shape. However, the present disclosure is not limited thereto and other suitable shapes may be used. In the example shown in Figure 1 (b) the conductive ink pattern only fills part of the well. However it may also fill a smaller or a larger part of the well, e.g. it may completely fill the well 30.

[74] A method of the present disclosure may be used for post-fabrication compensation for process variability (e.g. differences in V_T) or for post-fabrication compensation for gate voltage variations, which could increase leakage.

[75] A method of the present disclosure is not limited to unipolar depletion-load NORs as described above. It may for example also be used with enhancement-load NORs (or diode- load). Ultimately, in order to be more robust against V_T variation, one can provide both load transistors. A method of the present disclosure may also be used for adding or removing resistor-loads or in terms of complementary technologies, a pseudo-pMOS or pseudo-nMOS load.

[76] An 8bit thin-film microprocessor was fabricated using a hybrid oxide-organic complementary thin-film technology, comprising a memory formatted after fabrication by inkjet printing according to a method of the present disclosure. The n-type transistors are based on a solution-processed n-type metal-oxide semiconductor, and the p-type transistors use an organic semiconductor. As compared to previous work utilizing unipolar logic gates, the higher mobility n-type semiconductor and the use of complementary logic allows for a >50x speed improvement. It also adds robustness to the design, which allowed for a more complex and complete standard cell library. The microprocessor consists of two parts, a processor core chip and an instruction generator. The instructions are stored in a Write- Once-Read-Many (WORM) memory formatted by a post-fabrication inkjet printing step in accordance with a method of the present disclosure. This memory is further called Print- Programmable Read-Only Memory (P²ROM). The entire processing was performed at temperatures compatible with plastic foil substrates, i.e., at or below 250^qC.

[77] Typical output characteristics of the hybrid organic/oxide complementary transistors are shown in Figure 3. Figure 3(a) shows output characteristics of typical solution-processed oxide n-type transistors and Figure 3(b) shows output characteristics of typical evaporated pentacene p-type transistors. The use of this technology for complex designs has been proven already for a bi-directional RFID tag and has been proven on flexible substrates. The p:n transistor ratio for logic gates has been chosen to be 3:1 , whereby the minimal device size for an oxide n-TFT equals 50/5 μηη/μηη and for an organic p-TFT 150/5 μηη/μηη. Typical inverter characteristics are shown in Figure 3(c). The circuit realizations are based on bottom-gate top S/D contact oxide n-TFTs and bottom S/D contact organic p-TFTs, fabricated on a Si/Si0₂ substrate.

[78] The thin-film microprocessor is split up into two separate chips, being the processor core chip and a general purpose instruction generator or P²ROM. The P²ROM chip is a one-time programmable ROM memory that is configured by means of inkjet printing of a conductive ink in accordance with the present disclosure, the conductive ink containing silver in this example. Using this approach, the general-purpose instruction generator is converted into a specific-purpose instruction generator. The block diagram of the general purpose instruction generator is depicted in Figure 1 (a). It consists of a 4-bit program counter (PC), a 4-16 decoder to select each instruction line at once, a printable

(configurable) WORM memory and a 9-bit register that is updated each clock cycle with the next opcode (operation code) to drive the microprocessor. Each printed connection results in a logical 1 , while unprinted connections result in a logical 0. The printable WORM memory is designed as a unipolar n-TFT NOR, with a 1 :10 ratio between drive and load transistors. The drive transistor has a size of 140/5 μηη/μηη, while the load transistor has a size of 1400/5 μηη/μηη. In order to guarantee good NOR characteristics for the case that multiple select transistors are connected and required, up to 5 more load transistors can be added also by inkjet printing, as illustrated in Figure 1 (b).

[79] Figure 4 shows the layout of the P²ROM instruction generator chip, divided into a hybrid complementary part and a unipolar n-TFT part. In order to evaluate the P²ROM chip, instructions were printed to execute a running averager algorithm (out_new = 0.5 round (in + out_oi_d))- The first twelve lines have been printed for the running averager algorithm. The other 4 lines in the instruction generator are not printed and therefore result in the NOOP (no operation) command. The instructions run the algorithm twice before storing the value into the output register. Because the LSR instruction is executed only after the storage into the output register, the output code is a 7bit code, which is one bit more accurate than the 6 bit input. Figure 5 depicts the correct behavior of the P²ROM chip at a supply voltage of 10V and a maximum clock frequency of 650Hz. It generates the register select bits and the operational codes to drive the processor core chip in order to execute the running averager algorithm. The order of instructions are also detailed in Figure 5.

[80] Finally, the processor core and P²ROM chips were connected. Figure 6 shows the measured results when both chips are connected at a clock frequency of 500Hz. When the input switches from 0 to 7 (hexadecimal), the output averages between 7, C and E and remains constant at E (hexadecimal).

[81 ] Figure 7 shows an example of a block diagram of a 64 bit code generator 50 of an RFID transponder chip. The code generator 50 comprises a clock generator 51 , a 3-bit binary counter 52, a 8:1 multiplexer 53, an 8-bit line select block 54, a 64-bit WORM memory 55 storing a customized identification code, and an output register 56. The identification code may for example be written in the memory after circuit fabrication, e.g. by inkjet printing or by laser cutting as described above. When the transponder chip is powered, a clock signal 60 is generated by clock generator 51. The clock signal 60 is used to clock the output register 56, the 3-bit binary counter 52 and the 8-bit line select circuit 54. The line select circuit 54 has an internal 3-bit binary counter and a 3-to-8 decoder. This block selects a row of eight bits in the memory 55 comprising the code (this is for example done by turning ON the corresponding drive transistors). The 3-bit binary counter 52 drives the 8:1 multiplexer 53, which selects a column of eight bits in the memory 55. The data bit at the crossing of the selected row and the selected column is transported via the multiplexer 53 to the output register 56, which sends this bit on the rising edge of the clock signal to a modulation transistor (not shown in Figure 7). The three bits of the 3-bit binary counter 52 are also used in the 8-bit line select block 54 for selecting a new row after all eight bits in a row have been transmitted to the output register. In this way, all bits of the identification are read out upon powering the circuit.

[82] A method of the present disclosure may be used for modifying the thin-film logic gate circuit of the WORM memory 55. Each column of the WORM memory 55 may for example contain a logic gate circuit 10 as shown in Figure 1 (b), wherein each select transistor (drive transistor) corresponds to a different row of the memory matrix. After fabrication of the circuit and after writing an identification code in the memory, the memory is read out as described above, by sequentially selecting a row (i.e. sequentially turning ON a single select transistor of a logic gate circuit 10, subsequently for each of the plurality of select transistors) and measuring an output voltage value for each logic gate circuit 10, i.e. for each column of the memory matrix. Each output voltage value is interpreted as a logical level, i.e. a logical one or a logical zero. If a bit (logical level) read from the memory does not correspond to the expected or anticipated bit (expected logical level) of the identification code, an additional load element may be connected to the corresponding logic gate circuit 10 or a load element may be disconnected from the corresponding logic gate circuit 10.

[83] The foregoing description details certain embodiments of the disclosure. It will be appreciated, however, that no matter how detailed the foregoing appears in text, the disclosure may be practiced in many ways. It should be noted that the use of particular terminology when describing certain features or aspects of the disclosure should not be taken to imply that the terminology is being re-defined herein to be restricted to including any specific characteristics of the features or aspects of the disclosure with which that terminology is associated.

[84] While the above detailed description has shown, described, and pointed out novel features of the invention as applied to various embodiments, it will be understood that various omissions, substitutions, and changes in the form and details of the device or process illustrated may be made by those skilled in the technology without departing from the invention.

Claims

A method for manufacturing a thin-film circuit, the method comprising:

(b) sequentially providing a series of predetermined voltage patterns to the plurality of drive transistors, a voltage pattern comprising a set of voltages to be applied respectively between a gate and a source of a respective drive transistor;

(c) measuring a series of output voltage values of the at least one logic gate circuit corresponding to the series of predetermined voltage patterns;

(d) comparing the series of output voltage values with a series of respective

predetermined reference output voltage values;

(f) repeating steps (b) to (e) until the series of output voltage values matches the series of predetermined reference output voltage values.

The method according to claim 1 , wherein a predetermined part of the plurality of drive transistors has a drain electrically connected to the output of the at least one logic gate circuit.

3. The method according to any of claims 1 and 2, wherein the plurality of load elements are load transistors, at least one load transistor having a source electrically connected to the output.

4. The method according to any of the previous claims, wherein the thin-film circuit

comprises a plurality of logic gate circuits.

5. The method according to claim 4, wherein the plurality of logic gate circuits are part of a Write Once Read Many Memory, wherein sequentially providing a series of predetermined voltage patterns to the plurality of drive transistors comprises

sequentially turning ON only one of the plurality of drive transistors, subsequently for each of the plurality of drive transistors, and wherein measuring a series of output voltage values comprises reading out data stored in the memory.

6. The method according to claim 5, wherein the Write Once Read Many Memory is part of an instruction generator circuit, the Write Once Read Many Memory storing instructions for a general purpose microprocessor.

7. The method according to claim 5, wherein the Write Once Read Many Memory is part of a customized code generator of an RFID circuit, the Write Once Read Many Memory storing an identification code, wherein providing a series of predetermined voltage patterns to the plurality of drive transistors is initiated by powering the RFID circuit and wherein measuring a series of output voltage values comprises reading out the identification code.

8. The method according to any of the previous claims, further comprising, after obtaining the thin-film circuit and before providing the series of predetermined voltage patterns: estimating the number of load elements required to match a pull-up current with a pull-down current of the at least one logic gate circuit, based on statistical data; adapting the number of load elements electrically connected to the output of the at least one logic gate circuit to the estimated number of load elements.

9. The method according to claim 8, wherein said statistical data comprises measures of parameters selected from a transistor threshold voltage, a transistor threshold voltage spread, a carrier mobility, a carrier mobility spread, a gate capacitance, a gate capacitance spread, a gate width, a gate width spread, a gate length and a gate length spread.

10. The method according to any of the previous claims, wherein adapting the number of load elements electrically connected to the output of the at least one logic gate circuit comprises connecting one additional load element to the output of the at least one logic gate circuit.

1 1 . The method according to claim 10, wherein connecting one additional load element to the output of the at least one logic gate circuit comprises printing an electrical connection between the load element and the output.

12. The method according to claim 1 1 , wherein printing comprises inkjet printing an

electrically conductive material.

13. The method according to any of claims 1 to 9, wherein adapting the number of load elements electrically connected to the output of the at least one logic gate circuit comprises disconnecting one load element from the output of the at least one logic gate circuit.

14. The method according to claim 13, wherein disconnecting one load element from the output comprises interrupting an electrical connection between the load element and the output by laser cutting.

15. The method according to any of the previous claims, wherein the load elements are selected from an n-type depletion-load thin-film transistor, an n-type enhancement-load thin-film transistor, a p-type depletion-load thin-film transistor, a p-type enhancement- load thin-film transistor and a resistor.