Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F11/00—Error detection; Error correction; Monitoring
  • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
  • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
  • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
  • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
  • G06F11/1012—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using codes or arrangements adapted for a specific type of error
  • G06F11/1016—Error in accessing a memory location, i.e. addressing error
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F11/00—Error detection; Error correction; Monitoring
  • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
  • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
  • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
  • G06F11/1076—Parity data used in redundant arrays of independent storages, e.g. in RAID systems
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
  • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
  • G06F3/0601—Interfaces specially adapted for storage systems
  • G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
  • G06F3/0614—Improving the reliability of storage systems
  • G06F3/0619—Improving the reliability of storage systems in relation to data integrity, e.g. data losses, bit errors
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
  • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
  • G06F3/0601—Interfaces specially adapted for storage systems
  • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
  • G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
  • G06F3/065—Replication mechanisms
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
  • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
  • G06F3/0601—Interfaces specially adapted for storage systems
  • G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
  • G06F3/0671—In-line storage system
  • G06F3/0683—Plurality of storage devices
  • G06F3/0685—Hybrid storage combining heterogeneous device types, e.g. hierarchical storage, hybrid arrays
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
  • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
  • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
  • H03M13/05—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits
  • H03M13/11—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using block codes, i.e. a predetermined number of check bits joined to a predetermined number of information bits using multiple parity bits
  • H03M13/1102—Codes on graphs and decoding on graphs, e.g. low-density parity check [LDPC] codes
  • H03M13/1105—Decoding
  • H03M13/1142—Decoding using trapping sets

Definitions

• the field of the invention is that of data storage.
• the invention relates to a data storage technique based on the use of an error correction code, and more specifically on the use of a graph code, to cleverly distribute the data on different media. storage.
• the invention is based on the use of hollow graph codes, referred to as "sparse" graph codes.
• the invention finds particular applications for the storage of personal data, data within a company, etc.
• DCS distributed storage networks
• An RSDC network conventionally consists of a master server, one or more sets of hard disks that each have a slave server, and clients.
• the master server is responsible for receiving the files from the clients, distributing them and transmitting them to the slave servers.
• a slave server is responsible for encoding the files and distributing the bytes generated on the hard disks at its disposal. In case of failure of a hard disk, the slave server associated with it is responsible for finding the data erased from previously calculated parities.
• the master server When reading data stored by a client, the master server transmits to the slave servers concerned the request, collects the data and transmits it to the client.
• FIG. 1 illustrates an exemplary RSDC network comprising four clients 11 to 14, a set of five hard drives D1 to D5, and a single server 15 responsible for master and slave tasks.
• An error correcting code is a code enabling a decoder to detect or correct alterations as a result of transmission or storage. Such error correction code introduces redundancy, making it possible to reconstruct erased data in the event of failure of a hard disk.
• a first set of source data (DIA) of a first codeword on the disk D1 is stored, a second set of source data (D2A) of the first codeword on the disk D2, a third source data set (D3A) of the first code word on the disk D3, a fourth source data set (D4A) of the first code word on the disk D4, and a set of redundancy data ( PA) of the first codeword on the disk D5.
• DIA source data
• D2A source data of the first codeword on the disk D2
• D3A third source data set
• D4A fourth source data set
• PA redundancy data
• a first set of source data (DIB) of a second code word on the disk D1 is stored, a second set of source data (D2B) of the second code word on the disk D2, a third source data set (D2C) of the second code word on the disk D3, one set of redundancy data (PB) of the second code word on the disk D5, and a fourth set of source data (D2D) of the second word of code on the D4 disk, etc.
• N hard disks such as NM hard drives store source data (also called user data) and M hard drives store redundancy data (also called parity data), and if the error correction code is an MDS code, the system will be able to support M simultaneous failures without loss of data.
• RAID in English "Redundant Array of Independent Disks", in French “redundant grouping of independent disks”
• RAID refers to techniques for distributing data across multiple hard drives to improve either fault tolerance, security, or overall performance, or a breakdown of all this.
• RAID Levels Each of these levels constitutes a mode of use of the network of hard disks, according to:
• the storage cost the ratio between the number of bytes available for storage and the total byte number in the network
• the constitution of the different RAID networks results from a compromise between various parameters such as protection against hard disk failures, the speed of reading, writing and reconstructing data on the network and finally the cost of storage.
• the main limitation of this technology is that there is no RAID level that can handle multiple simultaneous hard drive failures, with low storage cost and low complexity.
• the main technological brake comes from the error correction code that protects the stored data.
• the invention proposes a new solution that does not have all of these disadvantages of the prior art, in the form of a data storage method, implementing an error correction code defining a set of related variables. constraints, each variable being associated with source data and / or redundancy data.
• such a method implements the following steps:
• the determination of the variables composing a stopping cycle makes it possible to identify the variables that must not be erased simultaneously in order to be able to find the source data.
• the distribution of the variables composing a stopping cycle on separate storage media thus makes it possible to avoid the blocking of the decoder which could occur if all the variables constituting a shutdown cycle were erased simultaneously in the event of a storage medium failure.
• stopping set is well known to those skilled in the art, and is particularly recalled in the document "Modem Coding Theory" by Richardson and Urbanke.
• a stopping cycle is a subset of the set of variables, such that all the constraint nodes (also called parity nodes) that are connected to the variables composing the stopping cycle in the representation under Shape of a Tanner graph are connected to the variables composing the stopping cycle at least twice.
• the size of a cycle is defined by the number of constraint nodes and variables thus connected.
• source or redundancy data may be bits or symbols, and correspond to values carried by the variables.
• the storage method according to the invention can implement a step of coding at least one vector comprising the source data, delivering at least one vector to be stored comprising the source data and / or the redundancy data, by applying the error correction code to the source data.
• the distribution step can then allocate the values of the variables associated with the vector (s) to be stored on the plurality of storage media.
• an error correcting code according to the invention is designed to correct erase (within) errors of a storage medium.
• the error correction code is of the hollow-graph code type, said "sparse" graph code, whose generator matrix or parity check matrix is a hollow matrix.
• such a code can be represented by a generator matrix or a parity check matrix mainly comprising null elements.
• This is for example an LDPC type code or derived from an LDPC (Low Density Parity Check) code.
• the method implements a preliminary step of constructing the error correction code, implementing the determination of a generator matrix or a parity check matrix formed from a repetition of at least one predetermined pattern, called structured matrix.
• Such a cyclic or quasi-cyclic structure of the matrix makes it possible to rapidly determine the short cycles, and especially the stopping cycles, of the error correction code.
• the form and / or size of the generator or parity check matrix can be defined taking into account the number of available storage media and / or the number of allowed variable deletions / failures of storage media.
• the number of columns of the generating matrix or parity check must be equal to the number of storage media, or a multiple of the number of storage media.
• the error correction code is systematic.
• the vector to be stored obtained at the end of the coding, carries both the source data and the redundancy data. It is thus possible to read part of the stored data (the part corresponding to the source data) without performing mathematical operations.
• the code is constructed with a generator matrix carrying an identity matrix.
• the distribution step stores the source and / or redundancy data associated / assigned to a given variable on the same storage medium.
• the distribution step stores the source and / or redundancy data associated / assigned to the same variable on separate storage media.
• variable distribution step is implemented "band by band", by determining a first allocation scheme for a first band corresponding to a first vector to be stored, then a second allocation scheme for a first band second band corresponding to a second vector to be stored, a third allocation scheme for a third band corresponding to a third vector to be stored, etc.
• the same allocation scheme is used for the different bands, but working on different storage media: for example the variables v0, v1, v2 are stored on a first storage medium for the first band, on a second storage medium for the second band, and a third storage medium for the third band.
• the storage media belong to the group comprising:
• such storage media can be connected in a network.
• Such a network can in particular be dynamic and flexible.
• the steps for constructing an error-correcting and allocation code determination of the stopping cycles, determination of an allocation scheme, distribution of the variables on the various storage media
• the steps for constructing an error-correcting and allocation code can be implemented again.
• it is also possible to adapt the allocation by deleting certain columns of the allocation matrix, without repeating the code construction steps, determining the stopping cycles. and determining an allocation scheme.
• all the storage media have the same size.
• the invention relates to a data storage device using an error correction code defining a set of variables linked by constraints, each variable being associated with source data and / or redundancy data.
• such a device comprises:
• a module for determining variables comprising at least one code stop cycle, a module for determining a variable allocation scheme, allocating to each component variable a stop cycle a separate storage medium,
• Such a data storage device is particularly suitable for implementing the data storage method described above. It is for example integrated in a server (slave or master-slave) of an RSDC network, responsible for coding the user data and to distribute the coded data generated on the storage media at its disposal.
• Such a data storage device may of course include the various features relating to the data storage method according to the invention, which can be combined or taken in isolation. Thus, the features and advantages of this data storage device are the same as those of the data storage method. Therefore, they are not detailed further.
• the invention also relates to a method of decoding data stored on a plurality of storage media, the data having been previously stored on the plurality of storage media by implementing an error correction code defining a set of related variables. by constraints, each variable being associated with source data and / or redundancy data, and variable determining steps comprising at least one code stop cycle, determining a variable allocation scheme, allocating each variable constituting a shutdown cycle a separate storage medium, and distribution of the variables or data associated with the variables on the storage media, according to the allocation scheme, as defined above.
• such a decoding method implements a decoding step comprising at least one iteration of the following steps, when at least one of the storage media is faulty:
• the invention thus makes it possible to implement an iterative type decoding, for an application in the field of data storage.
• Such decoding offers a reduced complexity compared to the decoding techniques conventionally used in this field.
• such a decoding method is adapted to decode data stored according to the storage method described above.
• the features and advantages of this method of decoding stored data are the same as those of the data storage method.
• the decoding method stores the order of solving the equations of the system of equations implemented. during the step of decoding a first set of stored data. During the step of decoding at least a second set of stored data, the decoding method resolves the equations of the system of equations in this order of resolution.
• the invention relates to a device for decoding data stored on a plurality of storage media, the data having been previously stored on the plurality of storage media by means of a data storage device using an error correcting code defining a set of variables linked by constraints, each variable being associated with source data and / or redundancy data, and comprising a module for determining the variables composing at least one code stopping cycle; a module for determining a variable allocation scheme, allocating to each component variable a shutdown cycle a separate storage medium, and a module for distributing the variables or data associated with the variables on the storage media, according to the allocation scheme, as defined above.
• such a decoding device comprises a decoding module comprising:
• a search module in a system of equations representative of the code, of at least one equation presenting a single variable associated with a datum previously stored on the faulty storage medium (s), said erased variable,
• the search, rebuild and update modules being activated at least once, in the form of at least one iteration, when at least one of the storage media has failed.
• Such a device for decoding stored data is particularly suitable for implementing the stored data decoding method described above. It is for example integrated in a server (slave or master-slave) of an RSDC network, responsible for reading the stored data and reconstruct the erased data.
• Such a device for decoding stored data may of course include the various features relating to the method of decoding stored data according to the invention, which can be combined or taken in isolation.
• the features and advantages of this stored data decoding device are the same as those of the stored data decoding method. Therefore, they are not detailed further.
• the invention also relates to one or more computer programs, comprising instructions for performing the steps of the data storage method as described above, and / or the method of decoding stored data as described above, when the program or programs are executed by a computer.
• Figure 1 illustrates an exemplary RSDC network
• FIG. 3 presents the main steps implemented by a data storage method according to at least one embodiment of the invention
• FIGS. 4A and 4B illustrate the general principle of the distribution of the variables composing a stopping cycle on separate storage media
• FIGS. 5A and 5B illustrate an example of distribution of the variables comprising stop cycles on ten hard disks
• FIG. 6 shows the distribution of the data of a vector to be stored on ten hard disks obtained at the end of the storage operation
• FIGS. 7 and 8 illustrate the distributions of the data of three vectors to be stored on ten hard disks obtained at the end of the storage operation, according to two variants
• FIG. 10 shows the main steps implemented by a method of decoding stored data according to at least one embodiment of the invention.
• Figures 11 and 12 respectively illustrate the simplified structure of a storage device implementing a data storage technique and the simplified structure of a stored data decoding device according to a particular embodiment of the invention.
• the general principle of the invention is based on the use of a particular type of error correction codes, the codes in graph, in particular of the "sparse" type, for data storage applications.
• the proposed solution relies on an algorithm associating specific error-correcting code and a data allocation in order to obtain a deterministic behavior codes in graphs. This makes it possible to consider the use of uncomplicated codes for data storage systems.
• the proposed data storage model can be simulated by a block erase channel (in English BLEC for "Erasure Block”) with a variable codeword size.
• D_max denotes the maximum protection of the network, i.e. the maximum number of erased storage media that the network can support.
• the proposed data storage model corresponds to a particular BLEC channel, with Pl> P2> ...> Pd_max. This means that the probability of erasure of a data carrier is considered to be dependent on the state of the rest of the network (i.e. of all storage media).
• Pd_max + ⁇ 0 with ⁇ an integer such that ⁇ > 0. This means that data stored on more than one storage medium can not be erased simultaneously.
• the codes in "sparse" graphs group different families of error-correcting codes.
• the first family of these codes noted LDPC, was introduced by Robert Gallager.
• the name of these codes comes from the fact that, contrary to the MDS codes for example, the generator matrix used (or the parity check matrix) includes many null elements, which means that the calculation of the parity bits becomes less complex. because it requires fewer operations.
• the term “graph code” comes from the generally bipartite graph representation that Tanner proposed for these codes. This representation is generalized for the families derived from the LDPC codes, and the term code in graph regroups today these numerous codes with complexities of encoding and / or weak decoding.
• FIG. 2 illustrates an error correction code under its representation in the form of a graph, where the circles on the left of the graph correspond to the variables v1 to v5 (which may be of the source data or redundancy data type). , and the squares on the right correspond to the constraints cl to c3.
• such a code can, equivalently, be represented by a system of equations or by a generator matrix or a parity check matrix.
• LDPC codes and their derived families, can reach or get closer to the Shannon bound, while keeping coding and decoding complexity low thanks to the use of an iterative decoder, for example of the "Belief Propagation" type (belief propagation decoder).
• Such a method can implement an error correction code defining a set of variables linked by constraints and can therefore be represented by a graph.
• a graph code is of the sparse type.
• Such a method may optionally implement a prior step of constructing the code, for example at the initialization of the storage algorithm.
• variables constituting at least one stopping cycle of the code also called “stopping set” and noted SS.
• a variable allocation scheme is determined, allocating to each component variable a shutdown cycle a separate storage medium.
• a third step 33 the variables, or the data associated with these variables, are distributed on the storage media, according to the allocation scheme.
• Each variable that composes a stop cycle (or associated data) is thus distributed on a separate storage medium.
• a step of coding the source data can be implemented prior to the distribution step. Such an encoding step makes it possible to construct, from at least one source data vector, at least one encoded data vector to be stored. The coded data associated with the variables can then be stored according to the allocation scheme.
• the codes in graph are non-MDS codes when using an iterative decoder.
• the main reason is the presence of stop cycles within these codes in graphs, which correspond to short cycles.
• the problem of short cycles can be presented by a system of equations in the context of data storage, where the only errors considered possible are the erasure of part of the data. When all the elements of a cycle are erased, we obtain a system where several equations have more than two unknowns, which makes the end of the decoding impossible.
• the various variables constituting a short cycle, and more specifically a stopping cycle are distributed over different storage media.
• the invention therefore proposes to use a highly structured code where the cycles are easily identifiable (generally this type of code has a large number of cycles and is not considered efficient) and to cleverly allocate the variables so that all variables of a stop cycle can not be erased at the same time.
• variable is defined at the level of the actual construction of the code.
• An error correction code thus defines a set of combinations that the variables must respect. These variables can take different values, corresponding to source data or redundancy data of a "code word", also called vector to be stored.
• condition s (H)> 2 (N-K) makes it possible to ensure a distribution of the data associated with variables composing a stopping cycle on more than N-K disks.
• the use of a structured code facilitates the implementation of the step of determining the variables making up a stop cycle.
• the chosen code must make it possible to quickly determine the cycles.
• a quasi-cyclic structure is used. It is recalled that this structure makes it possible to extend to infinity the same matrix structure. Thus, if one is able to determine the cycles on a given small structure (of the order of a hundred variables), one will regularly find the same cycles by extending this structure. We will then be able to determine the stopping cycles that prevent the iterative decoding from succeeding.
• a LDGM code is used which allows very fast data encoding.
• a parity check matrix consisting of ten rows and fifty columns, which means that five bytes per hard disk sector can be stored.
• Such a parity check matrix H is formed of an identity matrix of size 10 ⁇ 10, denoted Id 10 ⁇ 10, and of a repetition of four patterns column by column (11, 101, 1001, 10001):
• the columns of the parity check matrix H represent the different variables v0 to v49 of the error correction code, and the lines of the parity check matrix the different constraints c0 to c9 that the variables v0 to v49 must respect.
• vO vlO + vl9 + v20 + v28 + v30 + v37 + v40 + v46
• vl vlO + vil + v21 + v29 + v31 + v38 + v41 + v47
• v2 vil + vl2 + v20 + v22 + v32 + v39 + v42 + v48
• v3 vl2 + vl3 + v21 + v23 + v30 + v33 + v43 + v49
• v4 vl3 + vl4 + v22 + v24 + v31 + v34 + v40 + v44
• v5 vl4 + vl5 + v23 + v25 + v32 + v35 + v41 + v45
• v6 vl5 + v16 + v24 + v26 + v33 + v36 + v42 + v46
• v7 vl6 + v7 + v25 + v27 + v34 + v37 + v43 + v47
• v8 vl7 + vl8 + v26 + v28 + v35 + v38 + v44 + v48
• v9 vl8 + vl9 + v27 + v29 + v36 + v39 + v45 + v49
• the corresponding generator matrix G comprises fifty rows and forty columns:
• parity check matrix H and the generator matrix G both comprise the matrix P. This is a property of the LDGM codes, which use the same matrix for encoding and decoding the data.
• the parity check matrix H being very structured, it is possible to easily determine the short cycles, and especially the stopping cycles.
• the set of variables forming a size 6 stop cycle is thus identified, the set of variables forming a size 8 stop cycle, and so on.
• Each variable of a shutdown cycle is then distributed on separate hard disks.
• FIGS. 4A and 4B schematically illustrate the idea of distributing the variables comprising a stop cycle over a sufficiently large number of disks to make it impossible to delete all the variables of a stop cycle simultaneously.
• the hatched nodes represent a shutdown cycle.
• the size of this cycle defined by the number of nodes composing the cycle (ie the number of nodes of variables and nodes of constraint), is equal to 6. If the variables A, C, E composing this cycle of stop are erased simultaneously, the decoder will have to solve a system comprising three equations with two unknowns without the possibility of determining these unknowns. If one considers that one seeks to protect oneself from the loss of two disks, one will distribute the three variables A, C, E composing this cycle of stop on three different disks Dl, D2, D3 to make this case erasure impossible.
• the parity check matrix H does not have size cycles 4. It is also noted that two variables associated with the same pattern in the parity check matrix H ('1' for the variables vO to v9 of degree 1, '11' for variables vl0 to vl9 of degree 2, '101' for variables v20 to v29 of degree 2, '1001' for variables v30 to v39 of degree 2 and '10001' for variables v40 to v49 of degree 2) are usually part of a size 6 cycle (composed of 3 variables). So we decide not to store on the same support two variables associated with the same pattern. Moreover, we see that if all the variables allocated to the same storage medium do not intervene more than once on all the lines, then respecting the previous point, we will not be able to fall into a size cycle. when erasing two storage media.
• the allocation scheme can therefore be built iteratively in accordance with the rules above.
• FIGS. 5A and 5B show two equivalent allocation schemes illustrating an example of distribution of these variables over ten disks D1 to D10, working with five bytes per disk according to the invention. More precisely, FIG. 5A shows the result of the distribution of the variables on the ten disks, and FIG. 5B illustrates an allocation matrix making it possible to obtain this result. For example, we allocate the variables v0, v11, v23, v44 and v36 (or the values carried by these variables) to the disk D1, the variables v2, v13, v25, v46 and v38 (or the values carried by these variables).
• the proposed allocation according to the invention makes it possible to distribute the variables so that each disk stores a set of variables which intervenes only in nine different equations, which means that all the variables of the same disk does not intervene on a line of the parity check matrix.
• the parity check matrix very structured, has many short, closed cycles.
• the allocation therefore makes it possible to distribute the variables so that the variables intervening in stop cycles are stored on more than two disks.
• variables v26, v42 and v48, and variables v14, v22, v32 form two cycles that could block iterative decoding if a disk storing these variables fails.
• these variables are distributed on three different disks (D7, D5 and D3 for the first stopping cycle, and D7, D10 and D4 for the second stopping cycle).
• D7, D5 and D3 for the first stopping cycle
• D7, D10 and D4 for the second stopping cycle
• the following is an example of data storage implementing the method of data storage according to at least one embodiment of the invention.
• the generator matrix G can be obtained from the parity check matrix H.
• This generating matrix G makes it possible, from a source data vector U, to obtain a data vector to be stored R.
• the code constructed according to the invention is systematic.
• the values of the source data vector U are found identically in the data vector to be stored R, which thus comprises source data and redundancy data.
• RI [5,120,78,56,98,9,3,25,156,230,34,7,67,83,54,93,175,3,28,186,220,54,7,24,54,75,
• a data vector to be stored R2 is obtained carrying the following symbols:
• R2 [1,46,58,245,65,165,7,8,40,12,54,89,94,243,153,210,196,154,220,3,52,16,39,52,37,53,
• a data vector to be stored R3 is obtained carrying the following symbols:
• R3 [65.78,42.243,156,23,187,123,154,67,90,36,71,1,98,0,32,74,213,5,69,15,67,39,125,8, 39,2,15,69,176,216,176,3 , 74,92,42,189,38,4,80,75,233,153,194,69,116,75,127,172]
• variables v0 to v49 defined previously can successively take the following values (where for each cell, the three numbers respectively correspond to a symbol of the vector to be stored R1, to a symbol of the vector to be stored R2, and to a symbol of the vector to store R3):
• the distribution step stores the source or redundancy data assigned to a given variable on the same storage medium.
• the values 223, 36 and 80 assigned to the variable v0 are stored on the disk D1.
• the distribution step stores the source or redundancy data assigned to a given variable on separate storage media.
• the values 223, 36 and 80 assigned to the variable v0 are respectively stored on the disk D1, the disk D2 and the disk D3.
• the disks can be decomposed into strips (stripe), each band being associated with a vector to be stored.
• the first vector to store RI is stored as described above.
• the second vector to be stored R2 is stored as described above, with an offset of a disk relative to the first vector to be stored R1.
• the third vector to be stored R3 is stored as described above, with an offset of one disk relative to the second vector to be stored R2.
• variable distribution step is therefore implemented "band by band", by determining a first allocation scheme for the first band, then a second band allocation scheme for the second band, a third allocation scheme for each band. the third band, etc.
• the same allocation scheme is used with an offset of a hard disk.
• the redundancy data (parity) is distributed on the different disks, as proposed in the level 5 of the RAID algorithm ("Parity striping").
• FIG. 9 shows another example of distribution of the variables on eight disks D1 to D8, supporting the failure of two hard disks.
• This allocation scheme or matrix corresponds to a lower triangular LDPC matrix, and is obtained by deleting certain columns of the allocation matrix illustrated in FIG. 5B.
• the average complexities of encoding and decoding are 6.2 XORs per octet.
• such a decoding method makes it possible to retrieve the source data even if one or more storage media are erased.
• such a decoding method implements a decoding step 100 comprising at least one iteration of the following steps, when at least one of the storage media is faulty:
• search 101 in a system of equations representative of the code, of at least one equation presenting a single variable associated with a data item (source and / or redundancy) previously stored on the one or more failed storage media, said erased variable.
• a decoding step 100 is implemented for the decoding of each stored vector R, that is to say band by band.
• An example of implementation of the invention is presented more precisely, for the decoding of data stored on a set of ten hard disks as illustrated in FIG. 7, supporting the failures of two hard disks.
• the decoding step described above is applied to the first band.
• the eighth equation v7 + vl6 + vl7 + v25 + v27 + v34 + v37 + v43 + v47 0 includes a single unknown, the data associated with variable v25.
• v25 v7 + vl6 + v7 + v27 + v34 + v37 + v43 + v47
• v36 v9 + vl8 + vl9 + v27 + v29 + v39 + v45 + v49
• the system of equations can then be updated taking into account the values of the reconstructed v25 and v36 variables. This step makes it possible to play the equations in which the variables v25 and v36 intervene.
• the first equation always includes two unknowns. It is the same for the second, third, fourth, fifth and ninth equations.
• the sixth equation includes a single unknown, the data associated with variable v23.
• v23 v5 + v14 + v15 + v25 + v32 + v35 + v41 + v45
• the system of equations can then be updated taking into account the values of the v23 and v46 variables rebuilt.
• the equation system is then solved, which means that the first band, corresponding to the first stored vector, can be decoded, and the source data restored, even after erasure of two hard disks.
• the decoding step 100 can be implemented band by band.
• decoding can memorize the order of resolution of the equations of the system of equations implemented during the decoding step of the first band.
• the decoding method knows the optimal order of resolution of the equations, which gives a remarkable time saving to the decoding.
• the invention is not limited to this type of error correction code, and all codes in sparse type graph (i.e whose generating matrix and / or the parity check matrix is hollow) can be used.
• the code can be constructed to store the data on twelve hard disks and protect them from three erasures.
• the step of constructing the code proposes to respect the step structure, which allows a low-cost encoding thanks to the transformation algorithm of the parity check matrix H proposed in the document "Efficient encoding of Low-Density Parity- Check Codes "(TJ Richardson and RL Urbanke, IEEE Transactions on Information Theory, Vol 47, No. 2, February 2001), and build a relatively small basic matrix without size cycle 6.
• the character quasi-cyclic makes it easy to extend the size of the matrix.
• the simulation results show a remarkable gain in the decoding time in particular.
• all cases of erasure of three disks have been corrected without error.
• a data storage device according to at least one embodiment of the invention comprises a memory 111 comprising a buffer memory, a processing unit 112, equipped for example with a ⁇ microprocessor, and driven by the computer program 113, implementing the method of storing data according to at least one embodiment of the invention.
• the code instructions of the computer program 113 are for example loaded into a RAM before being executed by the processor of the processing unit 112.
• the processing unit 112 receives as input at least a source data vector.
• the microprocessor of the processing unit 112 implements the steps of the method of storing data according to at least one embodiment described above, according to the instructions of the computer program 113, for coding the source data vector or vectors, and distribute the symbols of the vector or vectors to be stored thus obtained on the various storage media.
• the data storage device comprises, in addition to the buffer memory 111, a determination module 114 of the variables comprising at least one code stop cycle, a determination module 115 of an allocation scheme of said variables, allocating to each component variable a shutdown cycle a separate storage medium, and a distribution module 116 of the variables or data associated with the variables on the storage media, according to the allocation scheme.
• a device for decoding stored data comprises a memory 121 comprising a buffer memory, a processing unit 122, equipped for example with a ⁇ microprocessor, and driven by the computer program 123, implementing the decoding method according to at least one embodiment of the invention.
• the code instructions of the computer program 123 are for example loaded into a RAM before being executed by the processor of the processing unit 122.
• the processing unit 122 has a set of data stored on storage media, at least one of which may be faulty.
• the microprocessor of the processing unit 122 implements the steps of the decoding method described above, according to the instructions of the computer program 123, to find all the source data from the stored data.
• the storage device comprises, in addition to the buffer memory 121, a decoding module comprising a search module 124, in a system of equations representative of the code, of at least one equation presenting a single variable associated with a given data item.

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