EP3089077A1 - Procede de controle d'un circuit integre, document, systeme de controle et dispositif de personnalisation - Google Patents

Procede de controle d'un circuit integre, document, systeme de controle et dispositif de personnalisation Download PDF

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Publication number
EP3089077A1
EP3089077A1 EP16166301.8A EP16166301A EP3089077A1 EP 3089077 A1 EP3089077 A1 EP 3089077A1 EP 16166301 A EP16166301 A EP 16166301A EP 3089077 A1 EP3089077 A1 EP 3089077A1
Authority
EP
European Patent Office
Prior art keywords
integrated circuit
test
document
program instructions
terminal
Prior art date
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Granted
Application number
EP16166301.8A
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German (de)
English (en)
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EP3089077B1 (fr
Inventor
Florian Peters
Steffen Scholze
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Bundesdruckerei GmbH
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Bundesdruckerei GmbH
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Publication of EP3089077A1 publication Critical patent/EP3089077A1/fr
Application granted granted Critical
Publication of EP3089077B1 publication Critical patent/EP3089077B1/fr
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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/0723—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips the record carrier comprising an arrangement for non-contact communication, e.g. wireless communication circuits on transponder cards, non-contact smart cards or RFIDs
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/26—Testing of individual semiconductor devices
    • G01R31/265—Contactless testing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/0716—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips at least one of the integrated circuit chips comprising a sensor or an interface to a sensor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07701—Constructional details, e.g. mounting of circuits in the carrier the record carrier comprising an interface suitable for human interaction
    • G06K19/07703—Constructional details, e.g. mounting of circuits in the carrier the record carrier comprising an interface suitable for human interaction the interface being visual
    • G06K19/07707—Constructional details, e.g. mounting of circuits in the carrier the record carrier comprising an interface suitable for human interaction the interface being visual the visual interface being a display, e.g. LCD or electronic ink
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/077—Constructional details, e.g. mounting of circuits in the carrier
    • G06K19/07749—Constructional details, e.g. mounting of circuits in the carrier the record carrier being capable of non-contact communication, e.g. constructional details of the antenna of a non-contact smart card

Definitions

  • the invention relates to a method for testing an integrated circuit with a contactless RF interface and to a document, in particular a value or security document, such as an identity document, with a document body containing such an integrated circuit.
  • the invention has for its object to provide an improved method for testing an integrated circuit with a contactless RF interface and a document that includes such an integrated circuit, a test system and a personalization device for such a document.
  • a “contactless HF interface” is understood here to mean, in particular, a communication interface, wherein the communication takes place via a high-frequency carrier wave, for example in the megahertz range, in particular according to an RFID or NFC method in the near field.
  • the coupling of the energy required for the operation of the integrated circuit also takes place via the carrier wave, so that a separate power supply of the integrated circuit and the consumer optionally connected thereto is not required.
  • An "integrated circuit” is understood to mean in particular an electronic semiconductor circuit, in particular a chip, or a printed electronic circuit, such as a polymer electronic circuit, or a combination thereof.
  • a "chip card command” is understood here in particular as a so-called command APDU (application protocol data unit), to which a response APDU is generated according to a request-response communication protocol.
  • command APDU application protocol data unit
  • a “terminal” is understood here to mean, in particular, an electronic device that is configured to send chip card commands and to receive replies to chip card commands, the terminal having a contactless HF interface that is compatible with the integrated circuit.
  • a "document” is understood to mean, in particular, paper-based and / or plastic-based documents, such as electronic identification documents, in particular passports, ID cards, visas and driving licenses, vehicle registration documents, vehicle letters, company ID cards, health cards or other ID documents as well as chip cards, payment means, in particular Banknotes, bank cards and credit cards, bills of lading or other credentials incorporating a non-volatile electronic data store for storing at least one attribute.
  • electronic identification documents in particular passports, ID cards, visas and driving licenses
  • vehicle registration documents vehicle letters, company ID cards, health cards or other ID documents as well as chip cards
  • payment means in particular Banknotes, bank cards and credit cards, bills of lading or other credentials incorporating a non-volatile electronic data store for storing at least one attribute.
  • the test of the integrated circuit in particular for the evaluation of a predefined quality requirements of the circuit, takes place with the contactless RF interface in that a terminal sends a predefined test command to the contactless RF interface. Only on condition that the integrated circuit is in its first unpersonalized state does the integrated circuit execute the test command and then send the test response back to the terminal.
  • the terminal determines / records the amount of time that elapsed between sending the test command and receiving the test response. The terminal then checks whether this period of time is within a specified tolerance range. The terminal then signals the result of the test.
  • the integrated circuit is configured to send a latency extension signal to the terminal via the contactless RF interface to request an extension of the latency of the terminal to the response of the integrated circuit to a smart card command of the terminal.
  • This can be a Waiting Time Extension (WTX) signal which is also referred to as Frame Waiting Time Extension signal, in particular as specified in ISO / IEC 14443.
  • WTX Waiting Time Extension
  • the waiting time of the terminal after sending a smart card command to the corresponding response of the integrated circuit is to be extended, which is the case in particular when the integrated circuit is operated at a low clock rate due to a relatively low power input got to.
  • the terminal may be arranged to generate the signal for signaling the existence of the check only under the additional condition that the waiting time extension signal is not received from the terminal after transmission of the check command, or that the wait time extension signal is only a maximum number of times Repetitions is received by the terminal if a single or multiple extension of the waiting time is tolerable.
  • the integrated circuit is designed to generate a field strength increase signal and to send it via the RF interface to the terminal, in particular when the power coupled in via the carrier wave is relatively low.
  • the integrated circuit requires such a field strength increase signal to request an increase in field strength at which the carrier wave is radiated from the terminal, this indicates that the quality and / or resonant frequency of the resonant circuit do not meet the quality requirements the coupled power is not sufficient at the field strength given by the terminal.
  • the terminal may be arranged to issue the signal for signaling the existence of the test only under the additional condition that it does not receive a field strength increase signal after the transmission of the test command.
  • the execution of the predetermined sequence of operations due to the execution of the test command involves the insertion of one or more integrated circuit electrical consumers, such as a non-volatile memory, a hardware random number generator, a hardware co-processor, in particular one hardware co-processor for symmetric and / or asymmetric cryptographic methods, a computing unit and / or a memory management unit.
  • integrated circuit electrical consumers such as a non-volatile memory, a hardware random number generator, a hardware co-processor, in particular one hardware co-processor for symmetric and / or asymmetric cryptographic methods, a computing unit and / or a memory management unit.
  • the test command can be parameterized.
  • the predetermined sequence of operations to be performed by the integrated circuit due to the receipt of the test command can be specified, in particular also which of the consumers are to be controlled in parallel or sequentially, how often and in what order to simulate a maximum power consumption of the integrated circuit or a typical power consumption in active mode.
  • a parameter of the test command indicates an approved number of repetitions of the waiting time extension signal, which may not be exceeded as an additional prerequisite for the generation of the signal for signaling the existence of the test by the terminal.
  • Embodiments of the invention are particularly advantageous since the integrated circuit test can be performed even before the personalization of the non-volatile electronic memory and is nevertheless meaningful, so that defective integrated circuits can be sorted out at an early stage of the production process.
  • a test can be carried out already before the document body is formed, in particular when the integrated circuit and its antenna are on a support which is tested prior to the formation of the document body.
  • Embodiments of the invention are also particularly advantageous in that the execution of the test command by the integrated circuit simulates the operation even though, prior to the personalization of the protected non-volatile electronic memory, execution of at least some of the smart card commands that are used to perform cryptographic functions, due to a corresponding configuration of the integrated circuit, in particular of its operating system, is not possible.
  • Such a configuration of the electronic circuit is advantageous in order to ensure the highest possible level of security by only after completion of the personalization process external access to the protected non-volatile electronic memory is enabled.
  • the integrated circuit has a non-volatile program memory in which first and second program instructions are stored.
  • the execution of the first program instructions can be started only with the strigkommando, whereas the execution of the second program instructions due to another chip card command in the active mode, that is, after the personalization can be done.
  • the smart card command is a command for initiating an external read access to the protected non-volatile electronic memory, for example from a chip card terminal or from an eID provider computer system via the Internet.
  • a command invokes a cryptographic function of the document implemented by the second program instructions to verify the fulfillment of a cryptographic access condition for the requested external access by performing the cryptographic function.
  • Such a cryptographic function can be, for example, a challenge-response protocol, symmetric or asymmetric encryption and / or decryption, one or more Diffie-Hellman key exchanges, for example for carrying out the PACE protocol, in particular one or more point point multiplications on an elliptic curve and or the generation of a pseudorandom random number or a combination of two or more such cryptographic operations.
  • Such cryptographic operations are generally relatively computationally intensive and require a correspondingly relatively high amount of energy for inclusion by the integrated circuit. If, on the other hand, the power coupled into the circuit is relatively low, depending on the embodiment, this can lead to the Cryptographic function is either not, not completely or very slowly performed, the latter in particular when the integrated circuit controls its clock rate depending on the injected power.
  • a low coupled power then leads to a low clock rate, which in turn has a correspondingly slow implementation of the cryptographic function result.
  • the execution of the cryptographic function in operative operation by the first program instructions in terms of power consumption and the associated processing speed.
  • such a simulation of the power consumption of the integrated circuit takes place in that a predetermined volume of pseudo-random data is generated and encrypted by the first program instructions, this being done in a working memory of the integrated circuit, since the first program instructions are not based on the protected non-volatile electronic memory to ensure maximum security.
  • the cryptographic parameters required to perform the encryption of the pseudorandom data are fixed and stored in a non-volatile electronic memory of the integrated circuit, so that the same processing steps are always performed for a consistent test to carry out the first program instructions.
  • a consumer is part of the integrated circuit or connected to the integrated circuit.
  • the load is switched on or off several times to simulate the power consumption of the load in active operation. Only if the power consumption in the test is sufficient, the integrated Circuit within the tolerance range send the test response after the consumer has been turned on and off one or more times by execution of the test command.
  • the consumer is a display device, which may be formed as a separate component or as part of the integrated circuit, as it is in itself WO 2011/023577 is known.
  • the consumer may be a sensor, in particular a biometric sensor for acquiring biometric data for authentication of a user to the integrated circuit, such as a fingerprint sensor or a camera for performing face biometry or Capture of an iris scan of the user.
  • a biometric sensor for acquiring biometric data for authentication of a user to the integrated circuit, such as a fingerprint sensor or a camera for performing face biometry or Capture of an iris scan of the user.
  • the integrated circuit is tested after it has been applied to a carrier together with its antenna.
  • the antenna is printed with a Silberleitpaste on the support.
  • the connection contacts of the integrated circuit are electrically contacted with the antenna, for example, with a conductive adhesive or another connection technique, wherein the integrated circuit can be simultaneously connected to the carrier.
  • the integrated circuit may be a chopped or ungated circuit, in particular a so-called bare die.
  • a first test of the integrated circuit takes place before the application of the integrated circuit to the carrier and / or before its connection to the antenna.
  • the connection contacts of the integrated circuit for example their contact pads, are contacted by measuring contacts, in particular so-called chip probes, in order to carry out the test.
  • the second tolerance range used for this initial test of the integrated circuit is preferably smaller than the first tolerance range that is used after the circuit has already been connected to the antenna, since the response of the integrated circuit via the measuring contacts in general will be faster than when coupled through the antenna.
  • the carrier on which the integrated circuit and its antenna are formed layered.
  • a multilayer document body is then formed to produce a document, for example by laminating layers.
  • the test of the integrated circuit takes place again after the document body has been produced. Only after this final check is the personalization of the non-volatile electronic memory carried out.
  • Embodiments of the invention are particularly advantageous because integrated circuits that do not meet the quality requirements with regard to their contactless RF interface and / or their antenna and / or the electrical contacting of the antenna with the RF interface, respectively at an early stage in the production process Documents can be detected and sorted out. This increases the overall throughput in the production of documents and the cost of rejects are reduced because a significant proportion of non-quality copies of the integrated circuit are sorted out either before application to the carrier or before the formation of the document body.
  • the invention relates to a corresponding document.
  • Embodiments of such a document are particularly advantageous, since the document is on the one hand completely verifiable even before its personalization, namely by performing the execution of a predetermined sequence of operations by the integrated circuit using the strigkommandos to simulate the power consumption in active mode, and this on the other without compromising the security of the document, since the integrated circuit, such as its operating system, is configured so that execution of the test command is possible only in the first unpersonalized state. On the other hand, if the integrated circuit receives the test command in the second personalized state, it will not be executed and no valid test response will be given.
  • the invention relates to a test system having a terminal and an embodiment of a document according to the invention.
  • the integrated circuit of the document is checked before personalization by the terminal coupling energy and sending the test command. If the time between the transmission of the test command and the receipt of the test response is within the tolerance range, the terminal generates a signal which signals the passing of the test or, in the contrary case, a signal which signals that the test was not passed.
  • the invention relates to a personalization system comprising a test system according to the invention and a personalization device.
  • the personalization device receives the signal from the test system that the integrated circuit has passed the test, the personalization device personalizes the protected non-volatile electronic memory of the integrated circuit, for example by providing one or more attributes concerning the document owner, such as for example its name, address, date of birth and / or attributes concerning the document itself, such as for example, its period of validity or the issuing authority, are stored in the protected non-volatile electronic memory.
  • the electronic circuitry Upon completion of this personalization, the electronic circuitry is irreversibly transitioned to its second personalized state such that the test command is no longer executable by the integrated circuit and the execution of other smart card commands is enabled, in particular to perform a cryptographic function to test a cryptographic access condition for to allow external access to the personalized non-volatile electronic memory.
  • the FIG. 1 shows an embodiment of an integrated circuit, which is designed here as a chip 100.
  • the chip 100 includes a microprocessor 102, for example a central processing unit (CPU), with a working memory 104, that is a so-called Random Access Memory (RAM).
  • a microprocessor 102 for example a central processing unit (CPU)
  • CPU central processing unit
  • RAM Random Access Memory
  • the chip 100 further has a nonvolatile electronic memory whose memory contents are fixed, that is, a so-called read only memory (ROM) 106.
  • ROM read only memory
  • a smart card operating system (COS) 108 or at least substantial parts thereof are invariably introduced into the ROM 106 during the manufacture of the chip 100 via a so-called ROM mask.
  • the smart card operating system 108 includes first program instructions 110 and second program instructions 112.
  • the chip 100 further has a personalizable and protected non-volatile electronic memory, such as an Electrically Erasable Programmable Read-Only Memory (EEPROM) 114, in which the integrated circuit is incorporated in a personalization of the integrated circuit or document Attributes 116 may be stored that are vulnerable, for example, personal information about the owner of the document, its biometric features or attributes of the document itself. At least some of these attributes 116 may only be read out of the document by a legitimate authority in the operative operation of the document after prior authentication and authorization checking.
  • EEPROM Electrically Erasable Programmable Read-Only Memory
  • the EEPROM 114 has a status register 118 indicating whether the chip 100 is in its first unpersonalized state or in its second personalized state.
  • the contents of the status register 118 are logic "0" in the first unpersonalized state and "1" in the second personalized state.
  • the ROM 106 and the EEPROM 114 are connected to the microprocessor 102 via an internal data and command bus 120 of the chip 100. An access to the ROM 106 and the EEPROM 114 can thus be made exclusively by the microprocessor 102 in order to ensure effective protection against unauthorized external accesses.
  • the chip card operating system 108 of the chip 100 is configured such that an execution of the first program instructions 110 is basically only possible when the chip 100 is in its first state, that is, when the content of the status register 118 is logic 0. In this non-personalized state, however, an execution of the second program instructions 112 for the execution of other chip card commands is not possible.
  • the smart card operating system 108 is configured so that execution of the first program instructions 110 is basically not possible when the chip is in its second state, that is, when the content of the status register 118 is logic 1. In this case, however, the execution of the second program instructions 112 for executing smart card commands is possible.
  • the chip 100 has a contactless RF interface 122 through which, for example, an RFID or NFC communication method is implemented.
  • the RF interface 122 also serves to couple the power required for the operation of the chip 100.
  • the RF interface 122 has a circuit 126 in order to obtain a supply voltage for the chip 100 from the carrier wave coupled in via an antenna 124. Further, the RF interface 122 has a circuit 128 with a demodulator for demodulating the carrier wave 142 to receive smart card commands and a modulator to send responses to smart card commands.
  • the antenna 124 is located on a carrier 130.
  • the carrier 130 is a plastic layer onto which the antenna 124 with one or more antenna windings is applied, for example by printing with a silver conductive paste.
  • the chip 100 has contact points, for example so-called pads 132, to which the antenna 124 is electrically connected to contacts 134.
  • This contacting can be, for example, an anisotropically conductive adhesive (anisotropic conductive adhesive - ACA) act as it is, for example DE 10 2010 028 444 A1 is known.
  • a resonant circuit is formed, which must have a suitable Q and resonant frequency to allow communication between a terminal 136 and the chip without contact and for couple the operation of the chip 100 required power.
  • This requires a suitable impedance of the antenna 124, a suitable resistance and capacitance of the contacts 134, a suitable contact resistance of the pads 132 and compliance with a predetermined input impedance of the RF interface 122 ahead.
  • the microprocessor 102 may have a controller 138 which, depending on the level of the supply voltage applied to the microprocessor 102 by the RF interface 122, controls a clock, that is to say a so-called clock 140 of the chip, so that the Clock 140 outputs a clock signal at a lower supply voltage at a lower frequency than is the case with a higher supply voltage.
  • the antenna may also be located on another layer that is connected to the carrier 130, for example via a via, to form the resonant circuit with the chip 100.
  • the composite of this other layer and the carrier 130 is tested with the chip 100.
  • the terminal 136 includes a tester 152 with a timer 154. By sending the test command 154, the timer 154 of the tester 152 is started, and by receiving the test response 148, the timer is stopped.
  • the resulting timer value indicates the length of time between the sending of the test command 144 and the receipt of the test response 148 and is characteristic of the processing speed at which the chip 100 has executed the first program instructions 110 and thus the clock rate which is determined by the power consumption and so that the quality of the resonant circuit is given.
  • the test apparatus 152 checks whether the resulting timer value lies within a tolerance range 156 stored in the test apparatus 152.
  • the tester 152 outputs a first signal 158 to a personalization device 160; in the opposite case, the tester 152 outputs a second signal 162 to the personalization device, whereafter the chip 100 is waste.
  • the personalization router accesses its memory 164 to read out the attributes 116 stored therein for the personalization of the chip 100 and into the memory EEPROM 114 to write.
  • the transfer of the attributes 116 stored in the memory 164 into the EEPROM 114 from the personalization device 160 may be contact-based, or via the terminal 136, which sends the attributes 116 to the chip 100 so that they can be read by the microprocessor 102 via the bus 120 in the EEPROM 114, which allows the smart card operating system 108 only as long as the status register 118 still has the logic value 0.
  • the smart card operating system 108 Upon completion of the transfer of the attributes 116 from the personalization device 160 to the chip 100 and after their storage in the EEPROM 114, the smart card operating system 108 sets the status register 118 to logic 1, thereby "completing" the EEPROM 114, that is, hereafter External access to the EEPROM 114 only after examination of a cryptographic access condition by execution of a corresponding chip card command, that is, the second program instructions 112 done.
  • one or more cryptographic parameters 166 are also stored in the ROM 106.
  • the smart card operating system 108 accesses these cryptographic parameters 166 to execute the first program instructions 110.
  • This can be, for example, a symmetric key for encrypting the data supplied by the pseudo-random generator 146, an asymmetric key pair and / or domain parameter for an elliptic curve cryptography.
  • the parameter or parameters 166 may also be stored in the EEPROM 114.
  • the second program instructions 112 implement a cryptographic protocol to check the fulfillment of a cryptographic condition that is a prerequisite for external read access to the attributes 116 stored in the EEPROM 114.
  • a cryptographic protocol to check the fulfillment of a cryptographic condition that is a prerequisite for external read access to the attributes 116 stored in the EEPROM 114.
  • the generation a challenge, an encryption or decryption with a symmetric or asymmetric key, a Diffie-Hellman key exchange and / or a point multiplication on an elliptic curve or a combination of two or more such cryptographic operations, in particular for implementing a Basic Access Control (BAC ) and / or Extended Access Control (EAC) and / or a PACE protocol or another challenge-response protocol and / or another protocol for authentication and / or authorization check as a prerequisite for reading one or more of the attributes 116 from the EEPROM 114.
  • BAC Basic Access Control
  • EAC Extended Access Control
  • PACE protocol another challenge-re
  • the chip 100 may include one or more consumers that may be driven by the microprocessor 102. This may be, for example, a display device 168, that is to say a so-called display, and / or a sensor 170, for example a biometric sensor.
  • the first program instructions 110 may be designed such that the display device 168 and / or the sensor are executed by the microprocessor 102 170 to be turned on and off, so as to simulate the power consumption in the active operation of the chip.
  • the first program instructions 110 may also be designed in this case to simulate the power consumption for the execution of the second program instructions 112 in the active mode.
  • the chip 100 may include or may be connected to one or more other or other consumers. This can happen for example, a non-volatile memory, a hardware random number generator, a hardware coprocessor, in particular a hardware coprocessor for symmetric and / or asymmetric cryptographic methods, a computing unit and / or a memory management unit act.
  • the test command 144 may be parameterizable to specify the sequence of operations to be performed on the basis of the test command, for example with regard to the consumers to be switched on and off.
  • the tolerance range 156 is selected by the tester 152 as a function of the parameterization of the test command 144.
  • the testing device 152 may include, for example, a so-called look-up table in which each possible choice of parameters for the strigkommando 144 is assigned a tolerance range 156, in which the time between the transmission of the corresponding parameterized fürkommandos 144 and the receipt of the test response 148 then sent must fall so that the signal 158 is delivered.
  • the attributes 116 include a passport photo or a sequence of passport photos of the owner of the document.
  • the microprocessor 102 accesses the image data stored in the EEPROM 114 in order to output it via the display device 168.
  • the display of an image sequence on a display device of a document is as such WO 2009/053249 A1 known.
  • biometric authentication may be provided additionally or alternatively to an authentication by means of a PIN.
  • the carrier 130 may be, for example, a plastic film made of a polymer such as polycarbonate, a paper layer or a composite of a paper and a polymer layer.
  • the antenna windings of the Antenna 124 are applied to the carrier 130, for example by printing with a Silberleitpaste.
  • the chip 100 is applied to the carrier 130, for example as a chip module or as a so-called bare die.
  • the attachment and electrical contacting of the chip 100 to the antenna 124 may be accomplished by per se known bonding techniques, such as an anisotropic conductive adhesive.
  • the chip 100 and its resonant circuit are tested as shown above. If the test shows that the chip 100 passes the test, then the carrier 130 is joined together with one or more further paper and / or plastic-based layers to form a multilayer document body, for example by lamination, cf. for example DE 10 2007 052 948 A1 ,
  • the chip 100 is designed to output a waiting time extension signal, that is to say a so-called WTX signal 172.
  • a corresponding function can be provided in the chip card operating system 108. If the power coupled into the chip 100 via the carrier wave 142 is relatively low and thus the clock rate generated by the clock 140 is relatively slow, the chip 100 generates the WTX signal 172 to signal the terminal 136 that the wait time is up to extend the response to the previously sent chip card command.
  • the carrier wave 142 coupled in to test the chip 100 will lead to the coupling of a relatively low power and thus to a low clock rate of the clock 140.
  • the terminal sends the test command 144
  • the chip 100 becomes 100 - each according to embodiment - then send the WTX signal 172 via the RF interface 122 to request an extension of the waiting time for the test response 148 from the terminal 136.
  • the receipt of the WTX signal 172 by the terminal 136 signals the terminal 136, however, that the coupling of the power into the chip 100 is not sufficient, so that the chip 100 or the carrier 130 with the chip thereon and the antenna 124 or the document body is considered as a scrap and the terminal 136 then outputs the signal 162 signaling this.
  • the chip 100 is configured to generate a field strength increase signal 174 and output via the RF interface 122 in order to request from the terminal 136 an increase in the field strength with which the carrier wave 142 is transmitted. Such a signal is then generated by the chip 100 when the coupled power is relatively low, which manifests itself, for example, in a relatively low clock rate of the clock 140.
  • the terminal 136 receives the field strength increase signal 174, the signal 162 is generated because the receipt of the field strength increase signal 174 indicates that the resonant circuit of the chip 100 does not meet the quality requirements.
  • the FIG. 2 shows an embodiment of a method for testing an integrated circuit for the production and personalization of a document.
  • a first test first the unoccupied chip 100 is tested before it has been connected to its antenna 124.
  • the pads 132 of the chip are contacted with measuring contacts, that is to say the so-called probes, in order, for example, to connect them electrically to the terminal 136.
  • electrical energy is then coupled via these measuring contacts into the chip 100, so that the clock 140 starts oscillating and the microprocessor 102 begins to operate.
  • the test command 144 is then sent via the measuring contacts to the chip 100 and executed there in the step 206, since the chip 100 in FIG his unpersonalized state.
  • the timer 154 is started.
  • the test response 148 generated by the chip 100 due to the execution of the test command 144 is then received via the sense contacts in step 208, the timer 154 is stopped, and the time between transmit and receive is detected by reading the timer value.
  • the timer 154 is thereby reset.
  • step 210 a check is then made as to whether the time duration between the transmission of the test command and the step 204 of the reception of the test response 208 lies within a first tolerance range. If this is not the case, the chip 100 is rejected and the test method is aborted in step 210.
  • step 212 the resonant circuit is produced by applying the antenna 124 and the chip 100 to the carrier 130. Subsequently, in step 214, energy is coupled via the carrier wave 152 into the resonant circuit, so that the clock 140 starts up again and the microprocessor 102 begins to operate. In step 216, the test command 144 is sent from the terminal 136 and executed by the chip 100 in step 218 because it is still in its first unpersonalized state.
  • step 220 the terminal 136 receives the test response 148 from the chip 100 and the time duration is detected by the timer 154 analogous to step 208. It is then checked in step 222 whether the time duration between the transmission of the test command 144 and the receipt of the test response 148 is within a second tolerance range. If this is not the case, the prepared carrier 130 is rejected and the test is terminated in step 224.
  • step 226 the document body of the document is made by placing the carrier 130 with one or more paper and / or paper plastic-based layers, for example by lamination is connected. Thereupon, a check of the chip 100 and its resonant circuit is performed again by executing steps 228, 230, 232, 234 and 236, which are carried out analogously to steps 214 to 222, wherein it is checked in step 236 whether the time period within a third Tolerance range, which may be identical to the second tolerance range.
  • step 238 If this check reveals that the time period is not in the third tolerance range, the produced document body is rejected and the check is aborted in step 238.
  • the test device 152 of the terminal 136 signals that the produced document body has passed the test, so that the personalization device 160 then personalizes the protected non-volatile electronic memory, ie the EEPROM 114.

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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Storage Device Security (AREA)
  • Credit Cards Or The Like (AREA)
EP16166301.8A 2015-04-28 2016-04-21 Procede de controle d'un circuit integre, document, systeme de controle et dispositif de personnalisation Active EP3089077B1 (fr)

Applications Claiming Priority (1)

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DE102015207745.4A DE102015207745A1 (de) 2015-04-28 2015-04-28 Verfahren zur Prüfung einer integrierten Schaltung, Dokument, Prüfsystem und Personalisierungsvorrichtung

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EP3089077A1 true EP3089077A1 (fr) 2016-11-02
EP3089077B1 EP3089077B1 (fr) 2018-09-12

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112965853A (zh) * 2021-02-26 2021-06-15 星汉智能科技股份有限公司 智能卡的数据存储及校验方法、装置及介质

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WO2009027240A1 (fr) 2007-08-30 2009-03-05 Bundesdruckerei Gmbh Compteur d'utilisations pour carte à puce
WO2009053249A1 (fr) 2007-10-19 2009-04-30 Bundesdruckerei Gmbh Document avec un dispositif d'affichage, appareil de lecture et procédé de lecture d'un document
DE102007052948A1 (de) 2007-10-31 2009-05-07 Bayer Materialscience Ag Verfahren zur Herstellung eines Polycarbonat-Schichtverbundes
EP2234030A2 (fr) * 2009-03-25 2010-09-29 Bundesdruckerei GmbH Carte à puce, système informatique, procédé d'activation d'une carte à puce et procédé de personnalisation d'une carte à puce
WO2011023577A1 (fr) 2009-08-28 2011-03-03 Bundesdruckerei Gmbh Document à affichage intégré et son procédé de fabrication
WO2011030947A1 (fr) 2009-09-08 2011-03-17 Lim Dong Gi Dispositif portatif pour traiter l'atopie
DE102010028444A1 (de) 2010-04-30 2011-11-03 Bundesdruckerei Gmbh Dokument mit einem Chip und Verfahren zur Herstellung eines Dokuments
DE102012022735A1 (de) * 2012-11-21 2014-05-22 Giesecke & Devrient Gmbh Verfahren zum Betreiben eines Kommunikationssystems

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Publication number Priority date Publication date Assignee Title
WO2009027240A1 (fr) 2007-08-30 2009-03-05 Bundesdruckerei Gmbh Compteur d'utilisations pour carte à puce
WO2009053249A1 (fr) 2007-10-19 2009-04-30 Bundesdruckerei Gmbh Document avec un dispositif d'affichage, appareil de lecture et procédé de lecture d'un document
DE102007052948A1 (de) 2007-10-31 2009-05-07 Bayer Materialscience Ag Verfahren zur Herstellung eines Polycarbonat-Schichtverbundes
EP2234030A2 (fr) * 2009-03-25 2010-09-29 Bundesdruckerei GmbH Carte à puce, système informatique, procédé d'activation d'une carte à puce et procédé de personnalisation d'une carte à puce
WO2011023577A1 (fr) 2009-08-28 2011-03-03 Bundesdruckerei Gmbh Document à affichage intégré et son procédé de fabrication
WO2011030947A1 (fr) 2009-09-08 2011-03-17 Lim Dong Gi Dispositif portatif pour traiter l'atopie
DE102010028444A1 (de) 2010-04-30 2011-11-03 Bundesdruckerei Gmbh Dokument mit einem Chip und Verfahren zur Herstellung eines Dokuments
DE102012022735A1 (de) * 2012-11-21 2014-05-22 Giesecke & Devrient Gmbh Verfahren zum Betreiben eines Kommunikationssystems

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN112965853A (zh) * 2021-02-26 2021-06-15 星汉智能科技股份有限公司 智能卡的数据存储及校验方法、装置及介质

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DE102015207745A1 (de) 2016-11-03

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