EP3085027B1 - Communication node for a packet-switched data network, and a method for operating same - Google Patents

Description

The invention relates to a communication node for a packet-switched data network comprising an integrated circuit with a system of electronic components for transmitting and / or receiving audio and / or video data, in particular an audio and / or video data stream. The invention further relates to a method for operating such a communication node.

An integrated circuit having a system of electronic components is known as system-on-a-chip (SoC). In such a system, all or large parts of the functions of the system are arranged on a single chip, ie an integrated circuit. A system is to be understood here as a combination of different elements, such as logic circuits, clocking, and the like, which together provide a specific functionality. Such integrated circuits are used, for example, in embedded systems. A possible application of SoCs is, for example, the transmission and / or reception of audio and / or video data (so-called streaming).

The term "Audio Video Bridge" (AVB) is a set of standards according to IEEE 802.1 for synchronized and prioritized streaming of audio and video data over networks. Among other things, AVB consists of the standards IEEE 802.1AS ( Timing and Synchronization for Time-Sensitive Applications (gPTP)) and IEEE 802.1Qav ( Forwarding and queuing for time-sensitive streams ). In addition, the IEEE AVTP) has been achieved in AVB 1722 (Transport Protocol for Time-Sensitive Applications (Audio Video Transport Protocol, shall apply. AVB allows a packet-switched data network, such as Ethernet-based networks, for duplex transmission of many audio Time synchronization between the communication nodes connected to the data network is effected via time information.As AVB uses existing standard Layer 2 MACs ( media access controllers ) and bridges, backward compatibility between communication nodes, the AVB, and communication nodes that do not use AVB, are enabled, so that they can communicate over conventional trained according to the standard IEEE 802 frame.

To allow a communication node to use AVB, various changes to the hardware and software of the communication node are required. For example, the IEEE 802.1AS standard requires a more accurate timestamp of incoming or outgoing data packets. Timestamping is typically implemented within a modified media access control (eg, Ethernet MAC) component of the integrated circuit (SoC). This ensures that the time of transmission of the data packet is as close as possible to the time of the time stamping. For this reason, this functionality is usually implemented in hardware (hardware assisted time stamping). The generation of synchronization messages as well as messages in terms of propagation delays and the like, on the other hand, in the media access control component are provided as software.

A queue management unit described in the IEEE 802.1Qav standard is generally implemented as FIFO (first in - first out). As a result, data packets are output according to specific criteria to a communication line of the data network to which the communication node is connected. However, this requires some computing power to meet the real-time requirements of AVB.

The WO 2013/126630 A1 discloses a communication node for a packet-switched data network comprising an integrated circuit having a system of electronic components for transmitting and / or receiving audio and / or video data. As components of the system, a media access control component (MAC) for implementing a media access control and a physical interface (PHY) with transmitting and receiving means, via which the communication node is connectable to a communication line of the data network, are provided. The media access control component is connected to the physical interface for exchanging data. The system further includes a time management module.

The DE 10 2005 037 376 B3 discloses an Ethernet controller wherein a device for time stamping packets is located between a media access control layer (MAC layer) and a physical layer (PHY layer).

The publication JOHAS TEENER MICHAEL D ET AL: "Heterogeneous Networks for Audio and Video: Using IEEE 802.1 Audio Video Bridging", PROCEEDINGS OF THE IEEE, IEEE, NEW YORK, US, Vol. 101, No. 11, Nov. 1, 2013, pages 2339 -2,354 discloses a protocol stack for a communication node.

It is an object of the present invention to provide a communication node for a packet-switched data network, which is fully adapted for the use of AVB and at the same time allows a reduced processing load of the media access control component in meeting all real-time requirements. In this case, the communication node should be backwards compatible and also able to communicate with other communication nodes that do not control AVB. It is a further object of the invention to specify a method for operating such a communication node.

This object is achieved by a communication node according to the features of claim 1 and a method according to the features of claim 13. Advantageous embodiments result from the dependent claims.

To achieve this object, a communication node for a packet-switched data network is proposed which comprises an integrated circuit with a system of electronic components for transmitting and / or receiving audio and / or video data. The packet-switched data network is in particular the Ethernet or based on Ethernet.

In particular, the integrated circuit comprises a system of electronic components for transmitting and / or receiving an audio and / or video data stream (so-called stream). Such an integrated circuit with a system of electronic components is for example in the form of a SoC. As components of the system, at least one media access control component for implementing a media access control and a physical interface with transmitting and receiving means, via which the communication node can be connected to a communication line of the data network, are provided. The media access control component is, for example, an Ethernet MAC. The physical interface is designed, for example, in the form of an Ethernet PHY. This is a special integrated circuit or functional group of circuitry responsible for encoding and decoding data between a purely digital system and a modulated analog system.

The media access control component is connected to the physical interface for exchanging data via an internal first interface. The system further includes a real-time clock synchronization unit for synchronizing time information with other communication nodes of the data network and a queue management unit. According to the invention, the real-time clock synchronization unit and the queue management unit are arranged completely in the physical interface.

In the proposed communication node, the integrated circuit is relieved of all real-time requirements caused by AVB. The functionality relating to AVB is instead located in the physical interface. This allows for backwards compatibility as well as a more cost effective realization of an AVB communication node, since the design of an AVB compliant integrated circuit is much more expensive than providing the physical interface, which is typically separately located in the communication node, with the necessary components and functionalities. By replacing a conventional physical interface with an interface proposed according to the invention, a communication node can be made AVB-compatible.

The fact that the physical interface handles all tasks relating to AVB in real time considerably reduces the interrupt load of the integrated circuit caused by AVB. As a further advantage, the internal first interface present between the physical interface and the media access control component is available exclusively for the transmission of data packets (with payload). This means that the bandwidth available via the internal, first interface is increased in comparison with conventional communication nodes, in which AVB tasks are taken over by the media access control component.

According to an expedient embodiment, the media access control component has no functionality of the real-time clock synchronization unit and the queue management unit. This can be avoided by the AVB interrupt requests to the integrated circuit. In addition, the backward compatibility of the communication node is improved.

According to a further expedient embodiment, the real-time clock synchronization unit in the physical interface is based on the IEEE 802.1AS standard and has implemented its complete functionality.

According to a further expedient embodiment, a first part of the functionality of the real-time clock synchronization unit in the physical interface is realized as hardware, by means of which a, in particular independent, time synchronization with further communication nodes of the data network can be carried out. The realized as hardware functionality of the real-time clock synchronization unit relates in particular to the provision of incoming and outgoing data packets with time stamps according to the specifications of AVB. Stand-alone time synchronization is understood to mean that there is no communication between the physical interface and the media access control component for the purpose of fulfilling the intended functionality of the hardware.

In a further expedient refinement, a second part of the functionality of the real-time clock synchronization unit in the physical interface is realized in software for implementing a measurement of propagation delays and / or the transmission of information for a time synchronization and / or the selection of one of the communication nodes of the data network as master -Node. This information is used by the communication nodes connected to the data network for time synchronization.

According to a further expedient refinement, the real-time clock synchronization unit in the physical interface comprises at least one register into which one or more time information determined by the real-time clock synchronization unit is stored during operation of the communication node, wherein the at least one register is stored by the media access control component and / or another Component of the system via the first interface is readable. In one of the registers, for example, the local time of the communication node is stored, which is synchronized with a master time (the so-called grandmaster clock).

The first interface over which data is exchanged between the media access control component and the physical interface within the communication node is conveniently the Media Independent Interface (MII).

According to a further expedient embodiment, the real-time clock synchronization unit can be configured as a master node or as a slave node by storing predetermined information in a predetermined register during operation of the communication node, which information is passed through the media access control component and / or another component of the system first interface is readable. This will result in no communication with the media access control component or any other component of the system require time synchronization between the nodes of the packet-switched data network.

According to a further embodiment, the physical interface may comprise an apparatus for coding and / or decoding audio data, in particular according to the specification IEEE 1722 Transport. This device (codec) makes it possible to stream and decode audio data from another communication node, so that the corresponding data can optionally be processed by a component of the integrated circuit or another, external audio component without further processing. Such a component may be, for example, a sound card within the integrated circuit of the communication node or another external audio terminal (for example, MP3 player).

The device for encoding and / or decoding audio data can be coupled to the system or to an external audio component for the direct exchange of data according to another embodiment via a second interface. In particular, the second interface may be a serial audio interface, such as I ² S.

According to a further embodiment, the queue management unit is set up to execute the leaky bucket algorithm. In particular, in the presence of the optional second interface, the queue management unit processes the data received via the second interface and from the first interface according to the algorithm used. By providing the second interface for the transmission of audio data, moreover, the bandwidth can be further increased via the first interface. Since, according to the invention, the management of the queue is no longer carried out in the integrated circuit (SoC) but in the physical interface, the computing load for the integrated circuit, in particular for the media access control component, considerably lowered. The saved computing power can therefore be provided by the integrated circuit for other tasks.

In order to achieve the object, a method is also proposed for operating a communication node for a packet-switched data network, wherein the communication node is designed in accordance with the above-described description. In the method according to the invention, only the real-time clock synchronization unit arranged in the physical interface performs a, in particular independent, time synchronization with further communication nodes of the data network as well as a measurement of propagation delays and / or transmission of information for a time synchronization and / or selection of one of the communication nodes of the data network Master node through.

The method according to the invention combines the same advantages as described above in connection with the communication node according to the invention.

The term "exclusive" is understood to mean that the media access control component or the integrated circuit or a component of the integrated circuit are not involved in performing these functions and tasks. In particular, there is no communication between the physical interface and the integrated circuit to accomplish the above tasks.

According to another embodiment of the proposed method, the queue management unit issues data packets received from the first and second interfaces from the system or, optionally, from the external audio component to the communication line of the data network for transmission according to certain criteria.

According to a further embodiment of the method according to the invention, the real-time clock synchronization unit stores one or more time information in one or a respective register for accessing the one or more time information of the media access control component and / or the other component of the system via the first interface through a read access to provide the register or registers for processing.

In a further embodiment of the method according to the invention, the real-time clock synchronization unit writes a predetermined information in a predetermined register, wherein the predetermined information indicates whether the communication node is configured as a master node or a slave node, wherein the predetermined register by a read access the media access control component and / or another component of the system is readable via the first interface.

Fig. 1

eine schematische Darstellung eines paketvermittelten Datennetzwerks mit mehreren Kommunikationsknoten, wobei einer der Kommunikationsknoten in herkömmlicher Weise zur Durchführung von AVB ausgebildet ist;

Fig. 2

eine schematische Darstellung eines AVB-Software-Stacks;

Fig. 3

eine schematische Darstellung eines paketvermittelten Datennetzwerks mit einem erfindungsgemäß ausgebildeten Kommunikationsknoten gemäß einer ersten Ausgestaltungsvariante; und

Fig. 4

eine schematische Darstellung eines paketvermittelten Datennetzwerks mit einem erfindungsgemäß ausgebildeten Kommunikationsknoten gemäß einer zweiten Ausgestaltungsvariante.

The invention will be described in more detail below with reference to embodiments in the drawing. Show it:

Fig. 1

a schematic representation of a packet-switched data network with a plurality of communication nodes, wherein one of the communication nodes is formed in a conventional manner for performing AVB;

Fig. 2

a schematic representation of an AVB software stack;

Fig. 3

a schematic representation of a packet-switched data network with an inventively designed communication node according to a first embodiment variant; and

Fig. 4

a schematic representation of a packet-switched data network with an inventively designed communication node according to a second embodiment variant.

Fig. 1 shows a schematic representation of a packet-switched data network with multiple communication nodes 16. In the embodiment, the data network is based on Ethernet. The communication nodes 16, also known as Ethernet AVB or EAVB nodes ("EAVB Node") are connected via lines 12 to an Ethernet AVB Bridge ("EAVB Bridge") 14. In this example, three communication nodes 16 are shown. The number can also be different in practice, in particular larger. Lines 12 are representative of wireline or wireless communication channels. The communication nodes 16 of the packet-switched data network are designed in this example to perform AVB. For the sake of simplicity, the components required for this purpose are shown only for one of the communication nodes 16. Also, communication nodes 16 that are not configured to perform AVB may be connected to the EAVB bridge 14.

The communication node 16 comprises an integrated circuit 2 in the form of a SoC ("system on a chip"), and a physical interface 6 in the form of an Ethernet PHY. The integrated circuit 2 and the physical interface 6 are connected via an internal, first interface 8 in the form of a MII ("Media Independent Interface") for exchanging data within the communication node 16.

The integrated circuit 2 includes electronic components on a common chip, such as digital components, analog components, mixed signal components, and radio frequency transmit (RF) functions. In the field of mobile devices or consumer electronics, the integrated circuit 2 is typically an embedded system.

It should be noted that in the present specification, an SoC is just one example of an integrated circuit. In the environment of desktop computers, a CPU is analogously connected to an Ethernet-over-PCI.

The integrated circuit 2 of the communication node 16 comprises a media access control component 4 (Ethernet MAC). In the media access control component 4, a device 21 implemented in hardware is provided for realizing AVB, which serves to provide data packets received by the communication node 16 or data packets to be transmitted from the communication node 16 to one of the other schematically represented communication nodes 16 with a respective time stamp. This functionality is called "PTP-Only Time Stamping". The remaining functionalities of IEEE 802.1AS (gPTP) are realized in software which also runs on the media access control component 4. These are, for example, functionalities for implementing a measurement of propagation delays and / or the transmission of information for a time synchronization and / or the selection of one of the communication nodes of the data network as a master node.

In addition, a queue management unit 20 ("Traffic Shaping") is provided in the media access control component 4, which delays or discards data packets to be sent by the communication node 16 to one of the further communication nodes 16 according to certain criteria in order to meet predetermined request profiles. One frequently used algorithm is the leaky bucket algorithm.

The media access control component 4 is generally a component that implements the Medium Access Layer 2 (Layer 2) MAC (Medium Access Controller) sub layer. The media access control component 4 is typically formed as part of the integrated circuit 2 and connected to other components of the integrated circuit via an internal system bus (not shown) Data connected. In the case of a CPU, the media access control component 4 is often implemented in an expansion card (for example, PCI card).

The media access control component 4 is connected to the physical interface 6 via the first internal interface 8 (MII). The physical interface 6 is often referred to as PHYceiver. This is a component that works on the physical layer. For example, the interface implements 1000Base-T, 100Base-T, and so on.

The first internal interface 8 is a standardized interface, which is connected to connect the media access control component 4 to the physical interface 6. Different variants are used in practice, such as RGMII ( Reduced Gigabit Media Independent Interface ) and SGMII ( Serial Gigabit Media Independent Interface ).

When talking about Ethernet in the present specification, this refers to the physical layer. Transmission may be via a coaxial cable, a twisted pair cable or a fiber optic cable. The speeds can vary between 10 Mb / s to 100 Gb / s. The protocol stack of Ethernet works in a similar way as other physical layers, with a definition given in the OSI layer model (ISO / IEC 7498-1).

The EAVB bridge 14 connects a plurality of communication nodes 16 with each other. The EAVB bridge 14 works similarly to the known Ethernet switches (switches). In addition, the EAVB Bridge supports 14 additional AVB features, such as PTP, Traffic Shaping, and Stream Reservation.

Each of the communication nodes 16 can act within the data network as a streaming source (English: AVB Talker) or streaming sink (English: AVB Listener). As described, the integrated circuit 2 and the physical Interface 6 as an embedded system (English: Embedded System) formed.

A like in Fig. 1 described AVB communication node 16 further includes a software AVB stack. This is schematic in Fig. 2 shown. The reference numeral 23 represents an application ("Application"). In the context of AVB, the application 23 represents a streaming application, optionally as a source or sink (talker or listener). Reference numeral 33 denotes an Ethernet driver according to the IEEE 802 ("IEEE 802 Ethernet Driver") standard. The driver 33 represents a driver of the media access control component 4. This typically writes Ethernet data packets from the TCP / IP stack 31 ("TCP / IP stack") to a memory of the media access control component 4, and vice versa. In the case of an AVB protocol, driver 33 is addressed directly because all AVB protocols are running on layer 2.

The reference numeral 25 ("IEEE 1722 transport") denotes a component disposed in the integrated circuit 2, typically outside the media access control component 4, which is responsible for integrating the transport layer realized according to IEEE 1722 into the present system architecture. For example, this is an ALSA sound driver that supports playback and recording under the Linux operating system.

The reference numeral 27 ("IEEE 802.1AS") denotes a software component which is for implementing a measurement of propagation delays, the transmission of information for time synchronization, and the selection of one of the communication nodes of the data network as a master node. This software component is typically located in the integrated circuit 2 and outside the media access control component 4.

The reference numeral 29 ("IEEE 802.1Qat") denotes a stream registration protocol which comprises three different signal protocols, viz MMRP, MVRP and MSRP, to realize a stream reservation in the data network with an EAVB bridge. The software component 29, which has no real-time requirements, is typically located in the integrated circuit 2 and outside the media access control component 4. Multiple Stream Registration Protocol (MSRP) is a signaling protocol that enables end nodes to reserve resources of the data network so that the transmission and reception of data streams across the entire data network is of a quality requested, QoS) is enabled.

Reference numeral 31 ("TCP / IP") denotes a set of in TCP / IP protocols. These can be, for example, IP, ARP, ICMP, UDP, TCP, IGMP. The TCP / IP stack is usually reserved for the operating system. It is, like the driver 33, arranged in the integrated circuit 2 from the point of view of the OSI-layer model above the media access control component 4.

By in the following embodiments according to Fig. 3 and 4 variants described, the integrated circuit 2 (SoC) can be freed from any real-time requirements introduced by AVB. The reference numeral 10 identifies, in contrast to the other communication node 16, an inventively designed communication node (EAVB node). For this purpose, according to the invention, the real-time clock synchronization unit 21 together with the associated software-controlled functionality (reference number 27 in accordance with FIG Fig. 2 ) and the queue management unit 20 are completely located in the physical interface 6. This makes it possible to integrate AVB in the communication nodes without having to modify the integrated circuit 2. This allows backward compatibility with non-AVB compliant communication nodes. One advantage is that AVB interrupt requests to the integrated circuit 2 are low. In the course of AVB applications, the integrated circuit 2 is also much less burdened, as the PTP time synchronization and the queue management be taken over by the physical interface 6. The same applies to the handling of data packets according to the standard IEEE 1722, provided that the corresponding functionality is optionally also provided in the physical interface 6.

It is understood that the relevant AVB software functionalities from the in Fig. 2 shown software stack of the integrated circuit 2 can be removed. This applies in particular to those designated by the reference numerals 25, 27 and 29 in FIG Fig. 2 marked software components. It is also clear that the in Fig. 1 20 and 21 identified hardware components are no longer included in the integrated circuit 2. The in Fig. 3 shown integrated circuit 2 does not support in the inventive manner AVB feature, that is, neither a queue management nor the insertion of time stamps in data packets. As described, these functionalities are implemented directly in the physical interface 6.

The inventively embodied real-time clock synchronization unit 18 within the physical interface 6 is responsible for the time synchronization with the other communication nodes 16. The other communication nodes 16 may be formed according to the invention or conventionally. Synchronization is performed in accordance with the IEEE 802.1AS standard in the following manner: one of the communication nodes 10, 16, which is a grandmaster node, sends information including a synchronized time to all other communication nodes 10, 16 of the data network. Each of these (AVB) communication nodes must correct the received time of the grandmaster node by taking into account a propagation time that takes into account the received data packet from the grandmaster node to the own communication node. To determine these, a forwarding delay and a transmission time are needed. The forwarding delay is the time required, like EAVB bridge 14, to process the particular data packet. The EAVB Bridges 14 can determine this time (residence time, English: residence time) itself.

The real-time clock synchronization unit 18 is responsible for determining the propagation delay. A corresponding result is stored in a register (not shown) of the physical interface 6. The integrated circuit 10 or one of its components can read this time from the register of the physical interface 6 by a read access via the first interface 8 for further processing. For example, MDIO, i. a specific interface called PHY Management Interface, to be used as part of the MII. The insertion of the time stamp in a PTP message is done directly by the real-time clock synchronization unit 18. The real time clock synchronization unit 18 also has a local clock time register which is synchronized with the grandmaster clock.

By a predetermined information in another register of the physical interface 6, the real-time clock synchronization unit 18 can be configured as master or slave.

All PTP messages are forwarded to the media access control component 4. This is necessary, for example, so that algorithms that are not real-time sensitive can run.

Is, as in the embodiments according to Fig. 3 and 4 1, the device 35 for encoding and / or decoding audio and / or video data according to IEEE 1722, the communication node 10 has a second internal interface 37 for transmitting serial audio data. The interface can be, for example, I ² S. An advantage of this approach is that the encoding or decoding of audio data in this case can be done directly in the physical interface 6 and the integrated circuit 2 is exempt from this computational burden. In addition, because the transmission of audio data via the second interface 37 takes place, wherein in the case of the integrated circuit 2 it is connected to a sound card contained therein, a high bandwidth is available via the first interface 8 for the transmission of user data.

The provided at a communication node 10 according to the invention first interface 8 (MII) includes all current and possible variants and future extensions, such as Reduced Media Independent Interface, Gigabit Media Independent Interface, Reduced Gigabit Media Independent Interface, Serial Gigabit Media Independent Interface, 10 Gigabit Media Independent Interface, XAUI, GBIC, SFP, SFF, XFP and XFI.

This in Fig. 4 embodiment shown differs from that in Fig. 3 shown embodiment in that the physical interface 6 is integrated into the integrated circuit 2. From a functional point of view, there are no differences.

Queue handling of data packets in accordance with IEEE 1722, ie audio and / or video data to be transmitted by the device 35 for encoding and / or decoding, as well as data packets received via the first interface 8 from the media access control component 4 are processed by the queue management unit 20 to meet certain requirement profiles to comply with the data flow. Also, the queue management unit 20 has one or more registers to make configurations for the queue flow. The queue management unit 20 is preferably realized in hardware.

LIST OF REFERENCE NUMBERS

2

integrated circuit (system-on-a-chip (SoC))

4

Media Access Control Component (Ethernet MAC)

6

physical interface (Ethernet PHY)

8th

first interface (MII - Media Independent Interface)

10

Communication node (EAVB node)

12

Ethernet cable

14

EAVB Bridge (Ethernet AVB Bridge)

16

further communication node (EAVB node)

18

Real-time clock synchronization unit

20

Queue Management Unit (Traffic Shaping)

21

Real-time clock synchronization unit with limited functionality

23

application

25

IEEE 1722

27

IEEE 802.1AS

29

IEEE 802.1Qat

31

TCP / IP

33

IEEE 802 Ethernet driver

35

Device for coding and / or decoding audio and / or video data (codec)

Claims (16)

1. A communication node (10) for a packet-switched data network, which comprises an integrated circuit (2) with a system of electronic components for sending and/or receiving audio and/or video data, particularly of an audio and/or video data stream, wherein at least a media access control component (4) for implementing a media access control and a physical interface (6) with transmitting and receiving means, by way of which the communication node (1) is connectable to a communication line (12) of the data network, are provided as components of the system, wherein the media access control component (4) is connected via an internal first interface (8) to the physical interface (6) for exchanging data, and wherein the system comprises a real-time clock synchronization unit (18) for synchronizing time information with other communication nodes (16) of the data network as well as a queue management unit (20),
   characterized in that
   the real time clock synchronization unit (18) and the queue management unit (20) are fully arranged in the physical interface (6).
2. The communication node according to claim 1, characterized in that the media access control component (4) does not have any functionality of the real time clock synchronization unit (18) and of the queue management unit (20).
3. The communication node according to claim 1 or 2, characterized in that the real time clock synchronization unit (18) is based on the standard 802.1AS and has implemented all of its functionalities.
4. The communication node according to claim 3, characterized in that a first part of the functionality of the real time clock synchronization unit (18) is carried out as hardware, by which time synchronization with other communication nodes (16) of the data network is, particularly autonomously, operable.
5. The communication node according to claim 3 or 4, characterized in that a second part of the functionality of the real time clock synchronization unit (18) is carried out as software for implementing a measurement of propagation delays and/or the transmission of information for time synchronization and/or choosing one of the communication nodes (10, 16) of the data network as a master node.
6. The communication node according to one of the afore-mentioned claims, characterized in that the real-time clock synchronization unit (18) comprises at least one register, in which a single or several pieces of time information determined by the real-time clock synchronization unit (18) are stored during operation of the communication node (10), wherein the at least one register is readable via the first interface (8) by the media access control component (4) and/or by another component of the system.
7. The communication node according to one of the afore-mentioned claims, characterized in that, the first interface (18) is the Media Independent Interface (MII).
8. The communication node according to one of the afore-mentioned claims, characterized in that the real-time clock synchronization unit (18) is configurable as master node or as slave node by storing a predetermined piece of information in a predetermined register during operation of the communication node (10), the information being readable by the media access control component (4) and/or by another component of the system via the first interface (8).
9. The communication node according to one of the afore-mentioned claims, characterized in that the physical interface (6) comprises a device (35) for encoding and/or decoding audio data, particularly according to the specification IEEE 1722 Transport.
10. The communication node according to claim 8, characterized in that the device (35) for encoding and/or decoding audio data is coupled via a second interface (37) with the system or with an external audio component for directly exchanging data.
11. The communication node according to one of the afore-mentioned claims, characterized in that the second interface (37) is a serial audio interface, particularly I²S.
12. The communication node according to one of the afore-mentioned claims, characterized in that the queue management unit (20) is configured to execute the leaky bucket algorithm.
13. A method for operating a communication node (10) for a packet-switched data network, wherein the communication node is designed according to one of the afore-mentioned claims, in which

    - only the real time clock synchronization unit (18) arranged in the physical interface (6) carries out a particularly autonomous time synchronization process with other communication nodes (16) of the data network as well as a measurement of propagation delays and/or transmission of information for time synchronization and/or choosing one of the communication nodes (10, 16) of the data network as a master node.
14. The method according to claim 13, wherein the queue management unit (20) outputs data packets, which are received from the first and second interface (8,37) by the system, or optionally by the external audio component, according to specific criteria, to the communication line (12) of the data network for transmission.
15. The method according to claim 13 or 14, wherein the real-time clock synchronization unit (18) stores one or several pieces of time information in a register or a respective register, in order to provide the one or several pieces of information, for processing, to the media access control component (4) and/or to the one other component of the system, by a read access to the register(s), via the first interface (8).
16. The method according to one of the claims 13 to 15, wherein the real-time synchronization unit (18) writes a predetermined piece of information into a predetermined register, wherein the predetermined piece of information indicates whether the communication node (10) is configured as a master node or as a slave node, wherein the predetermined register is readable, by a read access, by the media access control component (4) and/or another component of the system, via the first interface (8).

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