EP3048538B1 - Vector operation core and vector processor - Google Patents

Vector operation core and vector processor Download PDF

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EP3048538B1
EP3048538B1 EP14846444.9A EP14846444A EP3048538B1 EP 3048538 B1 EP3048538 B1 EP 3048538B1 EP 14846444 A EP14846444 A EP 14846444A EP 3048538 B1 EP3048538 B1 EP 3048538B1
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data
input
selector
output end
outputted
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French (fr)
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EP3048538A1 (en
EP3048538A4 (en
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Aijun Li
Wenqiong LIN
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Sanechips Technology Co Ltd
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Sanechips Technology Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/14—Fourier, Walsh or analogous domain transformations, e.g. Laplace, Hilbert, Karhunen-Loeve, transforms
    • G06F17/141—Discrete Fourier transforms
    • G06F17/142—Fast Fourier transforms, e.g. using a Cooley-Tukey type algorithm
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30061—Multi-way branch instructions, e.g. CASE
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3893—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator
    • G06F9/3895—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled in tandem, e.g. multiplier-accumulator for complex operations, e.g. multidimensional or interleaved address generators, macros

Definitions

  • the present disclosure relates to the flied of vector processor in chip design, and in particular to a vector ALU (Arithmetic Logical Unit) for butterfly operations in Fast-Fourier Transform.
  • a vector ALU Arimetic Logical Unit
  • GSM Global System for Mobile communication
  • UMTS Universal Mobile Telecommunications System
  • WLAN Wireless Local Area Network
  • TD-SCDMA Time Division-Synchronization Code Division Multiple Access
  • LTE Long Term Evolution
  • ASIC Application-Specific Integrated Circuit
  • a programmable vector processor is a core architecture of the SDR technology. In order to support the processing of multimode baseband, a vector processor must be able to perform several gigabytes per second of operations, and as a mobile terminal needs to meet several hundreds of mW of power dissipation.
  • An operation unit therein is a core operation part of the vector processor, the performance of which determines the performance of the whole processor, and moreover the power dissipation of which accounts for nearly half of power dissipation of the processor, and therefore the design and implementation of this part is very critical.
  • the vector ALU may implement the general multiplication, addition, multiplication addition, and may also implement the complex multiplication, addition, multiplication addition and butterfly operations in a specific Fast-Fourier Transform, and all these depend on the structure of the vector ALU.
  • the existing general schemes may only perform the butterfly operations in a base 2 Fast-Fourier Transform, and may not finish the butterfly operations in a base 3 Fast-Fourier Transform directly.
  • the butterfly operations in a base 3 Fast-Fourier Transform may be finished by a combination of sets of complex addition and complex accumulation instructions, but this adds the number of instructions, reduces computational efficiency, and at the same time increases the difficulty of programming, thereby causing lower programming efficiency.
  • EP 0 889 416 A2 discloses a processor architecture optimised for fast Fourier Transforms.
  • One of technical problems solved in the present disclosure is to propose a vector operation core which may flexibly implement various butterfly operations.
  • embodiments in the present disclosure provide a vector operation processor which may simultaneously support butterfly operations in the base 2, base 3 and base 5 Fast-Fourier Transform.
  • the vector operation core proposed in the present disclosure comprises: a first operation branch and a second operation branch;
  • the first operation branch comprises: input ends 1, 2, 3, a multiplier 7, an either-or selector 9, negators 11, 12, a three-input adder 15 and an output end 17;
  • the second operation branch comprises: input ends 4, 5, 6, a multiplier 8, an either-or selector 10, negators 13, 14, a three-input adder 16 and an output end 18;
  • the negators 11, 12, 13, 14 are configured to control signs of their output data respectively;
  • the data of input end 1 is input into one select input end of the selector 9, the data of input ends 2, 3 are input into two input ends of the multiplier 7, and the data outputted from the multiplier 7 is divided into two branches which are respectively input into input ends of the negators 11, 13;
  • the data of input end 6 is input into one select input end of the selector 10, the data of the input ends 4, 5 are input into two input ends of multiplier 8, and the data outputted from multiplier 8 is divided into two branches which are respectively input
  • one register is disposed respectively between the output end 1 and the selector 9 and between the input end 6 and the selector 10; one register is disposed respectively on output ends of the multiplier 7, 8 and output ends of the adder 15, 16.
  • the vector processor proposed in the present disclosure comprises: a control unit and the above vector operation core; the control unit is configured to control the input valid ends of the selectors 9, 10 in the vector operation core, and also configured to control the signs of output data of negators 11, 12, 13, 14 in the vector operation core.
  • the vector operation core of the present disclosure reduces chip area and power dissipation.
  • the butterfly operations in base 2, base 3 and base 5 fast Fourier transform may be supported simultaneously; when simultaneously calculating two branches of base 2 butterfly operations, since the number of multiplications is reduced by half, circuit power dissipation is reduced largely.
  • Fig.1 shows an architecture of a vector operation core in the prior art, and the architecture shows a traditional one for the vector operation core, which is composed of two multipliers and two adders.
  • Fig.2 shows an architecture of another vector operation core in the prior art, and the architecture is composed of two multipliers and three adders.
  • the vector processors constructed by the both existing vector operation cores may not realize the butterfly operations in base 2, base 3, base 5 Fast-Fourier Transform simultaneously.
  • Fig.3 shows an architecture of a vector operation core according to an embodiment of the present disclosure, which utilizes two three-input adders and four data negators, such that the data input into the input adders may be negated flexibly, and the vector processor constructed by the vector operation core may simultaneously realize the butterfly operations in base 2, base 3, base 5 Fast-Fourier Transform.
  • Fig.3 shows the basic architecture of the vector operation core.
  • the operation core is shown as only two stages, namely it is divided into three levels of pipelines to realize. In the practical hardware implementation, the operation core is realized by using different number of stages.
  • the number of stages required to realize it depends on its highest operation frequency and a process utilized, for example, if a clock frequency requirement is 800 M, then the operation core is realized by three stages, namely it is divided into four levels of pipelines to realize, and if the clock frequency requirement is 200 M, then the operation core is divided into one level of pipeline to realize. That is to say, the number of levels of pipelines is based on the clock frequency requirement, and in this application only three levels of pipelines are taken as an example to describe.
  • a first operation branch and a second operation branch are included in the vector operation core.
  • the first operation branch comprises: input ends 1, 2, 3, multiplier 7, either-or selector 9, negators 11, 12, three-input adder 15 and output end 17;
  • the second operation branch comprises: input ends 4, 5, 6, multiplier 8, either-or selector 10, negators 13, 14, three-input adder 16 and output end 18.
  • the negators 11, 12, 13, 14 may perform flexible negation according to operation requirement.
  • Data of the input end 1 is input into one select input end of the selector 9, data of the input ends 2, 3 are input into two input ends of the multiplier 7, and data outputted from multiplier 7 is divided into two branches which are respectively input into input ends of the negators 11, 13; data of the input end 6 is input into one select input end of the selector 10, data of the input ends 4, 5 are input into two input ends of the multiplier 8, and data outputted from multiplier 8 is divided into two branches which are respectively input into input ends of the negators 12, 14; data outputted from the selector 9, negators 11, 12 is respectively input into three input ends of the adder 15; data outputted from the selector 10, negators 13, 14 is respectively input into three input ends of the adder 16; output data of the adder 15 is divided into two branches which are respectively input into output 17 and the other select input end of the selector 9; output data of the adder 16 is divided into two branches which are respectively input into the output 18 and the other select input end of the selector 10.
  • one register is disposed respectively between the output end 1 and the selector 9 and between the input end 6 and the selector 10; one register is disposed respectively on the output ends of multiplier 7, 8 and the output ends of the adder 15, 16. As shown in Fig.3 , six registers are disposed totally.
  • the above vector operation core may be used as a core operation part of a vector processor, and the vector processor at least comprises: a control unit and a vector operation core described in claim 1or 2; the control unit is configured to control the valid input ends of the selectors 9, 10 in the vector operation core, and also configured to control the signs of output data of the negators 11, 12, 13, 14 in the vector operation core. Since the power dissipation of the vector operation core normally accounts for nearly half of power dissipation of the vector processor, and the above vector operation core reduces the number of operations and operation devices, the power dissipation of a vector processor using the above vector operation core will be reduced largely.
  • formula (5) may be completed by addition and accumulation instructions, and the optimization of the present disclosure mainly aims at formula (6) and formula (7).
  • Fig.6 The operation of real parts shown in Fig.6 comprises twice operation procedures, Fig.6a shows a first time operation diagram, and Fig.6b shows a second time operation diagram, with solid lines indicating the direction of data flow.
  • first time operation data Ar, Br, W1r, Bi, Wli, Ar are respectively input into input ends 1, 2, 3, 4, 5, 6, negators 11, 13, 14 control signs of their output data to be positive, negator 12 controls signs of its output data to be negative
  • selector 9 selects data of the input end 1 as valid input data
  • selector 10 selects data of the input end 6 as valid input data
  • the operation result outputted from output end 17 is used as input data selected by the selector 9 in the second time operation
  • the operation result outputted from the output end 18 is used as input data selected by selector 10 in the second time operation
  • data Cr, W2r, Ci, W2i are respectively input into input ends 2, 3, 4, 5, negators 11, 13, 14 control signs of their output data to be positive
  • negator 12 controls sign of its output
  • Fig.7a shows a first time operation diagram
  • Fig.7b shows a second time operation diagram
  • data Ai, Br, Wli, Bi, W1r, Ai are respectively input into input ends 1, 2, 3, 4, 5, 6, negators 11, 12, 14 control signs of their output data to be positive
  • negator 13 controls a sign of its output data to be negative
  • selector 9 selects data of input end 1 as valid input data
  • selector 10 selects data of input end 6 as valid input data
  • the operation result outputted from output end 17 is used as input data selected by the selector 9 in the second time operation
  • the operation result outputted from output end 18 is used as input data selected by the selector 10 in the second time operation
  • data Cr, W2i, Ci, W2r are respectively input into input ends 2, 3, 4, 5, negators 11, 12, 14 control signs of their output data to be positive
  • negator 13 controls a sign of its output data to be negative
  • selector 9 selects
  • A, B, C, D and E are complex vectors
  • w1, w2, w3, w4 are rotation factors
  • X1, X2, X3, X4, X5 are output vectors of butterfly operations in base 5 Fast-Fourier Transform.
  • Fig.8 The processing of formula (10) is shown in Fig.8 , which comprises four operations, respectively shown in operation diagram 8a, operation diagram 8b, operation diagram 8c and operation diagram 8d, with solid lines indicating the direction of data flow.
  • data Ar, Br, W1r, Bi, Wli, Ar are respectively input into input ends 1, 2, 3, 4, 5, 6, negators 11, 13, 14 control signs of their output data to be positive
  • negator 12 controls a sign of its output data to be negative
  • selector 9 selects data of input end 1 as valid input data
  • selector 10 selects data of input end 6 as valid input data
  • the operation result outputted from output end 17 is used as input data selected by the selector 9 in the second time operation
  • the operation result outputted from output end 18 is used as input data selected by the selector 10 in the second time operation
  • data Cr, W2r, Ci, W2i are respectively input into input ends 2, 3, 4, 5, negators 11, 13, 14 control signs of their output data to be positive
  • negator 12 controls a sign of its output
  • Fig.9 The processing of formula (11) is shown in Fig.9 , which comprises four operations respectively shown in diagram 9a, operation diagram 9b, operation diagram 9c and operation diagram 9d, with solid lines indicating the direction of data flow.
  • data Ai, Br, Wli, Bi, W1r, Ai are respectively input into input ends 1, 2, 3, 4, 5, 6, negators 11, 12, 14 control signs of their output data to be positive
  • negator 13 controls a sign of its output data to be negative
  • selector 9 selects data of input end 1 as valid input data
  • selector 10 selects data of input end 6 as valid input data
  • the operation result outputted from output end 17 is used as input data selected by the selector 9 in the second time operation
  • the operation result outputted from output end 18 is used as input data selected by the selector 10 in the second time operation
  • data Cr, W2i, Ci, W2r are respectively input into input ends 2, 3, 4, 5, negators 11, 12, 14 control signs of their output data to be positive
  • negator 13 controls a sign of its output
  • Fig.10 The processing of formula (12) is shown in Fig.10 , which comprises four operations respectively shown in operation diagram 10a, operation diagram 10b, operation diagram 10c and operation diagram 10d, with solid lines indicating the direction of data flow.
  • data Ar, Br, W3r, Bi, W3i, Ar are respectively input into input ends 1, 2, 3, 4, 5, 6, negators 11, 13, 14 control signs of their output data to be positive
  • negator 12 controls a sign of its output data to be negative
  • selector 9 selects data of input end 1 as valid input data
  • selector 10 selects data of input end 6 as valid input data
  • the operation result outputted from output end 17 is used as input data selected by the selector 9 in the second time operation
  • the operation result outputted from output end 18 is used as input data selected by the selector 10 in the second time operation
  • data Cr, W1r, Ci, Wli are respectively input into input ends 2, 3, 4, 5, negators 11, 13, 14 control signs of their output data to be positive
  • negator 12 controls sign of its output data to be
  • Fig.11 The processing of Formula (13) is shown in Fig.11 , which comprises four operations respectively shown in operation diagram 11a, operation diagram 11b, operation diagram 11c and operation diagram 11d, with solid lines indicating the direction of data flow.
  • data Ai, Br, W3i, Bi, W3r, Ai are respectively input into input ends 1, 2, 3, 4, 5, 6, negators 11, 12, 14 control signs of their output data to be positive
  • negator 13 controls sign of its output data to be negative
  • selector 9 selects data of input end 1 as valid input data
  • selector 10 selects data of input end 6 as valid input data
  • the operation result outputted from output end 17 is used as input data selected by the selector 9 in the second time operation
  • the operation result outputted from output end 18 is used as input data selected by the selector 10 in the second time operation
  • data Cr, W1i, Ci, W1r are respectively input into input ends 2, 3, 4, 5, negators 11, 12, 14 control signs of their output data to be positive
  • negator 13 controls a sign of its output data
  • a vector operation core and a vector processor provided in embodiments of the present disclosure have the following beneficial effects: because one two-input adder is saved and two two-input adders are replaced by one three-input adder, this reduces chip area and power dissipation.
  • the butterfly operations in base 2, base 3 and base 5 fast Fourier transform may be supported simultaneously; when simultaneously calculating two branches of base 2 butterfly operations, since the number of multiplications is reduced by half, circuit power dissipation is reduced largely.

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PCT/CN2014/077914 WO2015039452A1 (zh) 2013-09-22 2014-05-20 一种矢量运算核以及矢量处理器

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WO2015039452A1 (zh) 2015-03-26
US9910671B2 (en) 2018-03-06
CN104462016B (zh) 2018-06-05
CN104462016A (zh) 2015-03-25

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