EP2951681A4 - Solution to divergent branches in a simd core using hardware pointers - Google Patents

Solution to divergent branches in a simd core using hardware pointers

Info

Publication number
EP2951681A4
EP2951681A4 EP14746501.7A EP14746501A EP2951681A4 EP 2951681 A4 EP2951681 A4 EP 2951681A4 EP 14746501 A EP14746501 A EP 14746501A EP 2951681 A4 EP2951681 A4 EP 2951681A4
Authority
EP
European Patent Office
Prior art keywords
solution
divergent branches
simd core
pointers
hardware
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP14746501.7A
Other languages
German (de)
French (fr)
Other versions
EP2951681B1 (en
EP2951681A1 (en
Inventor
Reza Yazdani
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of EP2951681A1 publication Critical patent/EP2951681A1/en
Publication of EP2951681A4 publication Critical patent/EP2951681A4/en
Application granted granted Critical
Publication of EP2951681B1 publication Critical patent/EP2951681B1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3887—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by a single instruction for multiple data lanes [SIMD]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/40—Transformation of program code
    • G06F8/41—Compilation
    • G06F8/44—Encoding
    • G06F8/445—Exploiting fine grain parallelism, i.e. parallelism at instruction level
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30058—Conditional branch instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/321—Program or instruction counter, e.g. incrementing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3802—Instruction prefetching
    • G06F9/3804—Instruction prefetching for branches, e.g. hedging, branch folding
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3851—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution from multiple instruction streams, e.g. multistreaming
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G06F9/3853—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution of compound instructions
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G06F9/3889—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units controlled by multiple instructions, e.g. MIMD, decoupled access or execute

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Advance Control (AREA)
  • Devices For Executing Special Programs (AREA)
  • Executing Machine-Instructions (AREA)
EP14746501.7A 2013-01-29 2014-01-29 Solution to divergent branches in a simd core using hardware pointers Active EP2951681B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US13/753,113 US9639371B2 (en) 2013-01-29 2013-01-29 Solution to divergent branches in a SIMD core using hardware pointers
PCT/US2014/013474 WO2014120703A1 (en) 2013-01-29 2014-01-29 Solution to divergent branches in a simd core using hardware pointers

Publications (3)

Publication Number Publication Date
EP2951681A1 EP2951681A1 (en) 2015-12-09
EP2951681A4 true EP2951681A4 (en) 2016-12-07
EP2951681B1 EP2951681B1 (en) 2018-11-14

Family

ID=51224343

Family Applications (1)

Application Number Title Priority Date Filing Date
EP14746501.7A Active EP2951681B1 (en) 2013-01-29 2014-01-29 Solution to divergent branches in a simd core using hardware pointers

Country Status (6)

Country Link
US (1) US9639371B2 (en)
EP (1) EP2951681B1 (en)
JP (1) JP6159825B2 (en)
KR (1) KR101702651B1 (en)
CN (1) CN105051680B (en)
WO (1) WO2014120703A1 (en)

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US9697003B2 (en) * 2013-06-07 2017-07-04 Advanced Micro Devices, Inc. Method and system for yield operation supporting thread-like behavior
US9582321B2 (en) * 2013-11-08 2017-02-28 Swarm64 As System and method of data processing
US9292269B2 (en) * 2014-01-31 2016-03-22 Nvidia Corporation Control flow optimization for efficient program code execution on a processor
US9348595B1 (en) 2014-12-22 2016-05-24 Centipede Semi Ltd. Run-time code parallelization with continuous monitoring of repetitive instruction sequences
US10180841B2 (en) 2014-12-22 2019-01-15 Centipede Semi Ltd. Early termination of segment monitoring in run-time code parallelization
KR101624636B1 (en) * 2015-03-03 2016-05-27 주식회사 에이디칩스 Apparatus and Method for Instruction Fatch
US9208066B1 (en) * 2015-03-04 2015-12-08 Centipede Semi Ltd. Run-time code parallelization with approximate monitoring of instruction sequences
US10296346B2 (en) 2015-03-31 2019-05-21 Centipede Semi Ltd. Parallelized execution of instruction sequences based on pre-monitoring
US10296350B2 (en) 2015-03-31 2019-05-21 Centipede Semi Ltd. Parallelized execution of instruction sequences
US9715390B2 (en) 2015-04-19 2017-07-25 Centipede Semi Ltd. Run-time parallelization of code execution based on an approximate register-access specification
EP3106982B1 (en) * 2015-06-18 2021-03-10 ARM Limited Determination of branch convergence in a sequence of program instructions
US10585623B2 (en) 2015-12-11 2020-03-10 Vivante Corporation Software defined FIFO buffer for multithreaded access
JP6167193B1 (en) * 2016-01-25 2017-07-19 株式会社ドワンゴ Processor
US10474468B2 (en) 2017-02-22 2019-11-12 Advanced Micro Devices, Inc. Indicating instruction scheduling mode for processing wavefront portions
US10620994B2 (en) 2017-05-30 2020-04-14 Advanced Micro Devices, Inc. Continuation analysis tasks for GPU task scheduling
US10990394B2 (en) * 2017-09-28 2021-04-27 Intel Corporation Systems and methods for mixed instruction multiple data (xIMD) computing
US10877757B2 (en) * 2017-11-14 2020-12-29 Nvidia Corporation Binding constants at runtime for improved resource utilization
KR102406340B1 (en) * 2018-02-26 2022-06-13 에스케이하이닉스 주식회사 Electronic apparatus and operating method thereof
CN110716750A (en) * 2018-07-11 2020-01-21 超威半导体公司 Method and system for partial wavefront combining
FR3084187B1 (en) * 2018-07-18 2021-01-01 Commissariat Energie Atomique PROCEDURE FOR ACCELERATING THE EXECUTION OF A SINGLE PATH PROGRAM BY PARALLEL EXECUTION OF CONDITIONALLY COMPETING SEQUENCES
US11061681B2 (en) 2019-07-25 2021-07-13 International Business Machines Corporation Instruction streaming using copy select vector
CN113885877A (en) * 2021-10-11 2022-01-04 北京超弦存储器研究院 Compiling method, device, equipment and medium

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Also Published As

Publication number Publication date
US9639371B2 (en) 2017-05-02
US20140215187A1 (en) 2014-07-31
EP2951681B1 (en) 2018-11-14
CN105051680B (en) 2018-08-14
JP6159825B2 (en) 2017-07-05
EP2951681A1 (en) 2015-12-09
WO2014120703A1 (en) 2014-08-07
CN105051680A (en) 2015-11-11
KR101702651B1 (en) 2017-02-03
JP2016508640A (en) 2016-03-22
KR20150111990A (en) 2015-10-06

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