JP6167193B1 - Processor - Google Patents

Abstract

A processor capable of high-speed processing of non-numerical calculation processing is provided. A processor 1 includes a plurality of processing elements 10-1 to 10-N and an execution management unit 40. Each processing element has a temporary storage unit 11 for temporarily storing an assigned unit instruction sequence, and can execute an instruction included in the unit instruction sequence stored in each temporary storage unit. The execution management unit is an instruction sequence that does not include a branch instruction in the middle of a program that is an instruction sequence of the assembly language or lower, and is an instruction sequence that starts with the first instruction at the branch destination and ends with the branch instruction. The unit instruction sequence is divided, the divided unit instruction sequence is sequentially assigned to each of the plurality of processing elements, and the assigned unit instruction sequence is executed in parallel by the plurality of processing elements. [Selection] Figure 1

Description

  The present invention relates to a processor.

  In recent years, a technique for realizing high-speed processing of a processor by processing a program in parallel at an instruction level is known (for example, see Non-Patent Document 1). In a conventional processor using such a technique, in order to process more instructions in parallel, for example, a static optimization method in which a program is optimized by a compiler, a branch prediction and speculative execution are performed. Method is used.

G. S. Sohi, S. Breach, and T. N. Vijaykumar, Multiscalar Processors, 22th International Symposium on Computer Architecture (ISCA-22), 1995

  However, with the conventional processor described above, for example, there may be cases where sufficiently high-speed processing cannot be obtained for non-numerical calculation processing, which is a general application of the processor, and high-speed processing is possible for non-numeric calculation processing A processor is sought.

  The present invention has been made to solve the above problems, and an object of the present invention is to provide a processor capable of performing high-speed non-numeric calculation processing.

In order to solve the above problem, according to one aspect of the present invention, each has a temporary storage unit that temporarily stores an assigned unit instruction sequence, and the unit instruction sequence stored in each temporary storage unit includes A branch instruction that includes multiple processing elements that can execute the included instructions and a program that is an instruction sequence at a level lower than assembly language, and that does not include a branch instruction in the middle, starting from the first instruction at the branch destination Is divided into the unit instruction sequence that is an instruction sequence that ends with, and the divided unit instruction sequence is sequentially assigned to each of the plurality of processing elements, and the assigned unit instruction sequence is executed in parallel by the plurality of processing elements. an execution management unit, and the head position information indicating a position of the first instruction of the unit instruction sequence in the program, the unit instruction sequence Yes Comprising a whether a valid indicating information whether there are, then the management table storage unit that stores the management table in which a plurality having a management information associating the following execution information indicating the processing elements that perform, the execution management unit Is, when the divided unit instruction sequence is not stored in any of the temporary storage units of the plurality of processing elements, the unit instruction sequence is assigned to any of the plurality of processing elements, and the unit is divided When the instruction sequence is already stored in the temporary storage unit of any of the plurality of processing elements, the processing element is caused to execute the unit instruction sequence already stored in the temporary storage unit in parallel, The management table storage unit stores the management table when a branch instruction is detected in the program. Based on the Le, then the unit instruction sequence to be executed has already been stored in the temporary storage unit of any one of said plurality of processing elements, and wherein the determining whether and effective state Processor.

  In addition, according to one aspect of the present invention, in the processor, the execution management unit may change the next execution information from the management table stored in the management table storage unit when a branch instruction is detected in the program. Based on the start position information and the valid information corresponding to the unit instruction sequence to be executed next to the branch instruction, and the position indicated by the acquired start position information, the execution position of the program to be executed next, And when the acquired valid information indicates valid, the processing element that matches the next execution information stores the unit instruction sequence in the temporary storage unit and is in a valid state. It is determined that it is.

  Further, according to one aspect of the present invention, in the above processor, the execution management unit does not match a position indicated by the acquired head position information and an execution position of the program to be executed next, or acquires the effective When the information indicates invalidity, the unit instruction sequence to be executed next is assigned to one of the plurality of processing elements, and the management table is updated in correspondence with the assigned unit instruction sequence. To do.

  Further, according to one aspect of the present invention, in the above processor, when the execution management unit assigns the unit instruction sequence to be executed next to one of the plurality of processing elements, the unit instruction sequence of the management table And the valid information is updated to a value indicating invalidity, and when the processing element completes execution of the unit instruction sequence, the unit instruction sequence corresponding to the unit instruction sequence is stored. The valid information is updated to a value indicating validity.

  One embodiment of the present invention is the processor described above, wherein the processing element executes the instruction by pipeline processing.

One embodiment of the present invention is the processor described above, wherein each of the plurality of processing elements includes a register used for execution of the instruction, and further, the register of the register is between the plurality of processing elements. When a RAW hazard that is data-dependent due to reading after writing occurs, until the writing of the unit instruction sequence to the register by the processing element that has performed writing to the register in the nearest past is completed A register management unit that suspends instruction execution of the processing element that executes reading of a register is provided.
Further, according to one aspect of the present invention, each has a temporary storage unit that temporarily stores an assigned unit instruction sequence, and can execute an instruction included in the unit instruction sequence stored in each temporary storage unit An instruction sequence that does not include a branch instruction in the middle of multiple processing elements and a program that is an instruction sequence of the assembly language or lower level. The instruction sequence starts with the first instruction at the branch destination and ends with the branch instruction. And an execution management unit that sequentially assigns the divided unit instruction sequence to each of the plurality of processing elements and causes the plurality of processing elements to execute the assigned unit instruction sequence in parallel. , Each of the plurality of processing elements has a register used for execution of the instruction, and When a RAW hazard that is data-dependent due to reading after writing to the register occurs between the processing elements, the register of the unit instruction sequence by the processing element that has performed writing to the register in the nearest past The processor further comprises a register management unit that suspends instruction execution of the processing element that executes reading of the register until writing to the register is completed.

Further, according to an aspect of the present invention, in the above processor, PE identification information for identifying the processing element, update information indicating that the register is updated in the execution of the unit instruction sequence, and the unit instruction sequence An update history table having update history information corresponding to the number of processing elements, which is associated with completion information indicating that the last write of the register in the memory is completed and execution information indicating that the write of the register is executed An update history storage unit for storing, and the register management unit determines whether or not the RAW hazard has occurred based on an update history table stored in the update history storage unit , and reads into the register In the processing element for performing the processing in the processing element No RAW hazard occurs, and a RAW hazard occurs between the processing elements between the processing element that reads the register and the processing element that writes to the register in the past. Whether or not to suspend instruction execution of the processing element that reads from the register based on the completion information regarding the register to be written for the processing element that writes to the nearest past It is characterized by controlling .

Further, according to one aspect of the present invention, in the processor, the register management unit is configured to perform the processing on the register based on the execution information regarding the register to be read with respect to the processing element that reads the register. in the processing element to read Te, characterized that you determine whether RAW hazard within the processing element occurs.

  In one embodiment of the present invention, in the above processor, each of the plurality of processing elements includes a plurality of the registers, and the update history storage unit stores the update history table corresponding to each of the plurality of registers. It is memorized.

  Further, according to one aspect of the present invention, in the above processor, a store buffer table in which local position information corresponding to each instruction included in the unit instruction sequence is associated with access information indicating a history of accessing the external storage unit For each of the plurality of processing elements, and when there is an access request from the processing element to the external storage unit, the store buffer storage unit corresponds to the processing element stored in the store buffer storage unit. And a store buffer control unit that controls access to the external storage unit based on a store buffer table.

  In one embodiment of the present invention, in the above processor, the access information is associated with type information indicating an access type, storage location information accessed in the external storage unit, and accessed data. The store buffer control unit outputs the data to the processing element when the data corresponding to the access request exists in the store buffer table in response to the access request for reading data from the external storage unit When the data corresponding to the access request does not exist in the store buffer table, the data read from the external storage unit is output to the processing element.

  Further, according to one aspect of the present invention, in the processor, the store buffer control unit may store the local buffer in the store buffer table corresponding to the processing element in response to the access request for writing data in the external storage unit. The position information and the access information are stored in association with each other, and the data is stored in the external storage unit.

  According to the present invention, non-numeric calculation processing can be performed at high speed.

It is a block diagram which shows an example of the processor by this embodiment. It is a figure explaining an example of an atomic block in this embodiment. It is a block diagram which shows the structural example of PE in this embodiment. It is a block diagram which shows the structural example of the execution management unit in this embodiment. It is a figure which shows the structural example of the update log | history memory | storage part in this embodiment. It is a block diagram which shows an example of the register management unit in this embodiment. It is a figure which shows the structural example of the store buffer memory | storage part in this embodiment. It is a figure which shows the structural example of the entry table memory | storage part in this embodiment. It is a figure which shows an example of the state transition of PE in this embodiment. It is a figure which shows an example of the pipeline process of the processor by this embodiment. It is a figure which shows an example of the parallel processing of PE by this embodiment. It is a figure which shows an example of the RAW hazard process between PE of the processor by this embodiment. It is a figure which shows an example of the RAW hazard process in own PE of the processor by this embodiment.

A processor according to an embodiment of the present invention will be described below with reference to the drawings.
FIG. 1 is a block diagram illustrating an example of a processor 1 according to the present embodiment.
As shown in FIG. 1, the processor 1 includes a plurality of (for example, N) processing elements (10-1, 10-2,..., 10-N), a PC (program counter) update unit 20, An instruction fetch unit 30, an execution management unit 40, a register management unit 50, a store buffer unit 60, and a memory management unit 70 are provided. The processor 1 is connected to the data memory 71 via the memory management unit 70.

  The “processing element” is expressed as “PE” (Processing Element) in the following description. Moreover, each of PE10-1, PE10-2, ... 10-N has the same configuration, and in the present embodiment, when any PE included in the processor 1 is indicated, or when not particularly distinguished, This will be described as PE10. In the present embodiment, the number of PEs 10 is, for example, 8.

  The PC update unit 20 has a PC (program counter) 21 and updates the PC 21. Here, the PC 21 is a register that stores an address (position information) indicating an instruction execution position of a program memory (not shown) that stores a program. The PC update unit 20 "+ ILs" the PC 21 every time a normal instruction is executed, and updates the PC 21 to the designated branch destination address when a branch instruction is executed. Here, “IL” indicates a fixed instruction length. The PC updating unit 20 outputs the PC value stored in the PC 21 to the program memory as an address.

  The instruction fetch unit 30 includes an IR (instruction register) 31, and stores (stores) an instruction (Instruction) output from the program memory in the IR 31 in accordance with the address output from the PC update unit 20. Here, IR 31 is a register for storing an instruction read from the program memory. The instruction fetch unit 30 outputs the instruction stored in the IR 31 to the execution management unit and supplies it to the PE 10 via the instruction network NW1.

  Each of the plurality of independent PEs 10 includes an instruction included in the atomic block as a list entry (input data) of an expanded linked list (unrolled linked list) obtained by dividing a program that is a sequence of instructions at a level lower than assembly language. Execute. Here, an atomic block (an example of a unit instruction sequence) is a program that is an instruction sequence at a level lower than assembly language, an instruction sequence that does not include a branch instruction in the middle, and the first instruction at the branch destination is the starting point, It is an instruction sequence that ends with a branch instruction.

FIG. 2 is a diagram illustrating an example of an atomic block in the present embodiment.
FIG. 2A is a list showing an example of a program (PR1) described in assembly language. FIG. 2B is an example in which the program (PR1) shown in FIG. 2A is divided into atomic blocks to form an expanded linked list.
As shown in FIG. 2B, the program (PR1) is divided into atomic blocks AB_A to AB_E. For example, in the atomic block AB_D, the start point (start end) is “add r2, r2, r1” (instruction I1) which is the first instruction of the branch destination, and the end point (end) is “bneq loop” (instruction which is the branch instruction). Instruction I2).

  As described above, in the processor 1 according to the present embodiment, the program is divided into atomic blocks, the expanded linked list as shown in FIG. 2C is obtained, and each PE 10 is caused to execute each atomic block. The example shown in FIG. 2C is an expanded linked list of the program shown in FIG. Here, the processor 1 causes the “atomic block A” (AB_A) to be executed by the “atomic block B” (AB_B). In the “atomic block B” (AB_B), the “atomic block C” (AB_C) A process branching to “Block D” (AB_D) is executed. Further, the processor 1 causes a conditional loop to be executed by “atomic block B” (AB_B) and subsequent “atomic block D” (AB_D). In FIG. 2C, the shaded area indicates a branch instruction.

Returning to FIG. 1, each of the plurality of PEs 10 has an instruction cache unit 11 that temporarily stores an assigned atomic block, and can execute an instruction included in the atomic block stored in each instruction cache unit 11. is there.
Here, the configuration of the PE 10 will be described with reference to FIG.

FIG. 3 is a block diagram illustrating a configuration example of the PE 10 in the present embodiment.
As shown in FIG. 3, the PE 10 includes an instruction cache unit 11, a register file unit 12, and an instruction execution unit 13.
The instruction cache unit 11 (an example of a temporary storage unit) is a register group that stores the instruction output from the instruction fetch unit 30 as a cache. The instruction cache unit 11 has, for example, M registers, a cache register (C1) to a cache register (CM), and stores an atomic block. Here, the number M of cache registers is, for example, a size that can store one atomic block, for example, 16.

  The register file unit 12 is a group of registers for storing calculation results by the PE 10, data read from the data memory, and the like, and is used for executing instructions. The register file unit 12 includes a plurality of general purpose registers (for example, Reg1 to RegR) and a control register. In other words, the register file unit 12 includes R registers from the general-purpose register (Reg1) to the general-purpose register (RegR), and a control register, and is used for executing instructions. Note that data communication between the register file units 12 included in each PE 10 is executed via the operand data network NW2. In the following description, the general-purpose register and the control register will be described simply as “register”.

The instruction execution unit 13 includes, for example, an instruction decoder and an ALU (Arithmetic Logic Unit), and executes an instruction output from the instruction fetch unit 30 or an instruction stored in the instruction cache unit 11.
Note that, in the first execution of the atomic block, the PE 10 may cause the instruction execution unit 13 to execute the instruction output from the instruction fetch unit 30 and store the instruction in the instruction cache unit 11 in order. The instructions output from the unit 30 may be stored in the instruction cache unit 11 in order, read out from the instruction cache unit 11, and executed by the instruction execution unit 13. In addition, in the second execution of the atomic block, the PE 10 reads instructions in order from the instruction cache unit 11 and causes the instruction execution unit 13 to execute the instructions.
The PE 10 is configured to be able to execute instructions stored in the instruction cache unit 11 in parallel by pipeline processing.

  1 again, the execution management unit 40 (an example of the execution management unit) divides the program into atomic blocks, sequentially assigns the divided atomic blocks to each of the plurality of PEs 10, and assigns the assigned atomic blocks to the plurality of atomic blocks. The PE10 is executed in parallel. When the divided atomic block is not stored in any instruction cache unit 11 of the plurality of PEs 10 (in the case of a cache miss), the execution management unit 40 assigns the atomic block to any one of the plurality of PEs 10. Further, when the divided atomic block is already stored in one of the instruction cache units 11 of the plurality of PEs 10 (in the case of a cache hit), the execution management unit 40 has already stored the PE 10 in the instruction cache unit 11. Run stored atomic blocks in parallel.

  Further, the execution management unit 40, when a branch instruction is detected in the program, based on a management table stored in a management table storage unit 41 to be described later, the atomic block to be executed next is one of the instructions of the plurality of PEs 10. It is determined whether it is already stored in the cache unit 11 and is in a valid state. When the execution management unit 40 determines that the atomic block to be executed next is already stored in one of the instruction cache units 11 of the plurality of PEs 10 and is in a valid state (in the case of a cache hit). The PE 10 is caused to execute the atomic block stored in the instruction cache unit 11.

Here, the configuration of the execution management unit 40 in the present embodiment will be described with reference to FIG.
FIG. 4 is a block diagram illustrating a configuration example of the execution management unit 40 in the present embodiment.
As shown in FIG. 4, the execution management unit 40 includes a management table storage unit 41, a cache miss handler unit 42, and a predecoder unit 43.

  The management table storage unit 41 is, for example, a storage composed of registers, and corresponds to “PE_NO”, “BTA”, “valid flag”, “LGT”, “PTR1”, and “PTR2”. A management table having a plurality of attached management information is stored. here. “PE_NO” indicates the number of the PE 10, and the number of management information is N, which is the number of PEs 10. “BTA” is a branch target address and indicates the address of a branch target instruction. That is, “BTA” is head position information (head address) indicating the position of the head instruction of the atomic block in the program.

The “valid flag” is flag information indicating whether or not the management information (the PE 10) is valid. That is, the “valid flag” is valid information indicating whether or not the atomic block is valid. The “valid flag” indicates, for example, valid when “1”, and invalid when “0”. “LGT” indicates the block length of the atomic block.
“PTR1” and “PTR2” are row numbers (pointers) in the management table of the atomic block to be executed next. That is, “PTR1” and “PTR2” are next execution information indicating the PE 10 to be executed next. In this embodiment, since the branch instruction is an example in the case of having two branch destinations, for example, it has two pointers “PTR1” and “PTR2”. If there are M branch destinations, it will have M pointers.

  In the example illustrated in FIG. 4, for example, for PE 10 with “PE_NO” being “1”, “BTA” (head address) is “XXXX”, “Valid flag” is “1”, and “LGT” (block This indicates that an atomic block whose length is “10” is allocated. Further, “PTR1” to be executed next by the atomic block is “2”, and “PTR2” is “3”. That is, the PR 10 to be executed next indicates that “PR_NO” is “2” or “3”.

The predecoder unit 43 decodes the instruction output from the instruction fetch unit 30 and determines a branch instruction.
The cache miss handler unit 42 controls assignment and execution of atomic blocks to the PE 10. For example, when the atomic block is a cache miss, the cache miss handler unit 42 allocates an atomic block to one of the plurality of PEs 10 and causes the PE 10 to execute. Further, when the atomic block to be executed next is a cache hit, the cache miss handler unit 42 causes the PE 10 that has hit to execute the atomic block that is already stored in the instruction cache unit 11.
The predecoder unit 43 includes a comparison circuit 421, an AND circuit 422, an AND circuit 423, an LRU (Least Recently Used) arbiter 424, and a handler unit 425.

  The comparison circuit 421 compares the PC value, which is the value of the PC 21, with the “BTA” of the atomic block (PE 10) to be executed next stored in the management table storage unit 41. For example, the comparison circuit 421 outputs an H state (High state (“1” state)) when they match, and outputs an L state (Low state (“0” state)) when they do not match.

The AND circuit 422 outputs the result of the logical product operation of the output of the comparison circuit 421 and the “valid flag” of the atomic block (PE10) to be executed next.
The AND circuit 423 outputs a logical product operation result of the output of the AND circuit 422 and the branch instruction signal indicating the branch instruction output from the predecoder unit 43 as a HIT signal. This HIT signal is a signal indicating that there is a cache hit for the next PE 10 to be executed. That is, the AND circuit 423 outputs an H state when there is a cache hit.

  The LRU arbiter 424 selects the PE 10 to be used next from the plurality of PEs 10 when the atomic block (PE 10) to be executed next is a cache miss. The LRU arbiter 424 selects, for example, the PE 10 that “has been used for the longest time” or “the one that is least frequently referenced”.

The handler unit 425 controls the cache miss handler unit 42. For example, the handler unit 425 causes the PE 10 having a cache hit to execute an instruction stored in the instruction cache unit 11. Further, for example, the handler unit 425 causes the PC update unit 20 to output “LGT” of the next PE 10 to be executed, and updates the value of the PC 21 to the value of “LGT”.
Further, the handler unit 425 updates the management information corresponding to the PE 10 selected by the LRU arbiter 424 in the case of a cache miss. That is, in the case of a cache miss, the handler unit 425 displays “BTA”, “valid flag”, “LGT”, and “PTR1” in the corresponding “PE_NO” row of the management table storage unit 41. , Management information associated with “PTR2” is stored.

  As described above, when a branch instruction is detected in the program, the execution management unit 40 reads the branch from the management table stored in the management table storage unit 41 based on the next execution information (“PTR1” or “PTR2”). Obtain “BTA” (head position information) and “valid flag” (valid information) corresponding to the atomic block to be executed next to the instruction. The execution management unit 40 executes the next execution when the position indicated by the acquired “BTA” matches the execution position (PC value) of the program to be executed next and the acquired “valid flag” indicates validity. The PE 10 that matches the information (“PTR1” or “PTR2”) stores the atomic block in the instruction cache unit 11 and determines that it is in a valid state.

In addition, the execution management unit 40 sets one of the plurality of PEs 10 when the acquired position indicated by “BTA” does not match the execution position of the program to be executed next or when the acquired valid information indicates invalidity. The atomic block to be executed next is allocated, and the management table is updated in correspondence with the allocated atomic block.
In addition, when the execution management unit 40 assigns the next atomic block to be executed to one of the plurality of PEs 10, the execution management unit 40 stores “LGT” corresponding to the atomic block in the management table and invalidates the “valid flag”. Is updated to a value (for example, “0”). When the PE 10 completes execution of the atomic block, the execution management unit 40 updates the “valid flag” corresponding to the atomic block to a value indicating validity (for example, “1”).

  Referring back to FIG. 1 again, the register management unit 50 (an example of a register management unit) manages the registers of the register file unit 12 included in each PE 10. When there is a data dependency across a plurality of atomic blocks for a specific register, the register management unit 50 controls the PE 10 to avoid the data dependency. For example, when a RAW hazard that is data-dependent due to reading after register writing occurs between the plurality of PEs 10, the register management unit 50 performs atomic processing by the PE 10 that has performed writing to the register in the nearest past. Until the writing of the block to the corresponding register is completed, the instruction execution of the PE 10 that executes the reading of the register is suspended (STALL). The register management unit 50 includes an update history storage unit 51.

  The update history storage unit 51 is, for example, a storage constituted by a register. As shown in FIG. 5, the “FIFO”, “UPD”, “W / A”, “RAW”, and “ACT” Is stored. The update history storage unit 51 stores an update history table having a plurality of update history information. Further, the update history storage unit 51 is configured in a FIFO (First In First Out), and the execution management unit 40 adds update history information corresponding to the PE 10 when an atomic block is allocated to the PE 10, Discard old update history information.

FIG. 5 is a diagram illustrating a configuration example of the update history storage unit 51 in the present embodiment.
In FIG. 5, “FIFO” indicates PE identification information for identifying the PE 10 and stores the PE identification information in the order of execution. “UPD” is a flag (UPD flag) indicating that the register has been updated in the execution of the atomic block. That is, “UPD” is update information indicating that the register has been updated. “UPD”, for example, indicates that it has been updated when it is “1”, and indicates that it has not been updated when it is “0”.

  “W / A” includes a W flag and an A flag. The W flag is completion information indicating that the last write of the register in the atomic block has been completed. The A flag is execution information indicating that the register write has been executed. For example, the W flag indicates that the last write of the register is completed when it is “1”, and indicates that the last write of the register is not completed when it is “0”. The A flag indicates, for example, that register writing has been executed when it is “1”, and indicates that register writing has not been executed when it is “0”.

“RAW” is a RAW flag indicating that a RAW hazard has occurred in its own PE 10. “RAW”, for example, indicates that a RAW hazard has occurred in its own PE 10 when it is “1”, and indicates that a RAW hazard has not occurred in its own PE 10 when it is “0”. Show. Further, “RAW” functions as a control flag for switching between processing for a RAW hazard in its own PE 10 and processing for a RAW hazard between PEs 10. “RAW” is changed to “1”, for example, when the A flag is “1” and there is a read request for the register.
“ACT” is an ACT flag indicating whether or not the PE 10 is being executed. “ACT” indicates, for example, that the PE 10 is being executed when it is “1”, and indicates that the PE 10 is not being executed when it is “0”.

The update history storage unit 51 stores an update history table having update history information corresponding to the number of PEs 10 (for example, N). The update history storage unit 51 stores an update history table corresponding to each of the plurality of registers. That is, the number of bits for “UPD”, “W / A”, and “RAW” is determined according to the number of registers included in the PE 10. For example, “UPD” is composed of RN × 1 bits, and “W / A” is composed of RN × 2 bits. “RAW” is composed of RN × 1 bit. Here, RN is the number of registers (the total number of R general-purpose registers and the number of control registers).
In the example illustrated in FIG. 5, for example, in the update history information in which “FIFO” corresponds to “PE_1”, “UPD” is “11...” And “W / A” is “0/0. ". Further, “RAW” is “00...” And “ACT” is “1”.

FIG. 6 is a block diagram showing an example of the register management unit 50 in the present embodiment.
As illustrated in FIG. 6, the register management unit 50 includes an update history storage unit 51, a multiplexer 52, and a multiplexer 53. The update history storage unit 51 illustrated in FIG. 6 stores only “UPD”, “W / A”, and “RAW” regarding a specific register (for example, RegX) in the above-described update history information illustrated in FIG. It is written.

The update history information EN2 corresponds to the PE 10-3 (PE_3) for which a read request has been issued to the register management unit 50 and no RAW hazard has occurred in its own PE 10. The update history information EN1 corresponds to the PE 10-1 (PE_1) that has written to the register RegX in the past closest to the processing of the PE 10-3 (PE_3).
The multiplexer 52 selects either the W flag of the update history information EN1 or the A flag of the update history information EN2 based on the value of “RAW”, and outputs a STALLB signal that stalls the PE 10-3 (PE_3). To do. The STALLB signal is a negative logic signal and stalls when it is “0”. Further, when “RAW” is “0”, the multiplexer 52 outputs the value of the W flag of the update history information EN1 as a STALLB signal. Further, when “RAW” is “1”, the multiplexer 52 outputs the value of the A flag of the update history information EN2 as a STALLB signal.

  The multiplexer 53 switches the register RegX for reading data between PE10-3 (PE_3) and PE10-1 (PE_1) based on the value of “RAW”. The multiplexer 53 designates the register RegX of the PE 10-1 (PE_1) as a register to read when “RAW” is “0”. Further, when “RAW” is “1”, the multiplexer 53 designates the register RegX of the PE 10-3 (PE_3) as a register to be read.

As described above, the register management unit 50 determines whether or not a RAW hazard has occurred in its own PE 10 based on the update history table stored in the update history storage unit 51, and the RAW hazard in its own PE 10 is determined. When it occurs, “RAW” is set to “1”. Then, the register management unit 50 executes writing to the register in the past in the update history table, including “RAW” corresponding to the PE 10 having requested reading, the A flag corresponding to the PE 10, and the closest past. Based on the W flag corresponding to the PE 10, the instruction execution of the PE 10 that requested the reading is suspended.
For example, when “RAW” corresponding to the PE 10 requested to read is “1”, the register management unit 50 uses the multiplexer 52 to enter an instruction to the PE 10 based on the A flag corresponding to the PE 10. A STALLB signal is generated as to whether or not to hold. In this case, the register management unit 50 causes the PE 10 to read data from the register (RegX) of the PE 10.

  Further, for example, when “RAW” corresponding to the PE 10 that has made a read request is “0”, the register management unit 50 corresponds to the PE 10 that has been writing to the register in the past by the multiplexer 52. Based on the W flag, a STALLB signal is generated as to whether or not to hold entry of an instruction to the PE 10 concerned. Further, in this case, the register management unit 50 causes the PE 10 that has requested reading to read data from the register (RegX) of the PE 10 PE 10 that has been writing to the register in the nearest past.

  For example, in the example shown in FIG. 6, when a read request for the register RegX is made to the PE 10-3 (PE_3) corresponding to the update history information EN2, “RAW” is “0”. As a source, PE10-1 (PE_1) is selected. Since the W flag of PE10-1 (PE_1) is “0”, the multiplexer 52 outputs “0” to the STALLB signal, and executes the instruction of PE10-3 (PE_3). ) Until the W flag becomes “1”.

Note that the register management unit 50 determines whether or not a RAW hazard has occurred based on the A flag, and selects the PE 10 that has performed writing to the register in the nearest past based on “UPD”.
In addition, the register management unit 50 changes the W flag, the A flag, and “RAW” to “0” in the update history information stored in the first instruction execution in which the atomic block is assigned to the PE 10, and the cache hit is detected. The state of the update history information stored in the second and subsequent instruction execution is maintained.

  Referring back to FIG. 1 again, the store buffer unit 60 (an example of the store buffer control unit) corresponds to the PE 10 stored in the store buffer storage unit 61 described later when an access request is made to the data memory 71 from the PE 10. Access to the data memory 71 is controlled based on the store buffer table. The store buffer unit 60 exchanges data with the register file unit 12 included in the PE 10 via the operand data network NW2.

The store buffer unit 60 accesses the data memory 71 via the memory management unit 70. In response to an access request for reading data from the data memory 71, the store buffer unit 60 outputs the data to the PE 10 when there is data corresponding to the access request in the store buffer table of the store buffer storage unit 61. Further, the store buffer unit 60 outputs the data read from the data memory 71 to the PE 10 when there is no data corresponding to the access request in the store buffer table.
The store buffer unit 60 includes a store buffer storage unit 61 and an entry table storage unit 62.

The store buffer storage unit 61 stores a store buffer table in which local position information corresponding to each instruction included in an atomic block and access information indicating a history of accessing the data memory 71 are associated with each other by the number of PEs 10 ( (For example, N items) are stored.
FIG. 7 is a diagram illustrating a configuration example of the store buffer storage unit 61 in the present embodiment.
As illustrated in FIG. 7, the store buffer storage unit 61 includes N store buffer tables. Further, the store buffer table stores, for example, “LPC”, “Ld”, “St”, “Addr”, “Data”, “completed”, and “end” in association with each other. The store buffer table has as many lines as the size of the instruction cache unit 11 of the PE 10.

  Here, “LPC” is a local program counter (local position information) in the PE 10 and corresponds to the address of the instruction cache unit 11 of the PE 10. “Ld” is a flag indicating that a load instruction has been executed, and “St” is a flag indicating that a store instruction has been executed. The load instruction is an instruction for reading data from the data memory 71 to the register, and the store instruction is an instruction for writing data from the register to the data memory 71. “Addr” indicates the address of the data memory 71, and “Data” indicates the value of the accessed data. “Complete” is a completion flag indicating that the access (data writing) to the data memory 71 is completed, and “End” is an end flag indicating that execution of the instruction is completed (terminated). . Here, “Ld”, “St”, “Addr”, “Data”, “Complete”, and “End” correspond to access information indicating a history of accessing the data memory 71.

For example, in the example shown in FIG. 7, an instruction whose “LPC” is “0” is a store instruction that writes “0x0f” of “Data” to “0x02” of “Addr” of the data memory 71. Although it is completed, it indicates that writing to the data memory 71 is not completed.
The store buffer unit 60 stores “LPC” (local position information) and the access information in association with each other in the store buffer table corresponding to the PE 10 in response to an access request for writing data to the data memory 71. At the same time, the data is stored in the data memory 71.

  Returning to FIG. 1 again, the entry table storage unit 62 stores the priority order when the same address is accessed from different PEs 10. The entry table storage unit 62 is configured as a FIFO, and the store buffer unit 60 adds information corresponding to the PE 10 that executes the instruction when the instruction to access the data to the data memory 71 is executed. , Discard old information that data access is complete. For example, as illustrated in FIG. 8, the entry table storage unit 62 stores “FIFO” and “entry NO” in association with each other.

FIG. 8 is a diagram illustrating a configuration example of the entry table storage unit 62 in the present embodiment.
In FIG. 8, “FIFO” indicates PE identification information for identifying the PE 10, and “Entry NO” indicates the number of the store buffer table described above.
For example, in the example shown in FIG. 8, “FIFO” is “1” in “Entry NO” corresponding to “PE_1”, and is the top row, so that the access by PE10 corresponding to “PE_1” has the highest priority. Is high.

  1 again, the memory management unit 70 is disposed between the store buffer unit 60 and the data memory 71, and relays data access between the store buffer unit 60 and the data memory 71. The data memory 71 (an example of an external storage unit) is a memory that stores data.

Next, the operation of the processor 1 according to the present embodiment will be described with reference to the drawings.
<Instruction execution processing>
First, the instruction execution process of the processor 1 according to the present embodiment will be described.
The processor 1 outputs the PC value as an address to the program memory, and the instruction fetch unit 30 stores the instruction output from the program memory in the IR 31. The processor 1 divides into atomic blocks as shown in FIG. 2, assigns them to one of a plurality of PEs 10, and causes the PEs 10 to execute instructions in units of atomic blocks. At this time, the execution management unit 40 manages the assignment of the PE 10 and the parallel processing of the PE 10.

FIG. 9 is a diagram showing a state transition of the PE 10 of the processor 1 according to the present embodiment.
In this figure, a state S1 indicates an active state during execution of an instruction, and a state S2 indicates an active state during suspension (during stalling). A state S3 indicates a sleep state in which the instruction execution of the atomic block is finished.
As shown in FIG. 9, the execution management unit 40 assigns an atomic block to the PE 10 and executes an instruction, thereby first causing the PE 10 to transition to the state S1. The execution management unit 40 sets the “valid flag” corresponding to the PE 10 in the management table stored in the management table storage unit 41 to “1”.

In the state S1, the execution management unit 40 determines whether or not stalling is necessary based on the management table stored in the management table storage unit 41 in response to an inquiry when the PE 10 executes a register read instruction. If it is necessary to stall, a stall instruction is transmitted to the PE 10 to make a transition to the state S2.
In the state S2, when the cause of the stall is solved, the execution management unit 40 transmits a stall release to the PE 10 and makes a transition to the state S1.

In the state S1, when a branch instruction is executed for the PE 10, the execution management unit 40 changes the PE 10 to the state S3.
In addition, in the state S3, when the previously executed atomic block is re-executed (in the case of a cache hit), the execution management unit 40 makes a transition to the state S2 again and executes the instruction stored in the instruction cache unit 11. Let it run.

In the state S3, when the PE 10 is not available and the LRU arbiter 424 determines that the PE 10 is an LRU replacement target, the execution management unit 40 invalidates the PE 10. That is, the execution management unit 40 sets the “valid flag” corresponding to the PE 10 in the management table stored in the management table storage unit 41 to “0”.
Further, when a cache miss occurs, the execution management unit 40 allocates an atomic block to one of the invalidated PEs 10 and makes a transition to the state S1 again.
When the “valid flag” corresponding to all the PEs 10 is “1”, the execution management unit 40 determines that the PE 10 is in the state S3 (sleep state) or the “valid flag” is “0”. Suspend execution of new atomic block.

  The execution management unit 40 updates the management table stored in the management table storage unit 41 when a new atomic block is allocated to the PE 10. Specifically, the execution management unit 40 stores the PC value in “BTA” of the PE 10 and stores the block length of the atomic block in “LGT”. Further, the execution management unit 40 stores “PE_NO” (line number) corresponding to the branch destination PE10 of the atomic block in “PTR1” and “PTR2” of the PE10, and sets the “valid flag” to “1”. .

Next, the cache hit determination by the execution management unit 40 will be described with reference to FIG.
In FIG. 4, when the PE 10 corresponding to the row L1 executes the branch instruction, the comparison circuit 421 compares the PC value with “BTA” of the PE 10 (row L2) corresponding to the atomic block to be executed next. If they match, the H state is output. The AND circuit 422 outputs the result of the logical product operation of the output of the comparison circuit 421 and the “valid flag” of the PE 10 corresponding to the atomic block to be executed next. In the example shown in FIG. 4, since the “valid flag” in the row L2 is “1” (= H state), the AND circuit 422 outputs the H state. Then, the AND circuit 423 performs a logical product operation result (H state) between the branch instruction signal (here, H state) indicating the branch instruction output from the predecoder unit 43 and the output (H state) of the AND circuit 422. ) As a HIT signal. Further, when “BTA” is statically determined, the execution management unit 40 outputs “BTA” in the row L2 to the PC update unit 20 to update the value of the PC 21 to the value of “BTA”. That is, in the example shown in FIG. 4, the execution management unit 40 outputs an H state to the HIT signal, and causes the PE 10 whose “PE_NO” is “6” to execute the instruction stored in the instruction cache unit 11.

Next, the pipeline processing of the PE 10 will be described with reference to FIG.
FIG. 10 is a diagram illustrating an example of pipeline processing of the processor 1 according to the present embodiment.
As shown in FIG. 10, each PE 10 of the processor 1 performs pipeline processing for processing five processes (cycles) of “IF”, “ID”, “RR”, “EX”, and “WR” in parallel. Run.

Here, “IF” is an instruction fetch process, and “ID” is an instruction decode process (control signal generation process). “RR” is an operand reading process from the register, and “EX” is an operation execution process. “WR” is a process of writing a calculation result to a register.
As shown in FIG. 10, for example, the PE 10 executes pipeline processing by shifting and executing five processes (cycles) in the order of “instruction 1”, “instruction 2”,.

Next, an instruction execution process of the processor 1 according to the present embodiment will be described with reference to FIG.
FIG. 11 is a diagram illustrating an example of parallel processing of the PE 10 according to the present embodiment.
FIG. 11A shows an example of a program in the expanded linked list of “atomic block A” to “atomic block D” (AB_A to AB_D). Moreover, FIG.11 (b) has shown PE10 (10-1, 10-2, 10-3, 10-4, ..., 10-N) which the processor 1 has.

FIG. 11C shows an example when the processor 1 executes the atomic blocks (AB_A to AB_D) shown in FIG.
As shown in FIG. 11C, at time T1, the processor 1 first assigns “atomic block A” to the PE 10-1 (PE_1), and the PE 10-1 sequentially assigns the instruction of “atomic block A”. Run.

  Next, when execution of the “atomic block A” by the PE 10-1 is completed at time T2, the processor 1 assigns “atomic block B” to the PE 10-2 (PE_2), and the PE 10-2 receives the “atomic block A”. The instruction “B” is executed sequentially. Here, the instruction cache unit 11 of the PE 10-1 is in a state where “atomic block A” is stored, and the management information corresponding to the PE 10-1 is stored in the management table storage unit 41 as “valid flag” “ It is stored in the state of 1 ″.

  Next, when execution of the “atomic block B” by the PE 10-2 is completed at time T3, the processor 1 assigns “atomic block D” to the PE 10-3 (PE_3), and the PE 10-2 receives the “atomic block B”. The instruction “B” is executed sequentially. Here, the instruction cache unit 11 of the PE 10-2 is in a state where “atomic block B” is stored, and the management information corresponding to the PE 10-2 is stored in the management table storage unit 41 as “valid flag”. It is stored in the state of 1 ″.

Next, when execution of the “atomic block D” by the PE 10-3 is completed at the time T4, the processor 1 stores the instruction of the “atomic block B” stored in the instruction cache unit 11 in the PE 10-2 (PE_2). Is executed. Here, the execution management unit 40 determines a cache hit by the process shown in FIG. 4 described above, and causes the PE 10-2 (PE_2) to re-execute “atomic block B”.
At time T5, the processor 1 further causes the PE 10-3 (PE_3) to execute the instruction of “atomic block D” stored in the instruction cache unit 11. Here, the execution management unit 40 determines a cache hit by the process shown in FIG. 4 described above, and causes the PE 10-3 (PE_3) to re-execute “atomic block D”. Thereby, PE10-2 and PE10-3 are executed in parallel.

At subsequent time T6 and time T7, the processor 1 executes the same processing as at time T4 and time T5, and the PE 10-2 and PE 10-3 are executed in parallel.
In FIG. 11C, a period PT1 after time T4 is a period of parallel execution.
As described above, the execution management unit 40 causes the plurality of PEs 10 (10-2, 10-3) to execute the assigned atomic blocks (“atomic block B” and “atomic block D”) in parallel.

<Data dependency avoidance process>
Next, the data dependence avoidance process of the processor 1 according to the present embodiment will be described.
The register management unit 50 of the processor 1 executes processing for avoiding data dependency between the registers of the PE 10 based on the following basic rules.
(1) When writing data to the register, the PE 10 writes data to its own register. In addition, when the PE 10 performs writing to the register, the PE 10 requests the register management unit 50 to update the update history table, and the register management unit 50 updates the update history table in the update history storage unit 51. .

  (2) The PE 10 makes an inquiry to the register management unit 50 when reading data from the register. Based on the update history table of the update history storage unit 51, the register management unit 50 instructs the suspension of instruction execution (outputs the STALLB signal), and when the cause of the suspension is resolved (for example, write completion), Instruct to release the hold. Based on the update history table, the register management unit 50 causes the PE 10 to read data from either the register of its own PE 10 or the register of the PE 10 executed in the nearest past.

  For example, when there is no RAW hazard in its own PE 10 (“RAW” is “0”), the register management unit 50 completes writing to the register in the PE 10 executed in the nearest past In this case, the data of the register of the PE 10 executed in the nearest past is read into the PE 10 that has requested reading. Further, the register management unit 50 causes the PE 10 that has made a read request to read the data of its own register when a RAW hazard has occurred in its own PE 10 (“RAW” is “1”). .

Next, an operation for generating the STALLB signal when a RAW hazard occurs by the register management unit 50 will be described with reference to FIG.
In FIG. 6, in the PE 10-3 (PE_3) corresponding to the update history information EN2, whether or not the PE 10-3 (PE_3) stalls in the register management unit 50 when a read instruction is executed to the register RegX. Make an inquiry. Since the A flag of the update history information EN2 corresponding to PE10-3 (PE_3) is “0”, the register management unit 50 keeps “RAW” of the update history information EN2 at “0”. Based on the W flag of the update history information EN1 and “RAW” of the update history information EN2, the L state is output to the STALLB signal. As a result, the PE 10-3 (PE_3) suspends execution of the read instruction of the register RegX.

  When the last write in the register RegX is completed in the PE 10 corresponding to the update history information EN1, the register management unit 50 sets the W flag of the update history information EN1 to “1”. As a result, the register management unit 50 outputs an H state to the STALLB signal by the multiplexer 52, and the PE 10 resumes the read instruction for the register RegX.

Next, the RAW hazard processing of the processor 1 between the PEs 10 according to the present embodiment will be described with reference to FIG.
FIG. 12 is a diagram illustrating an example of a RAW hazard process between the PEs 10 of the processor 1 according to the present embodiment.
FIG. 12 shows a state in which two PEs 10 (PE_1, PE_3) execute instructions in parallel, and each PE 10 executes pipeline processing. In FIG. 12, a waveform W1 indicates the logic state of “RAW” of PE_3, and a waveform W2 indicates the logic state of the A flag of PE_3. Waveform W3 shows the logic state of the A flag of PE_1, waveform W4 shows the logic state of the W flag of PE_1, and waveform W5 shows the logic state of the STALLB signal of PE_3. In each waveform, the horizontal axis indicates time, and the vertical axis indicates a logical state.

For example, when the PE 10-1 (PE_1) executes a write instruction to the register RegX at time T11, the register management unit 50 updates the A flag of the management information corresponding to PE_1 to “1” (H state).
Similarly, at time T11, when the PE 10-3 (PE_3) executes a read instruction to the register RegX, the register management unit 50 sets “RAW” of the management information corresponding to PE_3 to “0” (L state). Therefore, the multiplexer 53 selects the PE_1 executed in the past in the past as the RegX reading source. Also, the register management unit 50 sets the STALLB signal of PE_3 to the L state by the multiplexer 52 based on the W flag of the management information corresponding to PE_1 and the “RAW” of the management information corresponding to PE_3. As a result, the instruction execution of PE_3 is suspended.

  Next, at time T12, when the PE 10-1 (PE_1) executes the last write instruction for the register RegX, the register management unit 50 sets the W flag of the management information corresponding to PE_1 to “1” (H state). Update. Based on the W flag of the management information corresponding to PE_1 and “RAW” of the management information corresponding to PE_3, the register management unit 50 sets the STALLB signal of PE_3 to the H state. As a result, the instruction execution suspension of PE_3 is released. Here, a period ST1 from time T11 to time T12 is a stall period. In this case, the PE 10-3 (PE_3) reads the value of the register RegX after the writing of the register RegX by the PE 10-1 (PE_1) is completed, so that the instruction can be executed normally.

Next, with reference to FIG. 13, the RAW hazard processing in the PE 10 of the processor 1 according to the present embodiment will be described.
FIG. 13 is a diagram showing an example of a RAW hazard process in the PE 10 of the processor 1 according to the present embodiment.
FIG. 13 shows a state in which PE10-3 (PE_3) is executing an instruction and executing pipeline processing. In FIG. 13, a waveform W6 indicates the logic state of “RAW” of PE_3, and a waveform W7 indicates the logic state of the A flag of PE_3. Waveform W8 shows the logic state of the STALLB signal of PE_3. In each waveform, the horizontal axis indicates time, and the vertical axis indicates a logical state.

For example, when the PE 10-3 (PE_3) executes a write instruction to the register RegX at time T21, the register management unit 50 updates the A flag of the management information corresponding to PE_3 to “1” (H state).
Next, when PE10-3 (PE_3) executes a read instruction to the register RegX at time T22, the register management unit 50 corresponds to PE_3 because the A flag of the management information is “1” (H state). Management information “RAW” is updated to “1” (1 state). Then, the register management unit 50 uses the multiplexer 53 to select its own PE_3 as the RegX reading source. Also, the register management unit 50 sets the STALLB signal of PE_3 to the H state by the multiplexer 52 based on the A flag of the management information corresponding to PE_3 and the “RAW” of the management information corresponding to PE_3. As a result, the instruction execution of PE_3 is executed as it is without being suspended.
As described above, when writing is performed in the register RegX in the PE 10 itself, the PE 10 reads (reads) data from the register RegX.

<Store buffer processing>
Next, the store buffer process of the processor 1 according to the present embodiment will be described.
Based on the store buffer table of the store buffer storage unit 61, the store buffer unit 60 uses its “Addr” of the load instruction in response to the load instruction, and stores its own on the “FIFO” of the entry table storage unit 62. Find the closest store buffer table including the store buffer table. The store buffer unit 60 transfers the access information data that is the newest (the largest “LPC” value) in the store buffer table and that matches the “Addr” value of the load instruction to the operand data network. Output to NW2 (load bypass process). As a result, the store buffer unit 60 reuses the data previously written (stored) in the data memory 71 and does not need to read (load) the data from the data memory 71 again, so the data is read (loaded) at high speed. )be able to. If the data read from the data memory 71 has not been updated, the store buffer unit 60 reuses the data that has been read (loaded) from the data memory 71 in the past and reuses the data memory again. Since there is no need to read (load) from 71, data can be read (loaded) at high speed.

  Further, the memory management unit 70 searches each store buffer table in the “FIFO” order of the entry table storage unit 62, and sequentially sets the flag “Ld” (load) or “St” (store) on each store buffer table. The data memory 71 is accessed for the row of “1”. The store buffer unit 60 searches the store buffer table, performs load bypass from the row having the corresponding “Addr”, and sets “complete” (completion flag) to “1” upon completion of this access. When the “completion” (completion flag) becomes “1”, the register management unit 50 sets “UPD” and A flag corresponding to the load destination register to “ Set to 1 ”. Further, when the instruction is the last write (load instruction) of the register, the register management unit 50 sets the corresponding W flag to “1”.

  Further, when the instruction is a store instruction, the store buffer unit 60 needs to read the register of the store source. Therefore, the store buffer unit 60 inquires the management table of the register management unit 50. Suspend instruction execution until possible. In addition, after reading the register, the store buffer unit 60 stores the register value and the address value in “Data” and “Addr” of the store buffer table. Further, the store buffer unit 60 sets “end” (end flag) to “1”.

  Next, when “St” of the store buffer table is “1”, the memory management unit 70 waits until the corresponding “end” (end flag) becomes “1” (becomes a stalled state). The memory management unit 70 starts the memory access to the data memory 71 when the “end” (end flag) becomes “1”, and when the store (write) is completed, the store buffer unit At 60, the corresponding “complete” (completion flag) is set to “1”, and the process proceeds to the next memory access process.

  As described above, when there is an access request from the PE 10 to the data memory 71, the store buffer unit 60 accesses the data memory 71 based on the store buffer table corresponding to the PE 10 stored in the store buffer storage unit 61. To control.

  As described above, the processor 1 according to the present embodiment includes the plurality of PEs 10 (processing elements) and the execution management unit 40 (execution management unit). Each of the plurality of PEs 10 includes an instruction cache unit 11 (temporary storage unit) that temporarily stores an assigned atomic block (unit instruction sequence), and is included in the atomic block stored in each instruction cache unit 11. The instruction is configured to be executable. The execution management unit 40 divides into atomic blocks, sequentially assigns the divided atomic blocks to each of the plurality of PEs 10, and causes the plurality of PEs 10 to execute the assigned atomic blocks in parallel. Here, an atomic block is an instruction sequence that does not include a branch instruction in the middle of a program that is an instruction sequence of the assembly language or lower level, and has a branch instruction at the beginning and a branch instruction at the end. It is.

As a result, the processor 1 according to the present embodiment assigns to the PR 10 in units of atomic blocks, and causes the assigned atomic blocks to be executed in parallel by the plurality of PEs 10, so that, for example, high-speed numerical processing can be performed. Note that the processor 1 according to the present embodiment is effective for the following application software.
(1) An application that requires high-speed processing for a single thread.
(2) An application having an algorithm having a loop structure in which a plurality of atomic blocks and this block group are configured within the number of prepared PEs 10.
(3) In addition, an application configured with an algorithm having a complicated control flow.

For example, the processor 1 according to the present embodiment is effective for control problems, graph problems, information retrieval, computer-aided design, theorem proving, and the like, which are non-numerical calculation applications that satisfy the above requirements.
Further, the processor 1 according to the present embodiment can execute non-numeric calculation processing at high speed by causing a plurality of PEs 10 to execute in parallel without preparing a dedicated compiler.

In this embodiment, the execution management unit 40 assigns the atomic block to any one of the plurality of PEs 10 when the divided atomic block is not stored in any instruction cache unit 11 of the plurality of PEs 10. When the divided atomic block is already stored in any instruction cache unit 11 of the plurality of PEs 10, the execution management unit 40 stores the atomic block already stored in the instruction cache unit 11 in the PE 10 Are executed in parallel.
Thereby, the processor 1 according to the present embodiment can easily realize allocation to the PE 10 and parallel execution in units of atomic blocks.

Further, the processor 1 according to the present embodiment has the head position information (“BTA”) indicating the position of the head instruction of the atomic block in the program and the valid information (“valid flag”) indicating whether or not the atomic block is valid. ) And the next execution information (“PTR1”, “PTR2”) indicating the PE10 to be executed next, the management table storage unit 41 that stores a management table having a plurality of management information. When a branch instruction is detected in the program, the execution management unit 40 has an atomic block to be executed next in any instruction cache unit 11 of the plurality of PEs 10 based on the management table stored in the management table storage unit 41. It is determined whether it is already stored and valid.
Thereby, the processor 1 according to the present embodiment can more easily determine the cache miss and the cache hit based on the management table.

Further, in this embodiment, the execution management unit 40 is based on the next execution information (“PTR1”, “PTR2”) from the management table stored in the management table storage unit 41 when a branch instruction is detected in the program. Thus, the head position information (“BTA”) and valid information (“valid flag”) corresponding to the atomic block to be executed next to the branch instruction are acquired. Then, the execution management unit 40 matches the next execution information when the position indicated by the acquired head position information matches the execution position of the program to be executed next and the acquired valid information indicates validity. The PE 10 stores the atomic block in the instruction cache unit 11 and determines that it is in a valid state.
Thereby, the processor 1 according to the present embodiment can appropriately determine a cache hit by a simple method.

Further, in the present embodiment, the execution management unit 40 has a plurality of positions when the position indicated by the acquired head position information does not match the execution position of the program to be executed next, or when the acquired valid information indicates invalidity. The atomic block to be executed next is assigned to one of the PEs 10 and the management table is updated in correspondence with the assigned atomic block.
Thereby, the processor 1 by this embodiment can allocate an atomic block to PE10 appropriately by simple prescription in the case of a cache miss.

In the present embodiment, when the execution management unit 40 assigns the next atomic block to be executed to one of the plurality of PEs 10, the execution management unit 40 stores the head position information (“BTA”) corresponding to the atomic block in the management table. At the same time, the valid information (“valid flag”) is updated to a value indicating invalidity. Then, when the PE 10 completes execution of the atomic block, the execution management unit 40 updates the valid information (“valid flag”) corresponding to the atomic block to a value indicating validity.
Thereby, the processor 1 by this embodiment can manage the atomic block already performed appropriately.

In the present embodiment, the PE 10 executes instructions by pipeline processing.
Thereby, the processor 1 according to the present embodiment can execute instructions at higher speed by pipeline processing.

In the present embodiment, each of the plurality of PEs 10 includes a register file unit 12 (register) that is used to execute an instruction. The processor 1 further includes a register management unit 50 (register management unit). When a RAW hazard, which is data-dependent due to reading after register writing, occurs between the plurality of PEs 10, the register management unit 50 creates an atomic block by the PE 10 that has performed writing to the register in the nearest past. Until the writing to the register is completed, the instruction execution of the PE 10 that reads the register is suspended.
As a result, the processor 1 according to the present embodiment can appropriately execute instructions even when a RAW hazard occurs. That is, the processor 1 according to the present embodiment can avoid data dependency between the registers of the PE 10.

The processor 1 according to the present embodiment also includes PE identification information (such as “PE — 1”) for identifying the PE 10, update information (“UPD”) indicating that the register has been updated in the execution of the atomic block, and the atomic block. Update history information associating completion information (W flag) indicating completion of the last register write with execution information (A flag) indicating that register write has been executed for the number of PEs 10. An update history storage unit 51 that stores an update history table is provided. Then, the register management unit 50 determines whether or not a RAW hazard has occurred between the PEs 10 based on the update history table stored in the update history storage unit 51, and when a RAW hazard has occurred between the PEs 10 (for example, The instruction of the PE 10 in which the RAW hazard has occurred is based on the completion information corresponding to the PE 10 that has been writing to the register in the past in the update history table, when “RAW” is “0”). Defer execution.
Thereby, the processor 1 according to the present embodiment can appropriately hold (stall) the instruction execution of the PE 10 in which the RAW hazard has occurred when the RAW hazard has occurred based on the update history information.

In the present embodiment, the register management unit 50 determines whether or not a RAW hazard has occurred based on the execution information (A flag), and based on the update information (“UPD”) The PE 10 that is writing to the register is selected.
Thereby, the processor 1 according to the present embodiment can appropriately detect the occurrence of the RAW hazard and select the PE 10 that has performed writing to the register in the near past by a simple method.

In the present embodiment, each of the plurality of PEs 10 includes a plurality of registers, and the update history storage unit 51 stores an update history table corresponding to each of the plurality of registers.
Thereby, the processor 1 according to the present embodiment can cope with the case where each PE 10 includes a plurality of registers. Further, the processor 1 according to the present embodiment can perform more complicated processing when the PE 10 includes a large number (a plurality) of registers.

The processor 1 according to the present embodiment includes a store buffer storage unit 61 and a store buffer unit 60 (store buffer control unit). The store buffer storage unit 61 associates local position information (“LPC”) corresponding to each instruction included in the atomic block with access information indicating a history of accessing the data memory 71 (external storage unit). The table is stored for the number of PEs 10. When there is an access request from the PE 10 to the data memory 71, the store buffer unit 60 controls access to the data memory 71 based on the store buffer table corresponding to the PE 10 stored in the store buffer storage unit 61.
As a result, the processor 1 according to the present embodiment can appropriately perform processing even when accessing the data memory 71. Further, the processor 1 according to the present embodiment uses the store buffer storage unit 61 to store data read in the past from the data memory 71 or stored in the data memory 71 via the store buffer storage unit 61, for example. Since the data can be reused, the data access processing time can be shortened.

In this embodiment, the access information includes type information (“Ld”, “St”, etc.) indicating the type of access, storage location information (“Addr”) accessed in the data memory 71, and accessed data ( “Data”). In response to an access request for reading data from the data memory 71, the store buffer unit 60 outputs the data to the PE 10 when data corresponding to the access request exists in the store buffer table. The store buffer unit 60 outputs the data read from the data memory 71 to the PE 10 when there is no data corresponding to the access request in the store buffer table.
Thereby, the processor 1 according to the present embodiment can appropriately read data from the data memory 71 by a simple method.

In the present embodiment, the store buffer unit 60 stores the local position information and the access information in association with each other in the store buffer table corresponding to the PE 10 in response to an access request for writing data in the data memory 71. At the same time, the data is stored in the data memory 71.
Thereby, the processor 1 according to the present embodiment can appropriately write data from the data memory 71 by a simple method.

In addition, this invention is not limited to said embodiment, It can change in the range which does not deviate from the meaning of this invention.
For example, in the above embodiment, the execution management unit 40 includes the management table storage unit 41. However, the management table storage unit 41 may be provided outside the execution management unit 40. Further, the example in which the register management unit 50 includes the update history storage unit 51 has been described, but the update history storage unit 51 may be provided outside the register management unit 50. Further, the example in which the store buffer unit 60 includes the store buffer storage unit 61 and the entry table storage unit 62 has been described. However, either the store buffer storage unit 61 or the entry table storage unit 62 is provided outside the store buffer unit 60. One or both may be provided.

In the above embodiment, the update history storage unit 51 and the entry table storage unit 62 are configured as FIFOs. However, the update history storage unit 51 and the entry table storage unit 62 may be configured cyclically by providing pointers.
Further, in the above-described embodiment, the example has been described in which the register management unit 50 instructs the PE 10 to suspend execution of the instruction and to release the suspension, but the inquiry to the register management unit 50 at the time of a read instruction to the register Then, the PE 10 may hold the execution of the instruction by itself, and the register management unit 50 may instruct the PE 10 to release the hold in response to the inquiry.

In the above embodiment, the example in which the processor 1 accesses the data memory 71 via the memory management unit 70 has been described. However, the present invention is not limited to this, and the processor 1 and the data memory 71 via the cache memory are not limited thereto. You may make it access, and you may make it access the data memory 71 directly.
Further, the configuration of the execution management unit 40 is not limited to the configuration illustrated in FIG. 4, and the execution management unit 40 may be realized by other configurations. Further, the configuration of the register management unit 50 is not limited to the configuration shown in FIG. 6, and the register management unit 50 may be realized by other configurations.

  In the above embodiment, the example in which the processor 1 centrally manages the execution management unit 40 and the management table storage unit 41 in one place has been described. However, the present invention is not limited to this. For example, the processor 1 may include a part or all of the execution management unit 40 and the management table storage unit 41 distributed in each PE 10 and may be managed in a distributed manner. Even when the processor 1 is implemented in such a distributed type, the processor 1 has the same effect as the above embodiment.

  DESCRIPTION OF SYMBOLS 1 ... Processor 10, 10-1, 10-2, 10-3, 10-4, 10-N ... PE, 11 ... Instruction cache part, 12 ... Register file part, 13 ... Instruction execution part, 20 ... PC update , 21 ... PC, 30 ... instruction fetch unit, 31 ... IR, 40 ... execution management unit, 41 ... management table storage unit, 42 ... cache miss handler unit, 43 ... predecoder unit, 50 ... register management unit, 51 ... Update history storage unit, 52, 53 ... multiplexer, 422, 423 ... AND circuit, 60 ... store buffer unit, 61 ... store buffer storage unit, 62 ... entry table storage unit, 70 ... memory management unit, 71 ... data memory, 421 ... Comparison circuit, 424 ... LRU arbiter, 425 ... Handler part, NW1 ... Instruction network, NW2 ... Operand data Ttowaku

Claims (13)

A plurality of processing elements each having a temporary storage unit for temporarily storing an assigned unit instruction sequence, and capable of executing instructions included in the unit instruction sequence stored in the temporary storage unit;
A program that is an instruction sequence at a level of assembly language or lower is changed to the unit instruction sequence that is an instruction sequence that does not include a branch instruction in the middle and that has a branch instruction at the beginning and a branch instruction at the end. An execution management unit that divides and sequentially assigns the divided unit instruction sequence to each of the plurality of processing elements, and causes the plurality of processing elements to execute the assigned unit instruction sequence in parallel ;
Start position information indicating the position of the start instruction of the unit instruction sequence in the program, valid information indicating whether or not the unit instruction sequence is valid, and next execution information indicating the processing element to be executed next A management table storage unit for storing a management table having a plurality of associated management information ,
The execution management unit
When the divided unit instruction sequence is not stored in any of the temporary storage units of the plurality of processing elements, the unit instruction sequence is assigned to any of the plurality of processing elements,
When the divided unit instruction sequence is already stored in the temporary storage unit of any of the plurality of processing elements, the unit instruction sequence already stored in the temporary storage unit is connected in parallel to the processing element. Let it run
When a branch instruction is detected in the program, based on the management table stored in the management table storage unit, the unit instruction sequence to be executed next is stored in the temporary storage unit in any of the plurality of processing elements. Determine whether it is already stored and valid
Processor, wherein a call. The execution management unit
When the branch instruction is detected in the program, the head position corresponding to the unit instruction sequence to be executed next to the branch instruction based on the next execution information from the management table stored in the management table storage unit Information and the valid information,
If the position indicated by the acquired head position information matches the execution position of the next program to be executed, and the acquired valid information indicates validity, the processing element that matches the next execution information is , the unit instruction sequence is stored in the temporary storage unit, and processor according to claim 1, wherein the determining that the valid state. The execution management unit
When the position indicated by the acquired head position information does not match the execution position of the next program to be executed or when the acquired valid information indicates invalid, the next execution is performed on one of the plurality of processing elements. The processor according to claim 2 , wherein the unit instruction sequence to be assigned is assigned and the management table is updated in correspondence with the assigned unit instruction sequence. The execution management unit
When allocating the unit instruction sequence to be executed next to one of the plurality of processing elements, the start position information corresponding to the unit instruction sequence of the management table is stored, and the valid information indicates invalidity Update to value,
The processor according to claim 3 , wherein when the processing element completes execution of the unit instruction sequence, the valid information corresponding to the unit instruction sequence is updated to a value indicating validity. The processor according to any one of claims 1 to 4 , wherein the processing element executes the instruction by pipeline processing. Each of the plurality of processing elements has a register used to execute the instruction,
Furthermore, when a RAW hazard that is data-dependent due to reading after writing to the register occurs between the plurality of processing elements, the unit by the processing element that has performed writing to the register in the nearest past until the write to the register of the instruction sequence is completed, any one of claims 1 to 5, characterized in that it comprises a register management unit for holding the instruction execution of the processing elements to perform the reading of the register The processor according to item.   A plurality of processing elements each having a temporary storage unit for temporarily storing an assigned unit instruction sequence, and capable of executing instructions included in the unit instruction sequence stored in the temporary storage unit;
  A program that is an instruction sequence at a level of assembly language or lower is changed to the unit instruction sequence that is an instruction sequence that does not include a branch instruction in the middle and that has a branch instruction at the beginning and a branch instruction at the end. An execution management unit that divides, sequentially assigns the divided unit instruction sequence to each of the plurality of processing elements, and causes the plurality of processing elements to execute the assigned unit instruction sequence in parallel;
  With
  Each of the plurality of processing elements has a register used to execute the instruction,
  Furthermore, when a RAW hazard that is data-dependent due to reading after writing to the register occurs between the plurality of processing elements, the unit by the processing element that has performed writing to the register in the nearest past A register management unit that suspends instruction execution of the processing element that executes reading of the register until the writing of the instruction sequence to the register is completed.
  A processor characterized by that. PE identification information for identifying the processing element, update information indicating that the register has been updated in the execution of the unit instruction sequence, and completion indicating that the last write of the register in the unit instruction sequence has been completed An update history storage unit for storing an update history table having update history information in association with information and execution information indicating that writing of the register has been executed, for the number of processing elements;
The register management unit
Based on the update history table stored in the update history storage unit, it is determined whether or not the RAW hazard has occurred,
In the processing element that reads from the register, a RAW hazard in the processing element does not occur, and the processing element that reads from the register and a write to the register that is closest to the past are written. When a RAW hazard between the processing elements occurs between the processing elements to be performed, the register based on the completion information on the register to be written for the processing element to be written in the nearest past The processor according to claim 6 , wherein the processor controls whether or not to suspend the execution of the instruction of the processing element that reads from the processing element . The register management unit
Whether or not a RAW hazard has occurred in the processing element in the processing element that reads the register based on the execution information related to the register to be read for the processing element that reads the register the processor of claim 8, wherein the determining whether. Each of the plurality of processing elements includes a plurality of the registers,
The processor according to claim 8 or 9 , wherein the update history storage unit stores the update history table corresponding to each of the plurality of registers. A store buffer that stores a store buffer table in which local position information corresponding to each instruction included in the unit instruction sequence and access information indicating a history of accessing the external storage unit are associated with each other as many as the number of the processing elements. A storage unit;
A store that controls access to the external storage unit based on the store buffer table corresponding to the processing element stored in the store buffer storage unit when there is an access request from the processing element to the external storage unit the processor according to any one of claims 1 0 to claim 1, characterized in that it comprises a buffer control unit. The access information is associated with type information indicating the type of access, storage location information accessed in the external storage unit, and accessed data.
The store buffer control unit
In response to the access request for reading data from the external storage unit, when the data corresponding to the access request exists in the store buffer table, the data is output to the processing element,
The processor of claim 1 1, wherein the data corresponding to the access request to the store buffer table in the absence, and outputs the data read from the external storage unit to the processing element. The store buffer control unit
In response to the access request for writing data to the external storage unit, the local location information and the access information are stored in association with each other in the store buffer table corresponding to the processing element, and the external storage unit the processor of claim 1 1 or claim 1 2, characterized in that to store the data.

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