EP2845131A2 - Bibliothèque de cellules et procédé de conception d'un circuit intégré asynchrone - Google Patents
Bibliothèque de cellules et procédé de conception d'un circuit intégré asynchroneInfo
- Publication number
- EP2845131A2 EP2845131A2 EP13723839.0A EP13723839A EP2845131A2 EP 2845131 A2 EP2845131 A2 EP 2845131A2 EP 13723839 A EP13723839 A EP 13723839A EP 2845131 A2 EP2845131 A2 EP 2845131A2
- Authority
- EP
- European Patent Office
- Prior art keywords
- terminal
- signal
- cell
- asynchronous
- circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/396—Clock trees
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/35—Delay-insensitive circuit design, e.g. asynchronous or self-timed
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/10—Distribution of clock signals, e.g. skew
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/12—Synchronisation of different clock signals provided by a plurality of clock generators
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/25—Testing of logic operation, e.g. by logic analysers
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4004—Coupling between buses
- G06F13/4009—Coupling between buses with data restructuring
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2111/00—Details relating to CAD techniques
- G06F2111/20—Configuration CAD, e.g. designing by assembling or positioning modules selected from libraries of predesigned modules
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2119/00—Details relating to the type or aim of the analysis or the optimisation
- G06F2119/12—Timing analysis or timing optimisation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Definitions
- the present invention relates to a library of standard cells for producing an asynchronous circuit and a method for designing a synchronous circuit implementing these cells.
- An integrated circuit can be synchronous or asynchronous.
- a synchronous integrated circuit is an integrated circuit whose operation is clocked by a periodic signal distributed throughout the circuit: the clock signal.
- An asynchronous integrated circuit is an integrated circuit whose operation is provided by means other than the use of a clock signal. The control of an asynchronous integrated circuit is generally done locally by a synchronization between functional blocks.
- synchronous integrated circuit design assistance tools implement optimization algorithms that have been perfected over many years and are effective in particular for reducing the area occupied by the circuit, for reducing the consumption of the circuit, for increase the operating speed of the circuit, etc.
- Help tools typically use standard cell libraries. Each cell corresponds to a set of elemen tary ⁇ components (e.g., MOS transistors) filling a func- tion (e.g., a gate OR, AND, NOR or NAND, an inverter, a memory, etc.).
- a library contains a set of parameters defining the circuit diagram and topology, as well as the input and output terminals of each cell. Each cell is further defined by parameters such as response time, power output, and so on.
- cells of the library are selected, arranged, and interconnected to provide the required functions of the circuit.
- the synchronous integrated circuit design assistance tools can not currently be used directly for the optimization of asynchronous integrated circuit design. Indeed, integrated circuits asyn ⁇ chrons have particular characteristics that are generally little or present in synchronous circuits, which are not supported by the support tools in the design of synchronous integrated circuits. It is usually not possible to benefit from all the optimization capabilities of these tools.
- an object of the present invention is to provide a library of cells, allowing the use of synchronous circuit design assistance tools for the design of asynchronous circuits.
- Another object of the present invention is to provide a method of designing an asynchronous integrated circuit implementing tools for assisting the design of synchronous integrated circuits.
- an embodiment of the present invention provides a method for designing a computer-implemented asynchronous integrated circuit from a cell library comprising at least one cell having signal propagation parameters between a first terminal and a second terminal and between the second terminal and a third terminal are a function of the signal propagation parameter between the first terminal and the third terminal, the method comprising the following steps:
- the library comprises, for said cell, an indication that the second terminal is intended to receive a fictitious clock signal during the design of the asynchronous integrated circuit by a tool to assist the design of synchronous circuits.
- the cell is representative of a portion of the asynchronous circuit, the second terminal being intended, in operation, receiving a reset signal of the circuit portion.
- the cell is representative of a portion of the asynchronous circuit
- the second terminal does not correspond to a physical terminal of the portion intended, in operation, to provide or receive signals.
- the cell comprises a first signal propagation parameter from the first terminal to the second terminal and a second signal propagation parameter from the second terminal to the third terminal, the first and second parameters. being obtained from a third signal propagation parameter from the first terminal to the third terminal, the third parameter corresponding to a matrix of elements Dr (A ⁇ z) or 1 is an integer varying from 1 to P and j is an integer varying from 1 to Q, the second parameter corresponding to a matrix of elements gr ( R ⁇ z ) 0 ] 3 -
- - enu according to the following relation:
- J being a natural integer selected from 1 to Q.
- the cell further comprises a fourth terminal B, a fourth signal propagation parameter from the fourth terminal to the third terminal corresponding to a matrix of elements D ⁇ , the library comprising in addition, a fifth signal propagation parameter from the fourth terminal to the second terminal, the fifth parameter corresponding to a matrix of elements s ' B ⁇ R ' obtained according to the following relation:
- Margin is a real number greater than or equal to zero, which is constant independently of i or which depends on the transition time of the dummy clock signal on the second terminal.
- the first terminal is, in operation, a terminal for receiving a first signal alternating between two states
- the third terminal being, in operation, a terminal for providing a second alternating signal. between two states and the third parameter corresponding to the duration between a change of state of the first signal and a change of state of the second signal.
- the second terminal corresponds to the terminal of the portion of the asynchronous circuit intended, in operation, to receive a reset signal of said portion of the asynchronous circuit
- the method comprising a step of designing the asynchronous circuit.
- a clock tree for transmitting the dummy clock signal to said portion of the asynchronous circuit, the clock shaft being used in operation as a distribution network of the reset signal to said portion of the asynchronous circuit.
- the verification step is performed with an asynchronous model to simulate the operation of said portion of the asynchronous circuit.
- An embodiment of the present invention also provides computer readable storage means storing a computer program comprising a set of computer executable instructions for implementing the previously defined method.
- An embodiment of the present invention also provides a computer readable storage means storing a cell library for carrying out the previously defined method.
- Figure 1 illustrates, schematically, an example of asynchronous circuit
- FIG. 2 schematically represents an exemplary asynchronous pipeline circuit
- FIG. 3 schematically illustrates an exemplary asynchronous circuit adapted to the implementation of a "1 out of 2" coding
- FIG. 4 is a timing diagram illustrating a "handshake" type data exchange protocol between the functional blocks of FIG. 3;
- Figure 5 schematically shows a general example of a stage of an asynchronous pipeline
- Figure 6 schematically shows a stage of a WCHB pipeline
- Figure 7 schematically shows a stage of an RSPCHB pipeline
- Figure 8 schematically shows a stage of a PCHB pipeline
- Figure 9 schematically shows a stage of a PCFB pipeline
- FIGS. 10 and 11 show exemplary embodiments of a functional cell of the WCHB stage of FIG. 6;
- FIGS. 12 and 13 show exemplary embodiments of a functional cell of the RSPCHB stage of FIG. 7;
- FIGS. 14 and 15 show exemplary embodiments of a functional cell of the PCHB stage of FIG. 8 or of the PCFB stage of FIG. 9;
- FIG. 16 represents an exemplary embodiment of a door C
- FIG. 17 represents a more detailed exemplary embodiment of the WCHB stage of FIG. 6;
- Fig. 18 is a timing chart illustrating the data exchange protocol of the stage of the WCHB pipeline shown in Fig. 17;
- Fig. 19 shows a more detailed exemplary embodiment of the PCHB pipeline functional cell of Fig. 14;
- Figure 20 schematically shows an example of a path traversed by a signal in an asynchronous pipeline
- Fig. 21 shows an example of a known library cell representing an asynchronous protocol rendezvous element
- Fig. 22 shows an example of a library cell according to the invention showing the asynchronous protocol rendezvous element of Fig. 21;
- FIG. 23 represents, in the form of a block diagram, an exemplary embodiment of a method for designing a cell according to the invention.
- Fig. 24 schematically shows paths traversed by signals in the pipeline of Fig. 20 using the cells shown in Fig. 22;
- Fig. 25 schematically shows other paths traversed by signals in the pipeline of Fig. 20 to illustrate an alternative embodiment of the cell design method according to the invention.
- FIG. 26 represents, in the form of a block diagram, an exemplary embodiment of a method for designing an asynchronous circuit according to the invention.
- the high and low levels of different binary signals may be different.
- the inverse of a binary signal at "1” corresponds to the binary signal at "0” and the inverse of a binary signal at "0" corresponds to the binary signal at "1".
- Asynchronous circuits are often broken down into functional blocks between which data (called tokens) communicate via communication channels.
- FIG. 1 represents a transmitting functional block 10 (Proc A) connected to a receiver functional block 12 (Proc B) via a communication channel 14.
- the communication channel 14 corresponds to the wires used for signal transmission, Rdata and Rack, between the transmitter 10 and the receiver 12 and the communication protocol used to carry out the transmission of the signals.
- the transmitted signals comprise the control signals dedicated to the communication between the blocks 10, 12 and signals carrying the other data.
- the set of wires carrying the data other than the control signals is called data bus.
- the functional blocks of an asynchronous circuit can be arranged in a succession of several stages, each stage being connected to a previous stage of the succession and to a next stage of the succession.
- Such a circuit is called a "pipeline circuit” or "pipeline”. Examples of pipelines will now be described.
- FIG. 2 schematically represents an example of a pipeline 20.
- the circuit 20 comprises a succession of blocks functional 22 (Floor). Each functional block 22 is connected to the next block by a communication channel 24. Each functional block 22 supplies the multi-bit Rdata data signal to the next functional block in the succession of functional blocks and receives the one-bit Rack acknowledgment signal. the next functional block. Each functional block 22 provides a one-bit Lack acknowledgment signal to the preceding function block in the sequence of function blocks and receives a multi-bit Ldata data signal from the preceding function block.
- the Ldata signal of a given stage corresponds to the Rdata signal of the preceding stage
- the Lack signal of a given stage corresponds to the Rack signal of the preceding stage
- the Rdata signal of a given stage corresponds to the Ldata signal of the next stage
- the Rack signal of a given stage corresponds to the Lack signal of the next stage.
- the flow of a pipeline is the number of chips per second that passes through a given floor. Latency is the time it takes for a datum to pass through the stages of the pipeline.
- the cycle time of a stage is the minimum time that separates the taking into account of two successive data in this stage.
- the pipeline may be a linear pipeline as shown in FIG. 2.
- each stage 22 has a single input channel (transmitting the Lack and Ldata signals) and a single output channel (transmitting the Rack and Rdata signals). ).
- the pipeline may be a non-linear pipeline. It then comprises at least one stage which may have at least two input channels connected to two different previous stages and / or at least two output channels connected to two different subsequent stages.
- An example of coding data exchanged between two stages is to add a wire to the data bus to specify that the data is valid.
- This type of coding is called coding "grouped data".
- Another example of coding of the data is to integrate the validity information into the data transported by the data bus. This is called “time-sensitive" coding.
- An example of time-lagless encoding is 4-state coding. In this encoding, each data bit is represented by two wires. Of the four possible state combinations for these two wires, half (for example, the combinations 00 and 10) are reserved for the bit value "0", the other half (for example the combinations 11 and 01) is reserved. to the bit value "1".
- time-sensitive coding is 3-state coding.
- each data bit is also represented by two wires.
- a single combination of states of the wires represents a bit value (for example, the combination 01 for the bit "1" and the combination 10 for the bit "0"), whereas the third combination (for example the combination 00) indicates the invalid state and the fourth combination (e.g. combination 11) is not used.
- the 3-state coding is a special case of coding "1 out of N" in which the transmission of an N-base digit used N wires.
- Each wire in the high state represents a digit in base N and the invalid state is obtained by the zeroing of all the wires. Combinations where two wires are simultaneously in the high state are forbidden. There is similarly an "M out of N" coding.
- the present invention can be implemented for the design of an asynchronous circuit implementing a coding "grouped data" or a coding "insensitive to delays".
- the communication protocol corresponds to the set of rules governing the exchange of signals within the communication channel 14 between the two functional blocks 10 and 12.
- an example of a communication protocol between functional blocks is the type protocol "hand shake".
- the protocol of the "handshake" type can be a 4-phase or 2-phase protocol.
- FIG. 3 represents an exemplary embodiment of communication channel 14 adapted to the implementation of a "1 of 2" type coding.
- the communication channel 14 comprises three wires carrying data signals CO, Cl and the acknowledgment signal Rack.
- Figure 4 illustrates the principle of a four-phase "handshake" protocol between functional blocks 10 and 12 of Figure 3 for "1 out of 2" data coding.
- the data transferred corresponds to a bit at "0" when the signal CO is at “1” and the signal Cl is at “0” and the data transferred corresponds to a bit at " 1 "when the signal C0 is at” 0 "and the signal Cl is at” 1 ". In other cases, the data is not valid.
- the acknowledgment signal Rack is valid when it is at "0".
- Moments tg to tg are successive moments.
- the signals C0 and C1 are at “0" and the acknowledgment signal Rack is at "1". There is no valid data to transfer.
- the signal C0 goes to "1".
- the receiver 12 detects the new data (data bit equal to “0"), performs the processing of this data and activates the acknowledgment signal Rack by setting it to "0" at time -2.
- the transmitter 10 detects the acknowledgment signal Rack and invalidates the data by putting the signal C0 at "0" at time t3.
- the receiver 12 detects the invalid state of the data and deactivates the acknowledgment signal Rack by setting it to "1" at time t / [ .
- Instants t5 to tg are associated with the transfer of another data (data bit equal to "1").
- Asynchronous circuits can be quasi-insensitive circuits to delays or circuits QDI (acronym for Quasi-Delay Insensitive).
- QDI circuits uses the concept of isochronous fork, that is to say a fork which connects a single transmitter to two receivers and for which the propagation delays of a signal between the transmitter and the receivers are identical.
- a QDI circuit is an asynchronous circuit for which: the delay of propagation of a signal in a wire or in a functional block can take any value;
- the acknowledgment can be made only for one of the branches of the fork.
- the present invention is particularly suitable for QDI asynchronous pipelines. Unless otherwise indicated, in the following description, the present invention is described for the design of asynchronous QDI pipelines.
- pipelines There are several types of pipelines whose structure depends on the communication protocol implemented for the exchange of data between the stages of the pipeline. Examples of pipelines whose inter-floor communication protocol follows the "handshake" protocol described earlier are the WCHB (English acronym for Weak-Condition Half-Buffer) pipeline, the RSPCHB pipeline (acronym for Reduced-Stack Pre Half-Buffer load), the PCHB pipeline (Pre-Charge Half-Buffer) and the PCFB pipeline (Pre-Charge Full-Buffer).
- WCHB English acronym for Weak-Condition Half-Buffer
- RSPCHB pipeline an RSPCHB pipeline
- PCHB pipeline Pre-Charge Half-Buffer
- PCFB pipeline Pre-Charge Full-Buffer
- FIG. 5 schematically represents an exemplary embodiment of a stage 26 enabling the realization of a pipeline stage WCHB, RSPCHB, PCHB or PCFB.
- the stage 26 comprises a functional block 28 receiving the signal Ldata (N bits) and providing the signal Rdata (M bits), N and M being integers which can be different.
- the functional block 28 is adapted to perform operations on Ldata data which depend in particular on the type of pipeline.
- the functional block 28 further receives, at a terminal Ra, the acknowledgment signal Rack provided by the next stage of the pipeline.
- the function block 28 may further receive a Reset reset signal at a Rst terminal.
- the block functional 28 may further comprise an EN terminal for receiving an Enable activation signal.
- Functional block 28 comprises M cells (Cell) 29.
- the cells 29 are generally identical.
- Each cell 29 receives the N-bit Ldata signal, performs an operation on the data Ldata and provides, as a function of the result of the operation ⁇ tion, a one-bit signal.
- the M 1-bit signals provided by the M cells 29 form the Rdata signal.
- Each cell 29 also receives the acknowledgment signal Ra, the activation signal Enable and the reset signal Reset.
- Each cell 29 comprises input terminals, an output terminal and, like the functional block 28, a terminal Ra for receiving the acknowledgment signal Rack and optionally a terminal EN for receiving the Enable signal and / or a terminal Rst of receiving the Reset reset signal.
- the stage 26 may comprise an upstream detection block 30 which receives the Ldata data and which provides a one-bit Ldetect signal.
- the Ldetect signal is active if valid Ldata data is present at the input of the functional block 28.
- the stage 26 comprises a downstream detection block 32 which receives the Rdata data and which provides a signal Rdetect to a bit.
- the Rdetect signal is active if the function block 28 provides new valid Rdata data.
- the stage 26 may comprise a synchronization block 34 which receives the signals Ldetect and Rdetect and which supplies the acknowledgment signal Lack to the preceding stage of the pipeline.
- the synchronization block 34 may furthermore provide the Enable activation signal to the terminal EN of the functional block 28.
- the stage 26 can be realized by providing that the Rack or Lack acknowledgment signals are active at the low level or at the high level. Similarly, the Ldetect and Rdetect signals can be active at the low level or at the high level. In the case where the active level of the signals Ldetect and Rdetect is the low level, the outputs of the detection blocks 30 and 32 are represented with an inverter.
- Fig. 6 shows an exemplary embodiment of a stage 36 of a WCHB pipeline which corresponds to a particular example of the stage 26 of Fig. 5 in which the upstream detection block 30 is not present.
- the Enable signal is not present.
- the sync block 34 corresponds to a thread receiving the output of the downstream detection block 32 and furnace ⁇ ning the Lack acknowledgment signal.
- the signal réinitia ⁇ lisation Reset may not be present.
- the communication protocol of a stage of the WCHB pipeline comprises the following successive steps:
- FIG. 7 shows an exemplary embodiment of a stage 38 of an RSPCHB pipeline that corresponds to a particular example of the stage 26 of FIG. 5 in which the upstream detection block 30 is not present.
- the Enable signal is not present.
- the synchronization block 34 comprises a gate C 40 and an inverter 42.
- the gate C 40 comprises a first input receiving the output of the downstream detection block 32 and a second input receiving a 1-bit request signal Lreq from the previous stage. pipeline.
- Gate C 40 provides a 1-bit Rreq request signal to the next stage of the pipeline.
- the signal Rreq is also supplied to the input of the inverter 42 which supplies the acknowledgment signal Lack. Reset reset signal may not be present.
- a gate C (also called Muller gate or element C) is a gate which outputs the value present at the inputs of the gate when these inputs are identical, and which otherwise maintains the last value supplied.
- a gate C may comprise an additional input receiving a Reset reset signal which, when activated, sets the output signal of the gate to "0" and does not affect the output signal of the gate when it does not. is not activated.
- a door C can have two or more entries of two entries.
- An asymmetric gate C is a variant of the gate C described above according to which first input signals cause the output to be set to "1" and second input signals, which are not always the same as the first signals of entrance, make the exit go down to "0". When the first input signals are all "1”, the output goes to "1". When the second input signals are all "0”, the output goes to "0". If neither of these conditions is true, the output remains unchanged.
- a symmetrical or asymmetric gate C makes it possible to realize in an asynchronous circuit a rendezvous function (also called synchronization function) between two signals or more than two signals.
- An element performing a rendezvous function, or rendezvous element is an element receiving a plurality of input signals and providing at least one output signal and modifying the output signal only when the input signals satisfy a condition particular and does not alter the output signal when the input signals do not respect the particular condition.
- FIG. 8 represents an exemplary embodiment of a stage 44 of a PCHB pipeline which corresponds to a particular example of the stage 26 of FIG. 5 in which the synchronization block 34 comprises a gate C 46 which receives the Ldetect signals. and Rdetect provided by the sense blocks 30 and 32.
- the gate C 46 provides the acknowledgment signal Lack.
- the Enable signal is equal to the Lack acknowledgment signal.
- Reset reset signal may not be present.
- the validity test of the incoming data is explicitly performed by block 30.
- the output is reset earlier as soon as it is acknowledged without waiting for the input channel to become invalid.
- the acknowledgment signal Lack is repositioned for the next data once the input channel is reset.
- the communication protocol of a stage of the PCHB pipeline comprises the following successive steps:
- FIG. 9 represents an exemplary embodiment of a stage 48 of a PCFB pipeline which corresponds to a particular example of the stage 26 of FIG. 5 in which the synchronization block 34 comprises a symmetrical gate C 50 with two inputs, a door asymmetric C 52 and two inverters 54 and 56.
- the gate 50 receives the C Rdetect signal and the acquired signal ⁇ Lack of charge and provides the enable signal.
- the inverter 54 receives the Ldetect signal and the inverter 56 receives the Rdetect signal.
- the first input signals of the asymmetric gate C 52 are the signal provided by the inverter 54, the signal provided by the inverter 56 and the Enable signal.
- the second input signals of the asymmetric gate C 52 are the signal provided by the inverter 54 and the Enable signal.
- the inverse of the signal provided by the asymmetrical gate C 52 corresponds to the acknowledgment signal Lack.
- the communication protocol of one stage of the PCFB pipeline comprises the following successive steps:
- FIG. 10 represents an exemplary embodiment of a cell 60 of the functional block 28 of the stage 36 of the WCHB pipeline shown in FIG. 6.
- the cell 60 comprises a block 62 based on P-channel MOS transistors.
- the block 62 receives the Ldata signal.
- the cell 60 comprises a block 64 based on N-channel MOS transistors.
- the block 64 receives the Ldata signal.
- the blocks 62 and 64 are connected in a node E.
- the blocks 62, 64 perform combinational logic functions on the Ldata signal according to which the state of the node E can be modified.
- the cell 60 comprises a P-channel MOS transistor 66 whose source is connected to a source of a high reference voltage VDD, the drain of which is connected to the block 62 and whose gate receives the acknowledgment signal Rack.
- the cell 60 comprises an N-channel MOS transistor 68 whose source is connected to a source of a low reference voltage GND, the drain of which is connected to the block 64 and whose gate receives the acknowledgment signal Rack.
- the acknowledgment signal Rack supplied by the following stage is used to allow the blocks 62, 64 to operate via transistors 66 and 68. In this example, the acknowledgment signal Rack, Lack is active at "0". Similar circuits may be designed with an active rack acknowledgment signal at "1".
- the cell 60 comprises an inverter 70 whose input is connected to the node E and whose output provides a 1-bit signal Z.
- the cell 60 furthermore comprises a weak inverter 72 whose input receives the signal Z and whose output is connected to the node E.
- the inverter 72 is said to be weak insofar as its output can be forced when the Node E is imposed by voltage sources VDD and GND through blocks 62, 64 and transistors 66, 68.
- inverter 72 may be replaced by a block combinatorial logic and receiving the signal Z and a multi-bit signal C which depends on the signal Ldata and whose output is connected to the node E.
- the cell 60 does not receive a Reset reset signal.
- FIG. 11 represents an exemplary embodiment of a cell 74 of the functional block 28 of the stage 36 of the WCHB pipeline shown in FIG. 6 which, with respect to the cell 60, comprises, in place of the inverter 70, a NOR gate 76, one input of which is connected to the node E, the other input of which receives the reset signal Reset and whose output supplies the signal Z.
- FIG. 12 represents an exemplary embodiment of a cell 78 of the functional block 28 of the RSPCHB pipeline stage 38 shown in FIG. 7 which, with respect to the cell 60, does not include the block 62.
- the drain of the transistor 66 is directly connected to node E.
- FIG. 13 shows another exemplary embodiment of a cell 80 of the functional block 28 of the RSPCHB pipeline stage 38 shown in FIG. 7 which, with respect to the cell 78, comprises the NOR gate 76 of the cell 74 to FIG. the place of the inverter 70 of the cell 78.
- FIG. 14 represents an exemplary embodiment of a cell 82 of the functional block 28 of the PCHB pipeline stage 44 represented in FIG. 8 or the stage 48 of FIG. PCFB pipeline shown in Figure 9, which, with respect to the cell 78 further comprises a P-channel MOS transistor 84 whose source is connected to the drain of the transistor 66, whose drain is connected to the node E and whose gate receives the Enable signal.
- the cell 82 further comprises an N-channel MOS transistor 86 whose source is connected to the drain of the transistor 68, the drain of which is connected to the block 64 and whose gate receives the Enable signal.
- FIG. 15 represents another exemplary embodiment of a cell 88 of the functional block 28 of the PCHB pipeline stage 44 represented in FIG. 8 or of the PCFB pipeline stage 48 represented in FIG. 9, which, with respect to FIG. cell 82, includes the NOR gate 76 of the cell 80 in place of the inverter 70 of the cell 82.
- the cells 60, 78 and 82 do not receive the Reset reset signal while the cells 74, 80 and 88 receive the Reset reset signal.
- the Reset signal can be active high or active low.
- the reset of the internal node E by the Reset signal in the cells 74, 80 and 88 can be carried out by various means, the use of the NOR gate 76 being given by way of example.
- FIG. 16 represents an exemplary embodiment of a two-input, reset gate C 90 which corresponds to a particular example of the cell 74 shown in FIG. 11 in which the block 62 comprises a single P-channel MOS transistor 92 whose source is connected to the drain of transistor 66 and whose drain is connected to node E and in which block 64 comprises a single N-channel MOS transistor 94 whose source is connected to the drain of transistor 68 and whose drain is connected to the node E.
- the gate C 90 receives two binary signals A and B. The signal A is supplied to the gates of the transistors 92 and 94 and the signal B is supplied to the gates of the transistors 66 and 68.
- stage 17 represents an exemplary embodiment of a stage 96 corresponding to a particular example of the stage 36 of the WCHB pipeline of FIG. 6 in the case where the functional block 28 only plays the role of data storage and in the case a "1 out of 2" type coding with Lack and Rack signals that are active at the low level.
- the stage 96 receives two LO and L1 input signals and provides two R0 and R1 bit output signals.
- the downstream detection block 32 corresponds to a NOR gate 98 which receives the output signals R0 and RI and which supplies the acknowledgment signal Lack to the preceding stage.
- the functional block 28 comprises two cells each corresponding to a gate C that can be reset.
- the functional block 28 comprises a gate C 100 receiving the signal L0 and the acknowledgment signal Rack of the next stage and supplying the output signal R0.
- the functional block 28 further comprises a C gate 102 receiving the signal L1 and the acknowledgment signal Rack of the next stage and providing the output signal R1.
- the door C 100 can be made as shown in FIG. 16.
- the signals A and B of the door C 90 correspond to the signals L0 and Rack and the signal Z of the door C 90 corresponds to the signal R0.
- FIG. 18 illustrates the principle of data transmission by stage 96.
- the signals L0 and L1 are at “0” and the acknowledgment signals Lack and Rack are at "1". There are no validated data to transfer.
- the signal L0 goes to "1" (reception of bit "0" by stage 96).
- the stage 96 puts the signal R0 at "1”.
- the instants t ' Q to t' ] _5 are successive instants.
- stage 96 activates the acknowledgment signal Lack by setting the acknowledgment signal Lack to "0".
- stage 96 deactivates the acknowledgment signal Lack by setting it to "1”.
- stage 96 deactivates the acknowledgment signal Rack by setting it to "1”.
- Instants t'g to t ' ] _g are associated with the transfer of bit "1" by stage 96.
- FIG. 19 represents a particular exemplary embodiment 104 of the PCHB pipeline cell 82 represented in FIG. 14 carrying out an OR logic function between two binary signals A and B and in which the block 64 comprises two mounted N-channel MOS transistors 106 and 108 in parallel, whose sources are connected to the drain of transistor 86 and whose drains are connected to node E.
- the gate of transistor 106 receives signal B and the gate of transistor 108 receives signal A.
- FIG. 20 schematically represents an exemplary embodiment of a pipeline 110, for example of the WCHB, RSPCHB, PCHB or PCFB type. Three successive stages of the pipeline 110 are shown.
- the protocol rendezvous elements may be the cells 29 of the functional block 28 or the sets of cells 29 of the functional block 28.
- the protocol rendezvous element may also correspond to certain cells of the block As an example, for stages 38, 48 of PCFB and RSPCHB pipelines, the protocol rendezvous elements may furthermore correspond to elements 40, 50 and 52.
- the protocol rendezvous element can perform a additional function to that of appointments.
- the cell 104 shown in FIG. 19 for a PCHB pipeline performs a logical OR function while performing the synchronization function between the A, B, Rack and Enable signals.
- the protocol rendezvous element may further receive a reset signal. This is the case, for example, with cells 74, 80, 88 shown in FIGS. 11, 13 and 15.
- the protocol rendezvous element may not receive a specific reset signal, as is the case with cells 60, 78, 82 shown in Figures 10, 12 and 14.
- An optimization step conventionally implemented by the synchronous integrated circuit design assistance tools comprises determining the duration of propagation of signals between functional blocks of the integrated circuit, in particular to determine whether or not there is no incom patibility ⁇ with the frequency of the clock signal which clocks the operation of the circuit.
- the distribution of storage elements so that the paths defined between the storage elements do not understand or quasi ⁇ no loops, that is to say that there is no or almost no path for which a signal passes several times in the same place.
- Algorithms can then optimize different parameters such as the position and structure of the storage elements and combinational logic blocks between the memo elements ⁇ authorization to ensure that there is no inconsistency, to reduce the area occupied by the integrated circuit, to reduce the consumption of the integrated circuit, to increase the operating speed of the integrated circuit, etc.
- Path delineation algorithms can not be applied directly when designing asynchronous integrated circuits.
- FIG. 20 illustrates a difficulty encountered when the design assistance tools for synchronous integrated circuits are directly implemented for the design of asynchronous integrated circuits.
- An asynchronous circuit does not include storage elements whose operation is clocked by a clock signal. Therefore, if we follow the path of a signal in an asynchronous circuit, it can propagate in loops, passing several times in the same place. An example of such a path 112 is shown in dotted lines in FIG. 20.
- the path delimitation step can not then be performed as for the synchronous integrated circuits. The designer must then indicate the starting and ending points of the paths to the design assistance tool.
- One possibility is to indicate to the design assistance tools not to consider the portions of the path (hereinafter also called arcs or internal paths) traversed by the signals in certain elements of the asynchronous integrated circuit, for example the elements of rendezvous protocol, in particular the cells of the functional block 28 of each stage 26, which makes it possible to delimit paths, each path extending from the output of a protocol rendezvous element to the input of another element of protocol rendezvous.
- the loops are thus interrupted.
- the design support tool can not then do global optimization of the asynchronous integrated circuit but only local optimizations that may not be the most suitable.
- the actual operating characteristics of the non-considered protocol rendezvous elements are not taken into account by the optimization algorithms.
- the The present invention consists in using a particular model of protocol rendezvous element that is used by synchronous circuit design assistance tools.
- An internal path is a propagation path of a signal between an input terminal of the cell receiving in operation a signal and an output terminal of the cell providing in operation a signal.
- FIG. 21 schematically represents a conventional library cell 114 of a protocol rendezvous element comprising, by way of example, two input terminals A and B, a terminal Rst for receiving the Reset reset signal, a terminal Rack receiving signal Rack, ENABLE signal receiving terminal EN and Z output terminal.
- terminals EN and / or Rst may not be present.
- the cell 114 comprises two input terminals A and B. However, it is clear that the cell 114 may comprise a larger number of inputs.
- a first internal path 116 connects the input terminal A to the output terminal Z and is denoted by A-> Z.
- a second internal path connects the input terminal A to the output terminal Z and is denoted by A-> Z.
- a third internal path 120 connects the terminal Ra to the output terminal Z and is denoted Ra-> Z.
- a fourth internal path 122 connects the terminal EN to the output terminal and is denoted EN-> Z.
- a fifth internal path 124 connects the Rst terminal to the output terminal Z and is noted Rst-> Z. When the terminals Rst and / or EN are not present, the fourth internal path 122 and / or the fifth internal path 124 are not present.
- the model associated with the cell indicates values for several parameters of signal propagation under different conditions of rfr operation of the cell.
- T " ⁇ are usually defined for each internal path:
- the parameter D is equal to the delay that elapses for the signal at the output of the internal path to change from “0" to "1" when the signal at the input of the internal path goes from “0" to "1";
- the parameter D " ⁇ is equal to the time that elapses for the signal at the output of the internal path to change from" 1 "to” 0 "when the signal at the input of the internal path goes from” 1 "to” 0 ""
- the parameter T is equal to the ratio between the duration of passage of the signal at the output of the internal path from “0" to “1” and the duration of passage of the signal at the input of the internal path from “0" to “1" when the signal at the input of the internal path goes from “0" to "1” and the signal at the output of the internal path goes from “0" to "1";
- the parameter T " ⁇ is equal to the ratio between the duration of passage of the signal at the output of the internal path from" 1 “to” 0 "and the duration of passage of the signal at the input of the internal path from" 1 “to” 0 "when the signal at the input of the internal path changes from” 1 "to” 0 "and the signal at the output of the internal path changes from” 1 "to” 0 ".
- the parameters D, D, T and T are given by way of example. Other parameters can be used in addition to the parameters D, D, T and T or in place of the parameters D, f r f
- 114 comprises a matrix which contains a number P * Q of parameter values determined for a number P of duration A_ of transitions of the signal to the input terminal of the internal path and a Q number of capacitors Capj of a load connected to the output terminal of the internal path, i being an integer ranging from 1 to P and j being an integer ranging from 1 to Q.
- the element of the matrix of r is an integer ranging from 1 to P and j being an integer ranging from 1 to Q.
- the matrices can be determined by simulations or tests.
- An exemplary embodiment of the present invention comprises, for at least some of the protocol rendezvous elements of the asynchronous circuit to be synthesized, modifying the cells of the library associated with these protocol rendezvous elements by using a new parameter model of parameters. propagation of internal signals so that these elements of protocol rendezvous are considered, by the design aids, as elements clocked by a clock signal.
- FIG. 22 schematically shows a library cell 125 according to the invention which is used in place of the cell 114.
- the present invention provides for creating a terminal R and replacing the paths A-> Z, B-> Z , Ra-> Z, and EN-> Z (respectively paths 116, 118, 120 and 122 in Figure 21) by the paths A-> R, B-> R, R-> R, EN-> R, Ra -> R and R-> Z in the model of the cell 125 (respectively the paths 126, 128, 130, 132 and 134 in Figure 22).
- the terminal R may be a terminal which does not exist on the cell 114. This is the case, for example, when the cell 114 does not include an RST terminal. Alternatively, when cell 114 receives a reset signal at terminal Rst, terminal R may correspond to terminal Rst.
- Terminal R is indicated in the model of the cell as a terminal for receiving a clock signal. Paths between the protocol rendezvous elements thus defined can then be determined automatically by the design assistance tool insofar as the tool considers that the elements of protocol rendezvous are elements clocked by a signal. clock.
- D, D, T and T depend on the capacity of the load connected to the output terminal of the internal path.
- a parameter S r is defined which corresponds to the delay which elapses for a fictitious clock signal to the Internal path output changes from “0" to "1” when the signal at the input of the internal path changes from “0” to "1".
- a parameter is also defined that corresponds to the time that elapses for a fictitious clock signal at the output of the internal path to change from "1" to "0” when the signal at the input of the path goes from "1 "a” 0 ".
- the parameters S ⁇ r and S "f depend on the transition time of the signal at the input of the internal path.
- FIG. 23 represents, in the form of a block diagram, an exemplary embodiment of the method for determining the matrices of the parameters, associated with the cell 125, S,
- step 140 one of the A-> Z, B-> Z, Ra-> Z or EN-> Z paths of cell 114 is selected.
- the internal path A-> Z is selected.
- the terminal EN is present, which is particularly the case of the cells of the functional blocks 28 of the PCFB and PCHB pipelines, the internal path EN-> Z can be advantageously selected.
- a transition duration A of the signal at the input of the internal path is selected from among the P durations and a capacitance Cap j is selected from the Q capacitances. This amounts to selecting the row I and the column J in the matrices of the parameters associated with the cell 114.
- the selection of the duration A and the capacitance Cap j can be arbitrary or depend on the intended use of the element of appointment you protocol.
- the parameters are determined according to the following relations for j varying from 1 to Q:
- the terminal R corresponds to the terminal Rst, it does not take into account the parameters that are normally associated with the path Rst-> Z in the model of the cell 114.
- step 146 for each path A-> R, B-> R, R-> R and optionally EN-> R the parameters S and S are determined according to the following relations for i varying from 1 to P:
- FIG. 24 illustrates examples of paths 148, 150, 152, 154 that can be used when implementing an optimization algorithm for a synchronous integrated circuit design assistance tool to replace the path 112 of FIG. 20.
- the paths 148, 150, 152 and 154 can be automatically delimited by a synchronous integrated circuit design assistance tool which considers for each protocol rendezvous element, in this example the function block 28 of each stage 26, the internal paths A-> R, B- > R, Ra-> R and EN-> R and R-> Z as defined above and which considers that the protocol rendezvous element is clocked by a fictitious clock signal which would be received by the terminal R.
- Figure 25 shows two stages of the pipeline 110 of Figure 24. Two particular paths 150 and 156 are shown.
- the path 156 starts at the terminal R of a cell of the functional block 28 of a stage 26 and then passes successively through the terminal Z of the cell of the functional block 28 of the stage 26, by the upstream detection block 30 of the next stage 26, the synchronization block 34 of the next stage 26, the terminal EN of a cell of the functional block 28 of the next stage 26 and ends at the terminal R of the cell of the functional block 28 of the next floor 26.
- the path 150 starts at the terminal R of another cell of the functional block 28 of the stage 26 and then passes successively through the terminal Z of the cell of the functional block 28 of the stage 26, via the terminal A of a cell of the functional block 28 of the next stage 26 and ends at the terminal R of the cell of the functional block 28 of the next stage 26.
- the path 156 is present when the terminal EN is present. This is notably the case of the PCHB and PCFB pipelines described previously.
- the paths 150 and 156 form an isochronous fork. Given the operation of the pipelines, the signal passing path 150 must arrive at terminal A before the signal passing path 156 reaches the terminal EN.
- the parameters S and S for the paths A-> R and B-> R of cell 125 are determined according to the relationships previously described by adding nevertheless a strictly positive margin of safety, the determination of the other paths EN-> R and Ra-> R not being modified.
- Margin is the safety margin and is a real number greater than or equal to zero.
- the margin of safety Margin can be a constant positive constant equal for the paths A-> R and B-> R of all the cells of the functional blocks 28 of the pipeline.
- the safety margin can be a strictly positive value that depends on the cell considered. For example, the safety margin may depend on the transition time ⁇ from the low level to the high level or from the high level to the low level of the clock signal declared on the terminal R, which is not used elsewhere. in the calculation of other parameters.
- the duration ⁇ can correspond to the duration for the same type of transition (from the low level to the high level or from the high level to the low level) for all these cells.
- the reset can be carried out for certain cells when the Reset reset signal goes from the high level to the low level (first type transition) and can be performed for other cells when the Reset reset signal goes from the low level to the high level (second type of transition).
- the duration ⁇ may correspond to the duration for the same type of transition of the clock signal (which may be of the first type or the second type of transition).
- the duration ⁇ may correspond to the duration for the opposite type of transition of the clock signal.
- FIG. 26 represents, in the form of a block diagram, an exemplary embodiment of a method for designing an asynchronous integrated circuit that implements a tool for assisting the design of synchronous integrated circuits.
- the synchronous integrated circuit design assistance tool can be realized by the hardware channel, that is to say by a dedicated electronic circuit.
- the synchronous integrated circuit design assistance tool can be implemented by computer, that is to say at least partly by the execution by a computer of instructions of a computer. computer program for example stored in a memory.
- the corresponding instruction sequence can be stored in a removable storage means (such as for example a floppy disk, a CD-ROM or a DVD-ROM) or in a non-removable memory, the storage means being readable by a computer or a microprocessor.
- a removable storage means such as for example a floppy disk, a CD-ROM or a DVD-ROM
- non-removable memory the storage means being readable by a computer or a microprocessor.
- step 160 the asynchronous circuit is designed in a high definition language, then synthesized, to obtain, in a conventional manner, interconnection list files that are independent of the technology used.
- the cells 125 as defined above are selected for certain protocol rendezvous elements of the circuit to be produced.
- a dummy clock signal is provided as being received by the terminal R of the selected protocol rendezvous elements.
- the selection of protocol appointment items depends on the pipeline structure.
- the protocol rendezvous elements may comprise the cells 29 of the functional block 28 of each stage of the pipeline.
- the terminal R as defined above may correspond to the terminal Rst of the protocol rendezvous element.
- the terminal R is then a dummy terminal which has no physical existence.
- the period of the dummy clock signal is set according to the intended performance of the asynchronous circuit. For example, it can be set at a quarter of the target cycle time for the asynchronous circuit. Alternatively, the period of the clock signal can be set to 0 seconds.
- the transition time ⁇ of the clock signal can be set to a value corresponding to the safety margin for the isochronous fork between the paths 150 and 156. Alternatively, the transition time of the clock signal can take a any value, when it is not desired to control a safety margin.
- step 164 (Technology Mapping) a method of technological matching is performed using the cells of the library, including the cells of one invention.
- step 166 Placement
- steps 168 and 170 a placement and routing method is implemented.
- Interconnection list files can be significantly modified.
- the design support tools distribute the protocol rendezvous elements and scale them as needed to minimize the time paths of data progression and acknowledgments.
- the combinational logic portions can be optimized until the propagation times satisfy the pseudo-synchronous constraints.
- step 168 a method of designing a dummy clock tree is implemented.
- the synthesized clock tree corresponds to the transmission network of the Reset reset signal of the protocol rendezvous elements.
- the Reset signal was considered a dummy clock signal and until this step, an ideal clock tree without propagation delay was considered.
- the resetting signal transmission network Reset is determined by creating a clock tree with low constraints on the propagation time of the clock signal from the clock generation circuit to the protocol rendezvous elements. and as to the offset of the arrival of the clock signal between different elements of protocol appointments.
- no clock tree is to be synthesized. For this purpose, it suffices to indicate that the clock signal is produced directly at the terminal R of each protocol rendezvous element.
- step 170 the method can continue optimizing the circuit.
- the optimization algorithms implemented after the step of designing the clock tree continue to advantageously consider that the reset signal is an ideal clock signal without offset.
- step 172 (Validation) all the verification steps are performed with the true asynchronous models (associated with the cells 114) for the protocol rendezvous elements.
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FR1254127A FR2990283A1 (fr) | 2012-05-04 | 2012-05-04 | Bibliotheque de cellules et procede de conception d'un circuit integre asynchrone |
PCT/FR2013/050875 WO2013164528A2 (fr) | 2012-05-04 | 2013-04-22 | Bibliothèque de cellules et procédé de conception d'un circuit intégré asynchrone |
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Country | Link |
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US (1) | US9430600B2 (fr) |
EP (1) | EP2845131A2 (fr) |
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US9520180B1 (en) | 2014-03-11 | 2016-12-13 | Hypres, Inc. | System and method for cryogenic hybrid technology computing and memory |
US9576094B2 (en) * | 2014-08-20 | 2017-02-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Logic circuit and system and computer program product for logic synthesis |
US10073939B2 (en) | 2015-11-04 | 2018-09-11 | Chronos Tech Llc | System and method for application specific integrated circuit design |
US9977853B2 (en) | 2015-11-04 | 2018-05-22 | Chronos Tech Llc | Application specific integrated circuit link |
US11550982B2 (en) * | 2015-11-04 | 2023-01-10 | Chronos Tech Llc | Application specific integrated circuit interconnect |
US10181939B2 (en) | 2016-07-08 | 2019-01-15 | Chronos Tech Llc | Systems and methods for the design and implementation of an input and output ports for circuit design |
US10797706B2 (en) * | 2016-12-27 | 2020-10-06 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device |
US10637592B2 (en) | 2017-08-04 | 2020-04-28 | Chronos Tech Llc | System and methods for measuring performance of an application specific integrated circuit interconnect |
US11087057B1 (en) | 2019-03-22 | 2021-08-10 | Chronos Tech Llc | System and method for application specific integrated circuit design related application information including a double nature arc abstraction |
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US6130475A (en) * | 1993-12-07 | 2000-10-10 | International Business Machines Corporation | Clock distribution system for synchronous circuit assemblies |
US6166963A (en) * | 1998-09-17 | 2000-12-26 | National Semiconductor Corporation | Dual port memory with synchronized read and write pointers |
WO2001001245A1 (fr) * | 1999-06-26 | 2001-01-04 | Yang Sei Yang | Procede et dispositif de sondage d'entree-sortie et procede mixte d'emulation-simulation base sur ces derniers |
US6597664B1 (en) * | 1999-08-19 | 2003-07-22 | Massachusetts Institute Of Technology | Digital circuit synthesis system |
DE60033531D1 (de) * | 1999-08-19 | 2007-04-05 | Massachusetts Inst Technology | Synthese einer synchronen schaltung unter verwendung einer asynchronen spezifikation |
FR2815197B1 (fr) * | 2000-10-06 | 2003-01-03 | St Microelectronics Sa | Circuit asynchrone pour la detection et la correction de l'erreur induite et procede de mise en oeuvre |
US7418676B2 (en) * | 2005-01-19 | 2008-08-26 | Seiko Epson Corporation | Asynchronous circuit design tool and computer program product |
US7647567B1 (en) * | 2005-01-31 | 2010-01-12 | Bluespec, Inc. | System and method for scheduling TRS rules |
US7610567B2 (en) * | 2006-04-27 | 2009-10-27 | Achronix Semiconductor Corporation | Systems and methods for performing automated conversion of representations of synchronous circuit designs to and from representations of asynchronous circuit designs |
FR2901437B1 (fr) * | 2006-05-16 | 2008-08-08 | Arteris Sa | Procede de realisation d'un circuit de synchronisation de donnees echangees de maniere asynchrone entre deux blocs synchrones, et circuit de synchronisation elabore a partir d'un tel procede |
US8065647B2 (en) * | 2007-10-19 | 2011-11-22 | The University Of Utah Research Foundation | Method and system for asynchronous chip design |
US8086975B2 (en) * | 2008-04-10 | 2011-12-27 | University Of Southern California | Power aware asynchronous circuits |
US8448105B2 (en) * | 2008-04-24 | 2013-05-21 | University Of Southern California | Clustering and fanout optimizations of asynchronous circuits |
JP5409231B2 (ja) * | 2008-09-26 | 2014-02-05 | 株式会社半導体エネルギー研究所 | 設計システム |
US8161435B2 (en) * | 2009-07-20 | 2012-04-17 | Achronix Semiconductor Corporation | Reset mechanism conversion |
US8301933B2 (en) * | 2009-09-14 | 2012-10-30 | Achronix Semiconductor Corporation | Multi-clock asynchronous logic circuits |
US8661378B2 (en) * | 2009-09-30 | 2014-02-25 | Achronix Semiconductor Corporation | Asychronous system analysis |
-
2012
- 2012-05-04 FR FR1254127A patent/FR2990283A1/fr not_active Withdrawn
-
2013
- 2013-04-22 US US14/395,344 patent/US9430600B2/en active Active
- 2013-04-22 EP EP13723839.0A patent/EP2845131A2/fr active Pending
- 2013-04-22 WO PCT/FR2013/050875 patent/WO2013164528A2/fr active Application Filing
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WO2013164528A2 (fr) | 2013-11-07 |
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