EP2826150B1 - Appareil turbocodeur - Google Patents

Appareil turbocodeur Download PDF

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Publication number
EP2826150B1
EP2826150B1 EP12865919.0A EP12865919A EP2826150B1 EP 2826150 B1 EP2826150 B1 EP 2826150B1 EP 12865919 A EP12865919 A EP 12865919A EP 2826150 B1 EP2826150 B1 EP 2826150B1
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Prior art keywords
bits
bitstream
encoder
input
output
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German (de)
English (en)
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EP2826150A1 (fr
EP2826150A4 (fr
EP2826150B8 (fr
Inventor
Jinsoup Joung
Joohyeong Lee
Jongho LIM
Seungkeun YOOK
Ji Hye Shin
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Innowireless Co Ltd
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Innowireless Co Ltd
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Publication of EP2826150B1 publication Critical patent/EP2826150B1/fr
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/47—Error detection, forward error correction or error protection, not provided for in groups H03M13/01 - H03M13/37
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/03—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words
    • H03M13/23—Error detection or forward error correction by redundancy in data representation, i.e. code words containing more digits than the source words using convolutional codes, e.g. unit memory codes
    • H03M13/235—Encoding of convolutional codes, e.g. methods or arrangements for parallel or block-wise encoding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2903—Methods and arrangements specifically for encoding, e.g. parallel encoding of a plurality of constituent codes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2957—Turbo codes and decoding
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/29—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes combining two or more codes or code structures, e.g. product codes, generalised product codes, concatenated codes, inner and outer codes
    • H03M13/2957—Turbo codes and decoding
    • H03M13/2993—Implementing the return to a predetermined state, i.e. trellis termination
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6522—Intended application, e.g. transmission or communication standard
    • H03M13/6525—3GPP LTE including E-UTRA
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
    • H03M13/65—Purpose and implementation aspects
    • H03M13/6575—Implementations based on combinatorial logic, e.g. Boolean circuits

Definitions

  • the present invention relates to a turbo encoder apparatus, and more particularly to a turbo encoder apparatus using an improved signal processing method in order to enhance a speed of a turbo encoder used in a channel coding technology.
  • a channel coding such as a turbo coding is used to increase the transmission efficiency of data in a communication system.
  • FIG. 1 is a block diagram illustrating a construction of a conventional turbo encoder.
  • the conventional turbo encoder 100 includes an internal interleaver 110 and two 8-state element encoders 120 and 130.
  • the conventional turbo encoder 100 performs a channel coding by using a Parallel Concatenated Convolutional Code (PCCC) .
  • PCCC Parallel Concatenated Convolutional Code
  • a transfer function of the 8-state element encoders 120 and 130 is defined as follows.
  • An input bitstream of the conventional turbo encoder 100 is represented as C 0 , C 1 , C 2 , C 3 ,.... C k -1 and output bitstreams of first and second 8-state element encoders 120 and 130 are represented as z 0 , z 1 , z 2 , z 3 ,... z k -1 and z ' 0 , z ' 1 , z ' 2 , z ' 3 ,... z ' k -1 , respectively.
  • Outputs of the internal interleaver 110 of the turbo encoder are represented as C ' 0 , C ' 1 , C ' 2 ,... C ' k -1 , and C ' 0 , C ' 1 , C ' 2 ,... C' k-1 become inputs of the second 8-state element encoder 130.
  • a trellis termination is performed by taking three shift register values indicating the state after all input bitstreams have been encoded as a final input bit. The final input bit is added to the back of the output bitstream after the input bitstreams have been fully encoded.
  • First three final bits should be used when the first 8-state element encoder 120 is terminated in a state where an operation of the second 8-state element encoder 130 is stopped. That is, a switch included in the first 8-state element encoder 120 is connected to a lower side.
  • Last three final bits should be used when the second 8-state element encoder 130 is terminated in a state where an operation of the first 8-state element encoder 120 is stopped. That is, a switch included in the second 8-state element encoder 130 is connected to a lower side.
  • Trellis termination bitstreams added to outputs are as follows.
  • the number of sizes (K) of input bitstreams, which can be encoded at one time, is a total of 188, and K can have values shown in the below table.
  • a maximum size (K) of the code block is 6144 bits.
  • the time spent for generating an output bitstream by encoding an input bitstream corresponds to a 6144+3+3 clock cycle in the implementation of hardware.
  • the time is calculated based on a basic sampling frequency (30.72 MHz) in LTE or LTE-Advanced, the time of about 200.2 us is required and the time corresponds to one subframe of about 20%.
  • three code blocks which are outputs of the conventional turbo encoder 100, should be converted to a structure body in the unit of 32 bits before entering a rate matching, which is a next signal processing step, and insufficient bits are filled with null bit.
  • the conventional turbo encoder 100 takes a long time for encoding since the conventional turbo encoder 100 performs the encoding in the unit of bits.
  • Document US 6 651 209 B1 discloses a parallel turbo encoder implementation.
  • Document US 2003/101401 A1 discloses an encoder for coding multiple data bits in parallel. Further, it is referred to M'Sir A et al: "A high speed encoder for recursive systematic convolutive codes", proceedings of the eighth IEEE international online testing workshop, 8 July 2002, pages 51 to 55 .
  • An aspect of the present invention provides a turbo encoder apparatus, which is implemented to perform an encoding in the unit of plural bits and reconstructs forms of an input bitstream and an output bitstream satisfying a code block size and a trellis termination method are satisfied.
  • the present invention has an effect of reducing the time spent for performing the encoding by enabling the encoding to be performed in the unit of plural bits every clock cycle.
  • the present invention has an effect of performing a turbo encoding with a structure optimized for a total signal processing processor through the assembly of input forms of encoding output bitstreams in a subsequent signal processing step for encoding through the bitstream assembling apparatus.
  • the present invention has an effect of generating bits for the trellis termination in one clock cycle.
  • FIG. 2 is a block diagram illustrating a construction of a turbo encoder according to an embodiment of the present invention.
  • the turbo encoder 200 according to the embodiment of the present invention includes a first element encoder 210, an internal interleaver 220, a second element encoder 230, a trellis termination encoder 240, and a bitstream assembling apparatus 250, and receives an input of data to generate and output an encoded bitstream for the input data.
  • the first element encoder 210 has a size of a designated code block.
  • the first element encoder 210 receives an input of a bitstream of input data in which the padding is performed, in the unit of plural bits to perform an encoding and generates a first output bitstream in the unit of plural bits.
  • the first output bitstream becomes a bitstream X (0,..., n) and a bitstream Z (0, ..., n).
  • the first element encoder 210 includes an internal register and a state of an initial register is "000".
  • the first element encoder 210 receives the bitstream of the input data in the unit of plural bits.
  • the input data is input to the first element encoder 210 in the unit of plural bits after the input data is divided in the unit of plural bits through a means for generating the bitstream of the input data in the unit of plural bits before the input data is input to the first element encoder 210.
  • FIG. 3 is a block diagram illustrating a structure of an input bitstream according to an embodiment of the present invention.
  • the first element encoder 210 receives an input of an input bitstream having the same number of filler bits existing in the front of the input data as the number of F, which has no remainder when C is divided by 8. At this time, the filler bit may be "0".
  • the size of the data bitstream input to the first element encoder 210 corresponds to a sum of the size (c) of the data input to the turbo encoder 200 and the number (F) of filler bits existing in the front of the data, and also corresponds to a value generated by multiplying the number (M 8 ) of input bitstreams and 8. Further, the size of the data bitstream is a maximum of 6144 and can have only a value of Ki defined in Table 1.
  • the first element encoder 210 generates the first output bitstream by using the bitstream of input data and an internal state.
  • the internal state of the first element encoder 210 refers to a state of the internal register included in the first element encoder 210.
  • the first element encoder 210 operates the state of the internal register while encoding the bitstream of the input data.
  • the first element encoder 210 generates first output bitstreams Z(n), Z(n+1), Z(n+2), Z(n+3), Z(n+4), Z(n+5), Z(n+6), Z(n+7) or X(n), X(n+1), X(n+2), X(n+3), X(n+4), X(n+5), X(n+6), X(n+7) when the bitstreams of the input data correspond to C(n), C(n+1), C(n+2), C(n+3), C(n+4), C(n+5), C(n+6), C(n+7) and the internal states of the first element encoder 210 correspond to D0 (n), D 1 (n), D 2 (n).
  • the first element encoder 210 uses an encoding method shown in FIG. 1 .
  • the first element encoder 210 derives D 0 (n+8), D 1 (n+8), D 2 (n+8), which are internal states in the case of n+8 according to the below equation.
  • FIG. 6 is a block diagram illustrating a construction of an element encoder circuit according to an embodiment of the present invention.
  • the element encoder circuit illustrated in FIG. 6 shows an example of deriving output bitstreams Z(n), Z(n+1), Z(n+2), Z(n+3), Z(n+4), Z(n+5), Z(n+6), Z(n+7) and subsequent internal states D 0 (n+8), D 1 (n+8), D 2 (n+8) by using the aforementioned inputs C(n), C(n+1), C(n+2), C(n+3), C(n+4), C(n+5), C(n+6), C(n+7) and internal states D 0 (n), D 1 (n), D 2 (n) .
  • the first element encoder 210 receives an input of input bitstreams having the form shown in FIG. 3 and generates output bitstreams including the same number of null bits as the number of filler bits existing in the input bitstreams.
  • the first element encoder 210 represents the null bit as "0". There are several methods to represent the null bit, but the null bit is represented herein as "0" in order to facilitate a next step of the signal processing of the turbo encoder. Thereafter, the null bit and the "0" bit are discriminated through the number of "0" which is inserted into the input bitstream. Referring back to FIG.
  • the internal interleaver 220 receives data input to the turbo encoder 200 and generates an interleaved input bitstream. It is preferable that the internal interleaver 220 is configured to generate the interleaved input bitstream in the unit of plural bits.
  • the second element encoder 230 receives an input of the interleaved input bitstream generated through the internal interleaver 220 in the unit of plural bits to encode the interleaved input bitstream and generates a second output bitstream in the unit of plural bits.
  • the second element encoder 230 has the same construction as that of the first element encoder 210 but the input data bitstream and the output bitstream transmitted to the bitstream assembling apparatus 250 are only different.
  • the difference of the output bitstream of the second element encoder 230 from the first element encoder 210 means that the output bitstreams transmitted to the bitstream assembling apparatus 250 by the first element encoder 210 are both of operated X(n) and Z(n) but the output bitstream transmitted to the bitstream assembling apparatus 250 by the second element encoder 230 is only X' (n) between operated X' (n) and Z' (n) .
  • the trellis termination encoder 240 generates a bit for the trellis termination of the first element encoder 210 and the second element encoder 230.
  • the trellis termination encoder 240 generates the bit for the trellis termination by using an internal state of the first encoder 210 or the second element encoder 230 when the last input bitstream for the input data is input to the first element encoder 210 or the second element encoder 230.
  • the trellis termination encoder 240 When the internal states of the first element encoder 210 or the second element encoder 230 in a state where the last input bitstream for the input data is input to the first element encoder 210 or the second element encoder 230 are D 0 (n), D 1 (n), D 2 (n), the trellis termination encoder 240 generates Z(n), Z(n+1), Z(n+2), X(n), X(n+1), X(n+2) according to the below equation.
  • bits for the trellis termination are 12 bits and the trellis termination encoder 240 can generate bits for the trellis termination during one clock cycle.
  • the bitstream assembling apparatus 250 receives the first output bitstream from the first element encoder 210, receives the second output bitstream from the second element encoder 230, and receives the bits for the trellis termination from the trellis termination encoder 240 to generate the input bitstream used in the rate matching.
  • the input bitstreams, which are used in the rate matching, generated by the bitstream assembling apparatus 250 are three bitstreams in the unit of bytes.
  • FIG. 4 is a block diagram illustrating a structure of a bitstream input to a bitstream assembling apparatus according to an embodiment of the present invention.
  • the bitstream assembling apparatus 250 receives an input of the first output bitstreams X(n) and Z(n) from the first element encoder, receives an input of the second output bitstream X'(n) from the second element encoder 230, and receives an input of the bits for the trellis termination from the trellis termination encoder 240.
  • the bitstream assembling apparatus 250 adds four bits for the trellis termination to each of the first output bitstreams and the second output bitstream, respectively as shown in FIG. 4 .
  • FIG. 5 is a block diagram illustrating a structure of an output bitstream of a bitstream assembling apparatus according to an embodiment of the present invention.
  • the bitstream assembling apparatus 250 connects the bits for the trellis termination to X(0, ..., k-1) and Z(0, ..., k-1) received from the first output bitstreams and X'(0, ..., k-1) received from the second output bitstream and generates a final output structure.
  • the bitstream assembling apparatus 250 divides 12 bit information generated by the trellis termination encoder 240 into three 4 bit information pieces. Further, the bitstream assembling apparatus 250 connects each of the divided 4 bits to the three final output bitstreams and adds null bits to the fronts of the output bitstreams such that the output bitstreams become structure bodies having the unit of 4 bytes.
  • the bitstream assembling apparatus 250 receives the first output bitstreams, the second output bitstream, and the bits for the trellis termination to make them become structure bodies having the unit of 32 bits and can be constructed such that they become structure bodies having the unit of 8 bits for an 8 bit unit processing.
  • FIG. 8 is a block diagram illustrating a construction of a bitstream assembling apparatus according to an embodiment of the present invention.
  • the bitstream assembling apparatus 250 delays lower 4 bits in the 8 bit unit by one cycle in order to construct 4 bits, which are the bits for the trellis termination, in the 8 bit unit by using the register.
  • bitstream assembling apparatus 250 detects third and fourth bits when added null bits according to a value of K are represented by a binary number and uses the detected bits as multiplexer control bits, and thus null bits, which are 4, 12, 20, or 28 bits, are inserted.
  • the number of null bits is 32-(K+4) mod 32.
  • bitstream assembling apparatus 250 can use a delay register in the unit of 8 bits including a D-flip flop (D-type flip flop).

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  • Physics & Mathematics (AREA)
  • Probability & Statistics with Applications (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Error Detection And Correction (AREA)

Claims (4)

  1. Appareil turbo-codeur (200) pour recevoir un train binaire d'entrée de données d'entrée pour générer et sortir des trains binaires codés, l'appareil turbo-codeur (200) comprenant :
    un premier codeur élémentaire (210) pour recevoir le train binaire d'entrée de données d'entrée qui a une taille K d'un bloc de code désigné et dans lequel un rembourrage a été mis en œuvre, pour coder le train binaire d'entrée de données d'entrée, et générer deux premiers trains binaires de sortie, dans lequel ladite réception, ledit codage et ladite génération par le premier codeur élémentaire (210) sont effectués dans une unité de 8 bits par cycle d'horloge, respectivement ;
    un entrelaceur interne (220) pour générer un train binaire d'entrée entrelacé à partir du train binaire d'entrée des données d'entrée ;
    un second codeur élémentaire (230) pour recevoir le train binaire d'entrée entrelacé, coder le train binaire d'entrée entrelacé, et générer un second train binaire de sortie, dans lequel ladite réception, ledit codage et ladite génération par le second codeur élémentaire (230) sont réalisés dans une unité de 8 bits par cycle d'horloge, respectivement ; et
    un codeur de terminaison en treillis (240) pour générer des bits pour les terminaisons de treillis du premier codeur élémentaire (210) et du second codeur élémentaire (230),
    caractérisé en ce que l'appareil turbo-codeur comprend en outre
    un assembleur de train binaire (250) pour recevoir les premiers trains binaires de sortie, les seconds trains binaires de sortie, et 12 bits pour les terminaisons de treillis, diviser les 12 bits pour les terminaisons de treillis en trois parties de 4 bits, connecter les trois parties de 4 bits aux premiers et seconds trains binaires de sortie, respectivement, et insérer des bits nuls dans une partie avant de chacun des premiers et seconds trains binaires de sortie de sorte que chacun des premiers et seconds trains binaires de sortie ait l'unité de 4 octets, dans lequel
    l'assembleur de train binaire (250) est configuré pour ajouter et insérer lesdits bits nuls en changeant les positions des 4 bits supérieurs et des 4 bits inférieurs dans une unité de 8 bits des premiers trains binaires de sortie et du second train binaire de sortie, en retardant les 4 bits inférieurs d'un cycle en utilisant un registre à 4 bits, et en faisant passer les 4 bits inférieurs à travers un circuit de retard de cycle selon le nombre de bits nuls à ajouter, ajoutant et insérant ainsi 32-(K+4) mod 32 bits nuls avant les 4 bits supérieurs.
  2. Appareil turbo-codeur selon la revendication 1, dans lequel le premier codeur élémentaire (210) génère les premiers trains binaires de sortie en utilisant le train binaire d'entrée des données d'entrée et un état interne du premier codeur élémentaire (210), et le second codeur élémentaire (230) génère le second train binaire de sortie en utilisant le train binaire d'entrée entrelacé et un état interne du second codeur élémentaire (230).
  3. Appareil turbo-codeur (200) selon la revendication 2, dans lequel le premier codeur élémentaire (210) ou le second codeur élémentaire (230) utilise « 0 » pour représenter chacun des bits nuls, dans lequel le nombre de bits nuls existant dans les premiers trains binaires de sortie ou le second train binaire de sortie est égal au nombre de bits de remplissage existant dans le train binaire d'entrée.
  4. Appareil turbo-codeur (200) selon la revendication 1, dans lequel le codeur de terminaison en treillis génère les bits pour la terminaison de treillis en utilisant un état interne du premier codeur élémentaire (210) ou du second codeur élémentaire (230), respectivement, lorsque la dernière unité de 8 bits de données d'entrée est entrée dans le premier codeur élémentaire (210) ou le second codeur élémentaire (230), respectivement.
EP12865919.0A 2012-01-20 2012-02-24 Appareil turbocodeur Active EP2826150B8 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020120006617A KR101286019B1 (ko) 2012-01-20 2012-01-20 터보 인코더 장치
PCT/KR2012/001439 WO2013108952A1 (fr) 2012-01-20 2012-02-24 Appareil turbocodeur

Publications (4)

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EP2826150A1 EP2826150A1 (fr) 2015-01-21
EP2826150A4 EP2826150A4 (fr) 2015-11-18
EP2826150B1 true EP2826150B1 (fr) 2021-06-30
EP2826150B8 EP2826150B8 (fr) 2021-08-04

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US (1) US9000959B2 (fr)
EP (1) EP2826150B8 (fr)
KR (1) KR101286019B1 (fr)
WO (1) WO2013108952A1 (fr)

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KR101526990B1 (ko) * 2008-01-31 2015-06-11 엘지전자 주식회사 전송 블록 크기 결정 방법 및 이를 이용한 신호 전송 방법
WO2009096658A1 (fr) 2008-01-31 2009-08-06 Lg Electronics Inc. Procédé de détermination de taille de bloc de transport et procédé de transmission de signaux utilisant ledit procédé

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US6772391B1 (en) * 1998-10-13 2004-08-03 Interdigital Technology Corporation Hybrid interleaver for turbo codes
EP1085660A1 (fr) * 1999-09-15 2001-03-21 TELEFONAKTIEBOLAGET L M ERICSSON (publ) Mise en oeuvre d'un dispositif de codage turbo
KR100369561B1 (ko) 2000-11-08 2003-01-29 학교법인 한국정보통신학원 터보 코드용 인코더 및 디코더
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CN102804609B (zh) * 2009-06-17 2015-04-01 相干逻辑公司 基于格式结构方法的并行执行

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Publication number Publication date
EP2826150A1 (fr) 2015-01-21
WO2013108952A1 (fr) 2013-07-25
KR101286019B1 (ko) 2013-07-19
EP2826150A4 (fr) 2015-11-18
US9000959B2 (en) 2015-04-07
US20140375485A1 (en) 2014-12-25
EP2826150B8 (fr) 2021-08-04

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