EP2814300B1 - Ansteuerung für eine Lichtquelle - Google Patents

Ansteuerung für eine Lichtquelle Download PDF

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Publication number
EP2814300B1
EP2814300B1 EP13171212.7A EP13171212A EP2814300B1 EP 2814300 B1 EP2814300 B1 EP 2814300B1 EP 13171212 A EP13171212 A EP 13171212A EP 2814300 B1 EP2814300 B1 EP 2814300B1
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EP
European Patent Office
Prior art keywords
control signals
control
driver
cycle
driving
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EP13171212.7A
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English (en)
French (fr)
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EP2814300A1 (de
Inventor
Henri Juslén
Kimmo Lamminpää
Aku Moilanen
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Helvar Oy AB
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Helvar Oy AB
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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/40—Details of LED load circuits
    • H05B45/44—Details of LED load circuits with an active control inside an LED matrix
    • H05B45/48—Details of LED load circuits with an active control inside an LED matrix having LEDs organised in strings and incorporating parallel shunting devices
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/10—Controlling the intensity of the light
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05B—ELECTRIC HEATING; ELECTRIC LIGHT SOURCES NOT OTHERWISE PROVIDED FOR; CIRCUIT ARRANGEMENTS FOR ELECTRIC LIGHT SOURCES, IN GENERAL
    • H05B45/00—Circuit arrangements for operating light-emitting diodes [LED]
    • H05B45/30—Driver circuits
    • H05B45/37—Converter circuits
    • H05B45/3725—Switched mode power supply [SMPS]
    • H05B45/375—Switched mode power supply [SMPS] using buck topology

Definitions

  • the invention relates to control of operation of one or more light sources.
  • embodiments of the invention relate to an arrangement comprising a single array of light emitting diodes and a driver apparatus for driving the single array of light emitting diodes, and to a use of a driver apparatus and a sum of two or more separate output currents provided by the driver apparatus.
  • a driver for a light emitting diode (LED) light source may apply a control signal, such as a pulse-width modulation (PWM) signal, for controlling the light intensity provided by the LED light source.
  • PWM pulse-width modulation
  • a periodic PWM signal with desired duty cycle and cycle frequency (PWM frequency) is typically applied in the driver to cause the driver to operate the LED light source at a light intensity determined by the duty cycle.
  • PWM frequency pulse-width modulation
  • too low PWM frequency is likely to result in perceivable flickering of light due to too long off periods between the on periods, which may even be perceived as a disturbing stroboscopic effect.
  • too high PWM frequency is likely to result in inaccurate control of light intensity or even variations in light level due to switching operation of power converters typically applied in such drivers.
  • US 2012/098869 A1 discloses a light emitting diode driving circuit that includes a DC-to-DC voltage converter, a pulse width modulator, a shifting circuit, and a plurality of current sink circuits.
  • the DC-to-DC voltage converter generates a driving voltage on first ends of the light emitting diode channels, in which the DC-to-DC voltage converter includes a switch, and a magnitude of the driving voltage is correlated with the conduction time of the switch.
  • the pulse width modulator generates a PWM signal having a duty cycle which drives the switch of the DC-to-DC voltage converter.
  • the plurality of clock cycles on the shifting circuit delays the PWM signal to generate a plurality of phase signals, in which the phase signals have different phases.
  • the current sink circuits are positioned to control the flows of current flowing through the light emitting diode channels according to the phase signals having different phases.
  • US 2010/301764 A1 discloses an LED controller with phase-shift dimming function and an LED Phase-Shift dimming circuit and method thereof.
  • the LED controller includes: a power circuit for supplying DC power to multiple LED channels; and an LED phase-shift dimming circuit for receiving a pulse width modulation (PWM) input signal and generating multiple phase-shifted PWM signals with a shifted phase between one another, wherein a turn-ON timing of each of the multiple phase-shifted PWM signals follows a turn-OFF timing of a previous PWM signal which is the input PWM signal or a previous one of the multiple phase-shifted PWM signals.
  • PWM pulse width modulation
  • WO 2008/034242 A1 discloses a system in which a number of LEDs are coupled between a power source and ground, each LED having a corresponding bypass switch for selectively bypassing one or more of the LEDs. Control signals to the bypass switches are issued in phased manner.
  • US 2010/220049 A1 discloses a load driving device that includes a power supply circuit for supplying to a load an output voltage converted from an input voltage, a detection voltage generation circuit for generating a detection voltage which varies depending on a magnitude of a voltage drop which across the load, and a control circuit for controlling the power supply circuit so that it performs output feedback control of the output voltage, on the basis of the detection voltage.
  • US 2009/225020 A1 discloses a backlight controller for driving a plurality of light source strings that includes a feedback circuitry, a phase array circuitry, and an encoder circuitry.
  • the feedback circuitry is coupled to the plurality of light source strings and generates a plurality of feedback signals indicative of a plurality of currents flowing through the plurality of light source strings respectively.
  • the phase array circuitry receives a dimming control signal and receives a code signal indicative of a total number of operative light source strings among the plurality of light source strings, and generates a plurality of phase shift signals according to the code signal and the dimming control signal.
  • the encoder circuitry is coupled to the phase array circuitry and receives the plurality of phase shift signals and the plurality of feedback signals, and generates a plurality of pulse width modulation signals to respectively control the operative light source strings.
  • US 2010/090530 A1 discloses a load driving circuit for carrying out PWM control to cause currents of respective light emitting diode lines connected in parallel, each of the light emitting diode lines including a plurality of light emitting diodes connected in series, causes timing at which a current of any one of the light emitting diode lines is turned on or off to be different from timing at which current(s) of at least another one of the light emitting diode lines is(are) turned on or off.
  • WO 02/056643 A1 discloses a sequential burst mode regulation system to deliver power to a plurality of loads.
  • the regulation system generates a plurality of phased pulse width modulated signals from a single pulse width modulated signal, where each of the phased signals regulates power to a respective load.
  • Exemplary circuitry includes a PWM signal generator, and a phase delay array that receives a PWM signal and generates a plurality of phases PWM signals which are used to regulate power to respective loads.
  • a frequency selector circuit can be provided that sets the frequency of the PWM signal using a fixed or variable frequency reference signal. Consequently, it is an object of the present invention to provide a technique that enables driving the LED light source(s) at sufficient PWM cycle frequencies while avoiding disturbances caused by the power converter switching frequency.
  • an arrangement comprising a single array of light emitting diodes and a driver apparatus for driving the single array of light emitting diodes that comprises a single light emitting diode or two or more light emitting diodes connected in series
  • the driver apparatus comprising: one or more power source portions for providing two or more driving currents as the respective two or more separate output currents of the driver apparatus; and a control portion for issuing two or more control signals for controlling the provision of the two or more respective driving currents, each control signal exhibiting a respective duty cycle at a first cycle frequency
  • the control portion is configured to issue the two or more control signals as synchronized control signals in predetermined time offsets with respect to each other for provision of the two or more driving currents in different phases, and wherein the control portion is configured to: receive a single command or request
  • a driver apparatus and a sum of two or more separate output currents provided by the driver apparatus to drive a single array of light emitting diodes that comprises a single light emitting diode or two or more light emitting diodes connected in series wherein the driver apparatus comprises: one or more power source portions for providing two or more driving currents as the respective two or more separate output currents of the driver apparatus; and a control portion for issuing two or more control signals for controlling the provision of the two or more driving currents, each control signal exhibiting a respective duty cycle at a first cycle frequency, wherein the control portion is configured to issue the two or more control signals as synchronized control signals in predetermined time offsets with respect to each other for provision of the two or more respective driving currents in different phases, and wherein the control portion is configured to: receive a single command or request indicative of a requested light intensity level to be provided by the sum of the two or more driving currents, derive a duty cycle corresponding to the requested light intensity level by using a
  • FIG. 1a schematically illustrates an exemplifying arrangement 100 for providing light at a selectable light level.
  • the arrangement 100 comprises a controller entity 110 for issuing input control signals 115-1, 115-2, ..., 115-n indicating desired characteristics of output currents 125-1, 125-2, ..., 125-n to a driver 120.
  • the driver 120 is arranged to derive each output current 125-1, 125-2, ..., 125-n on basis of operating power provided 117 thereto in accordance with the characteristics of the respective input control signal 115-1, 115-2, ..., 115-n.
  • the output currents 125-1, 125-2, ..., 125-n are provided to a single array of light emitting diodes (LEDs) 170'.
  • An array of LEDs in other words a LED array, comprises either a single LED light source or two or more light sources connected in series. Hence, the driver 120 may be used to drive the single LED array 170'.
  • the input control signals 115-1, 115-2, ..., 115-n may be referred to as input control signals 115 when referring jointly to all input control signals 115-1, 115-2, ..., 115-n or when referring to any single one of the input control signals 115-1, 115-2, ..., 115-n.
  • the reference number 115-i may be applied to refer to the i:th input control signal. Similar practice may be applied to any numbered element comprising multiple sub-elements, i.e. to reference number having the format xxx-i.
  • FIG. 1b schematically illustrates a second exemplifying arrangement 100' as a variation of the first arrangement 100.
  • each of the output currents 125-1, 125-2, ..., 125-n is coupled to one of separate LED arrays 170-1, 170-2, ..., 170-n, while the other components of the arrangement 100' are similar to those of the arrangement 100.
  • the separate LED arrays 170-1, 170-2, ..., 170-n are, preferably, arranged into a single luminaire or light fixture.
  • the LED arrays 170, 170' may be identical or they may have different light emission spectra.
  • the LEDs within a LED array 170-i, 170' may be identical or they may have different light emission spectra.
  • a dedicated input control signal 115-i is provided for each output current 125-i, i.e. the number of input control signals 115 is the same as the number of output currents 125. However, the number of input control signals 115 may be smaller than the number of output currents 125 e.g. such that each of the input control signals 115 is arranged to indicate desired characteristics for two or more output currents.
  • the number n indicating the number of input control signals and output currents in the arrangements 100 and 100' and the number of LED arrays for the arrangement 100' may be any number greater than or equal to two.
  • the driver 120 is configured to receive two or more input control signals 115 and to provide respective two or more output currents 125.
  • the two or more output currents 125 are coupled to respective two or more LED arrays 170.
  • the driver 120 may be used to drive the two or more LED arrays 170.
  • FIG. 9 Further exemplifying arrangements are schematically illustrated in Figures 9 and 10 .
  • An arrangement 400 depicted in Figure 9 employs a single input control signal 115' and a single output current 125'
  • an arrangement 500 depicted in Figure 10 employs a single input control signal 125' and a plurality of output currents 125-i.
  • the controller entity 110 may be provided as a single control entity providing the input control signals 115.
  • the controller entity 110 may comprise a number of control entities that are configured to operate independently of each other, each control entity providing at least one of the input control signals 115-1, 115-2, ..., 115-n.
  • the controller entity 110 may be arranged to issue the control signals 115 in response to a user input via a user interface and/or in response to a further control signal received at the controller entity 120 from a further entity.
  • the controller entity 110 may also be a sensor, such as a PIR sensor or a light sensor, and it may be arranged to issue the control signals 115 in response to sensor measurements.
  • the controller entity 110 may be applied e.g. to control operation of an arrangement comprising the driver 120 and the single LED array 170' or to control operation of an arrangement comprising the driver 120 and the two or more LED arrays 170. Moreover, the controller entity 110 may be applied to control e.g. a plurality of drivers 120, each driver arranged to drive one or more LED arrays.
  • the input control signals 115 may be provided in a number of ways and/or in a number of formats. Typically, however, the input control signal 115 is provided as a command or request in accordance with a lighting control protocol. As an example in this regard, the input control signal 115 may be provided as a control signal providing one or more commands according to the Digital Addressable Lighting Interface (DALI) protocol specified in Appendix E.4 of the International Electrotechnical Commission (IEC) standard 60929, in other words as one or more DALI commands.
  • DALI command provided in an input control signal 115-i may e.g.
  • an input control signal 115-1, 115-2, ..., 115-n may be provided as a control signal comprising one or more commands according to the 1-10 V lighting control signaling, as described/specified in Appendix E.2 of the International Electrotechnical Commission (IEC) standard 60929.
  • the voltage of the input control signal 115-i may serve as an indication or as a request of the desired light intensity level associated with the respective output current 125-i implying a request for a certain average current for the respective output current 125-i, as will be described in more detail hereinafter.
  • FIG. 2 schematically illustrates some components of a driver 220.
  • the driver 220 comprises a control portion 230 for issuing control signals 235-1, 235-2, ..., 235-n to control provision of respective driving currents 245-1, 245-2, ..., 245-n.
  • the driver 220 further comprises power converter portions 240-1, 240-2, ..., 240-n for converting the operating power 117 supplied thereto into said respective driving currents 245-1, 245-2, ..., 245-n.
  • the power converter portions 240-i serve as power source portions for providing the respective driving currents 245-i.
  • the driving currents 245 may be provided as separate output currents of the driver 220, possibly via an output current portion (not shown) arranged to derive the output currents 125 on basis of the driving currents 245.
  • the driver 220 may operate e.g. as the driver 120 of the arrangement 100 or 100', and hence the driving currents 245 may be provided e.g. as output currents 125 of the arrangement 100 or 100'.
  • the control portion 230 is, preferably, configured to issue the control signals 235-i as suitable signals exhibiting a duty cycle D i at the cycle frequency f ctrl .
  • An example of such a signal is a PWM signal exhibiting the duty cycle D i at the cycle frequency f ctrl .
  • Figure 3 provides an example of a PWM signal, i.e. a square wave signal consisting of a sequence of cycles, each cycle having an active period (active state, 'high' state) of duration t on , a non-active period (non-active state, 'low' state) of duration t off , and overall duration t c .
  • the 'high' state may be provided e.g. as a voltage/current that is greater than or equal to a predetermined high threshold current while the 'low' state may be provided e.g. as a voltage/current that is smaller than or equal to a predetermined low threshold.
  • the low threshold may be set to zero.
  • a signal of other type exhibiting the desired duty cycle D i may be employed as the control signal 235, e.g. a square wave signal that does not exhibit strictly constant cycle duration t c and therefore may not qualify as a PWM signal according a strict interpretation of the term PWM signal.
  • the control signal 235 may be provided as a PWM-type signal consisting pulses (i.e. active periods exhibiting the 'high' state) having shape different from square waves at the desired duty cycle D i .
  • the duty cycle D i is, preferably, set in accordance with the respective input control signal 115-i.
  • the duty cycles D i may be the same across all control signals 235 or the duty cycles D i may vary from one control signal 235 to another.
  • the control portion 230 may be configured to apply a predetermined mapping function to convert the specified/requested light intensity level into the duty cycle D i for the corresponding control signal 235-i.
  • control portion 230 may be configured to apply a(nother) predetermined mapping function to convert the specified/requested light intensity level into the duty cycle D i for the corresponding control signal 235-i.
  • the control signals 235 may employ a fixed predetermined cycle frequency f ctrl .
  • the applied cycle frequency f ctrl may be e.g. in the range 150 to 1000 Hz.
  • the applied cycle frequency f ctrl may be determined in accordance with the number of driving currents 245 employed by the driver 220.
  • the control signals 235 may employ cycle frequency f ctrl that is selected in accordance with the desired duty cycle, e.g. such that a lower duty cycle implies lower cycle frequency and vice versa.
  • the applied cycle frequency f ctrl is changed during operation of the driver, it is preferably changed simultaneously or essentially simultaneously for all control signals 245.
  • the driver 220 may be configured to apply a first cycle f ctrl_H frequency if the duty cycles D i are greater than or equal to a predetermined threshold duty cycle D TH and to apply otherwise a second cycle frequency f ctrl_L that is lower than the first cycle frequency f ctrl_H .
  • the driver 220 may be configured to apply a mapping function for determining the cycle frequency f ctrl on basis of the duty cycles D i such that a lower duty cycle implies lower cycle frequency. In case different duty cycles D i are applied for the control signals 235, the lowest duty cycle D i among the control signals 235 may determine the cycle frequency applied in all control signals 235.
  • the control portion 230 is configured to issue the control signals 235-1, 235-2, ..., 235-n in predetermined time offsets with respect to each other.
  • Providing the control signals 235-1, 235-2, ..., 235-n in suitably selected predetermined time offsets contributes to providing the respective output currents 125-1, 125-2, ..., 125-n in respective time offsets (or, broadly, in respective phase differences) in relation to each other.
  • the control signals 235 may be considered as synchronized control signals in the sense of employing the same or essentially similar cycle frequency f ctrl .
  • the control signals 235 are not time-aligned but exhibit said predetermined time offsets with respect to each other, such that the starting times of corresponding cycles of the control signals 235 are separated in time by the amount defined by the respective time offsets.
  • a purpose of such provision of the control signals 235 is to reduce or even eliminate the time periods during which none of the respective output currents 125 is in active state. Consequently, when the output currents 125 are coupled to drive the single LED array 170', the periods during which the LED array 170' is not providing light (i.e. the periods when none of the output currents 125 is in active state or, conversely, when all output currents 125 are in non-active state) are made shorter.
  • the output currents 125 are coupled to drive the plurality of LED arrays 170 arranged in a single light fixture or luminaire, the periods during which the light fixture or luminaire is not providing light are made shorter.
  • control signals 235-i setting the control signals 235-i to employ suitable duty cycles D i , suitable cycle frequency f ctrl and suitable time offsets with respect to each other enables jointly employing the output currents 125-1, 125-2, ..., 125-n to drive the LED array(s) 170, 170' according to an effective duty cycle D out at an effective cycle frequency f out that is higher than the cycle frequency f ctrl of the control signals 235 e.g. to cause the LED array(s) 170, 170' to provide light at desired light intensity level (corresponding to the effective duty cycle D out ), e.g. to provide desired dimming of light provided by the LED array(s) 170, 170'.
  • a particular advantage arising from such an approach is that the LED arrays 170, 170' can be effectively driven according to a high cycle frequency while still employing a low cycle frequency for deriving each of the individual output currents 125-i.
  • the time offsets may be expressed directly as time (e.g. in milliseconds or nanoseconds) or e.g. in relation to the overall cycle duration t c as a percentage of cycle duration.
  • the time offset between the control signals 235 may be also referred to as phase differences between the control signals 235.
  • control signals 235-1, 235-2, ..., 235-n in advantageous time offsets (or time differences, phase differences) with respect to each other and the relationship between the duty cycles D i and the cycle frequency f ctrl applied in the controls signals 235-i and the resulting effective duty cycle D out and the effective cycle frequency f out is discussed in detail hereinafter.
  • the control portion 230 may be configured to issue the control signals 235 independently of each other, thereby directly providing two or more control signals 235 exhibiting desired time offsets with respect to each other.
  • control portion 230 may be configured to issue a single source control signal and to apply time-shifting to the single source control signal to generate the two or more control signals 235 exhibiting the desired time offsets with respect to each other, i.e. two or more synchronized control signals 235 exhibiting desired time offsets between each other.
  • the single source control signal may constitute as such one of the control signals 235, whereas the other control signals 235 are generated by time-shifting.
  • instead of a single source control signal there may be a number of source control signals that are time-shifted to generate the two or more control signals 235 exhibiting the desired time offsets with respect to each other.
  • control portion 230 may be configured to issue two or more synchronized and time-aligned source control signals where the corresponding cycles of the control signals 235 coincide in time, and to apply time-shifting to at least one of these synchronized source control signals in order to provide the two or more control signals 235 exhibiting predetermined time offset with respect to each other.
  • this may include providing one of the synchronized source control signals as such as the respective control signal 235 while the other one or more synchronized source control signals are time-shifted to introduce the desired time offsets with respect to the non-shifted synchronized source control signal.
  • control portion 230 may be configured to issue the control signals 235 in different phases (only) in response to the desired duty cycles D i being less than 100 % for more than two control signals 235.
  • the power converter portions 240-i may be provided as switched-mode converters configured to convert the operating power 117 provided as input thereto at a first voltage into respective driving currents 245-i.
  • a switched mode converter may be embodied as a buck converter or another suitable converter for converting a first DC voltage into a second DC voltage according to desired voltage conversion characteristics.
  • Such power converters are known in the art.
  • Each of the power converter portions 240-i is preferably configured to provide, when enabled, the respective driving current 245-i at constant or essentially constant predetermined level.
  • each of the power converter portions 240-i is typically arranged to provide the driving current at the same or at similar level.
  • the power converter portions 240-i may be configured to provide, when enabled, constant or essentially constant output voltage.
  • each power converter portion 240 may be embodied as a buck converter.
  • Figure 4 schematically illustrates a buck converter arranged to drive the LED array 170-i.
  • This exemplifying buck converter receives the operating power via the input V in and comprises a switch S, a diode D, an inductor L and a capacitor C.
  • the driving circuitry DRV is arranged to operate, i.e. to periodically open and close at a frequency significantly higher than the cycle frequency f ctrl , the switch S in a suitable manner in order to result in a desired output current to be provided via the inductor L to the LED array 170-i exemplifying a load coupled to the exemplifying buck converter.
  • Suitable driving circuits DRV are known in the art, and further details regarding the operation logic of the driving circuit DRV are outside the scope of the present invention.
  • the control signal 235-i may be provided as an input to the driving circuitry DRV of the buck converter serving as the power converter portion 240-i, and the driving circuitry DRV is configured to operate the switch S to provide the respective driving current 245-i during active periods of the control signal 235-i, while on the other hand the driving circuitry DRV is configured to keep the switch S in open state during non-active periods of the control signal 235-i, thereby providing the driving current 245-i as zero current or current that is essentially zero.
  • the control signal 235-i causes the power converter portion 240-i to enable and disable provision of the driving current 245-i in accordance with the control signal 235-i.
  • the driving current 245-i exhibits alternating active and non-active periods following or at least approximating the duty cycle D i and the cycle frequency f ctrl of the control signal 235-i.
  • the phase of the driving current 245-i follows that of the control signal 235-i in relation to the phases of the driving currents 245 derived in control of the other control signals 235.
  • the driving currents 245-i exhibit the constant (predetermined) current
  • the driving currents 245-i exhibit zero current or current that is essentially zero, resulting in an average current corresponding to the requested light intensity level.
  • control portion 230 is configured to issue the control signals 235 such that they exhibit predetermined time offset with respect to each other.
  • the control portion may be configured to issue the control signals 235 in evenly distributed time offsets.
  • the time offsets for the control signals 235 are preferably set such that they are evenly distributed over the total cycle duration t c .
  • the two controls signals 235-1 and 235-2 may be considered to be in opposite phases. This also implies time offsets evenly distributed over the overall duration of the cycle t c . If using the phase shift (or phase difference) as the measure in this regard, the two control signals 235-1 and 235-2 exhibit phase difference of 180°, thereby setting the two controls signals 235-1 and 235-2 in opposite phases.
  • the phases of the four control signals 235-1 to 235-4 may be issued in time offsets of 25 % (i.e. t c / 4) to provide even distribution over the overall cycle duration t c , thereby corresponding to phases set into 90° intervals.
  • the first and second control signals 'take in providing active periods
  • the curve (c) indicates the combined effect of the first and second control signals.
  • the output currents 125-i derived on basis of the driving currents 245 and coupled to the single LED array 170' may be employed to drive the LED array 170' at an effective duty cycle D out approximating the duty cycle D sum and at an effective cycle frequency f out that approximate the cycle frequency f sum .
  • the output currents 125-i coupled to the LED arrays 170-i, respectively may be employed to drive a luminaire comprising the LED arrays 170-i at the effective duty cycle D out approximating the duty cycle D sum and at an effective cycle frequency f out that approximates the cycle frequency f sum .
  • a benefit of such an approach is that it allows increasing the effective cycle frequency provided in the output currents 125-i without the need to increase the cycle frequency applied in the control signals 235-i.
  • any flicker in the resultant light is at a higher frequency, while the accuracy of the light intensity control is not compromised.
  • the curve (d) of Figure 5a schematically illustrates the variations in the level of the sum of output currents 125 (denoted as I 125 in Figure 5a ) provided to the single LED array 170' or to the LED arrays 170-i on basis of the first and second control signals.
  • the duty cycle D sum in the combined signal may be considered to be 100 %.
  • the sum of output currents 125 as indicated by the curve (c) of Figure 5b , exhibits periodic variation, which may, consequently, result in corresponding variation in the color or color temperature of the light provided by the single LED array 170'.
  • the momentary lighting level provided by the luminaire may exhibit variation in intensity of light provided by the LED arrays 170 in accordance with the variation in the sum of the output currents 125.
  • the difference to the example of Figures 5a and 5b is that the first control signal employs the first duty cycle D 1 and the cycle frequency f ctrl (curve (a)) while the second control signal employs a second duty cycle D 2 ⁇ D 1 (with t on2 ⁇ t on1 ) at the cycle frequency f ctrl (curve (b)).
  • the first control signal employs the first duty cycle D 1 and the cycle frequency f ctrl (curve (a)) while the second control signal employs a second duty cycle D 2 ⁇ D 1 (with t on2 ⁇ t on1 ) at the cycle frequency f ctrl (curve (b)).
  • the phases of the first and second control signals are in this example evenly distributed by using the mid-points of an active period of a cycle as the reference point for determining the time offsets and by setting the time offsets such that the mid-points of the active-periods in the two control signals are offset by t c / 2.
  • the combined effect of the first and second control signals now exhibits cycles having duration that alternates between t c -sum1 and t c -sum2 where t c- sum1 ⁇ t c -sum2 as can be seen in the sum of the resulting output currents schematically illustrated in curve (c).
  • time offsets between the control signals 235 may be set to differ from each other according a predetermined rule such that the resulting distribution of phases over the total duration of the cycle t c is not even.
  • the controller entity 110 may be arranged to provide the control signals 115 to cause the control portion 230 to set the duty cycles D i to values whose sum is equal to or approximates the desired effective duty cycle D out .
  • the input control signals 115 may be arranged to request the driver 220 to provide the same duty cycle D i , determined by dividing the desired effective duty cycle D out by the number of power converter portions 240 applied in the driver 220.
  • the above considerations regarding the sum of the duty cycles D sum serving as an indication of the effective duty cycle D sum that can be obtained as combination of the output currents 125-i fully applies for the scenario where the active periods of the control signals 235 (and hence the active periods of the driving currents 245) do not overlap in time.
  • the resulting effective duty cycle D out may be smaller than the sum of the duty cycles D sum .
  • the input control signals 115 causing the control portion 230 to set the duty cycles D i to values whose sum is greater than 100 % the resulting effective duty cycle will be 100 %.
  • the periods during which none of the respective output currents 125 is in active state are shortened and/or made less frequent, and hence the periods during which the LED array 170' is or the plurality of LED arrays 170 are not providing any light are likewise shortened and/or made less frequent.
  • the appropriate number of the power converter portions may be selected e.g. in view of the applied or applicable cycle frequency f ctrl in relation to the desired or required effective cycle frequency f sum . This selection may be made (further) in view of limitations with respect to the physical size of the driver 220, standards or regulations prohibiting the light provided by the LED light sources from flickering at a certain frequency or within a certain range of frequencies, etc.
  • FIG 8 schematically illustrates some components of a driver 320.
  • a number of components of the driver 320 are similar to the corresponding components of the driver 220.
  • the control portion 230 and the power converter portions 240 are configured to operate in a manner described in context of the driver 220.
  • the driver 320 may operate e.g. as the driver 120 of the arrangement 100 or 100', and hence the driving currents 245 of the driver 320 may be provided e.g. as output currents 125 of the arrangement 100 or 100'.
  • a difference to the driver 220 is that in the driver 320 the control signals 235-1, 235-2, ..., 235-n issued by the control portion 240 are provided to control respective switches 350-1, 350-2, ..., 350-n arranged to control provision of the respective driving currents 245-1, 245-2, ..., 245-n for the output of the driver 320.
  • the control signal 245-i is arranged to control the respective switch 350-i such that the switch 350-i is kept closed during active periods of the control signal 235-i while the switch 350-i is kept in open state during non-active periods of the control signal 235-i.
  • the switches 350-i are controlled to enable or disable provision of the respective driving current 245-i as the output current 115-i of the driver 320. Consequently, the respective driving current 245-i, as provided to the output of the driver 320, is caused to exhibit alternating active and non-active periods following or at least approximating the duty cycle D i and the cycle frequency f ctrl of the control signal 235-i. Moreover, also the phase of the driving current 245-i follows that of the control signal 235-i in relation to the phases of the driving currents 245 derived in control of the other control signals 235. Therefore, during active periods the driving currents 245-i exhibit the constant (predetermined) current, whereas during non-active periods the driving currents 245-i exhibit zero current or current that is essentially zero, resulting in an average current corresponding to the requested light intensity level,
  • FIG 13 schematically illustrates some components of a driver 620.
  • a number of components of the driver 620 are similar to the corresponding components of the drivers 220 and 320.
  • the control portion 230 is configured to operate in a manner described hereinbefore in context of the driver 220 and/or, 320.
  • the driver 620 may operate e.g. as the driver 120 of the arrangement 100 or 100', and hence the driving currents 245 of the driver 620 may be provided e.g. as output currents 125 of the arrangement 100 or 100'.
  • the driver 620 comprises a voltage source portion 640 serving as a power source portion for providing the driving currents 245-i.
  • the voltage source portion 640 is configured to provide constant or essentially constant driving voltage for provision of the driving currents 245-i.
  • the driver 620 comprises the switches 350-i arranged to control provision of the respective driving currents 245-i in control of the respective control signal 245-i: along the lines described for the driver 320, also in the driver 620 the control signal 245-i is arranged to control the respective switch 350-i such that the switch 350-i is kept closed during active periods of the control signal 235-i while the switch 350-i is kept in open state during non-active periods of the control signal 235-i, thereby resulting in the respective driving currents 245-i exhibiting alternating active and non-active periods following or at least approximating the duty cycle D i , the cycle frequency f ctrl and phase of the control signal 235-i.
  • the driving currents 245-i exhibit the driving voltage, while during non-active periods the driving currents 245-i exhibit voltage that is zero or essentially zero, thereby resulting in an average voltage corresponding to the requested light intensity level.
  • the driving currents 245-i are provided as respective output currents 125-i of the driver 620.
  • the voltage source portion 640 may comprise a single power converter portion arranged to provide the constant driving voltage for provision of the driving currents 245-i on basis of the operating power 117 supplied to the driver 620.
  • the single power converter portion may be provided e.g. as a switched-mode converters configured to convert the operating power 117 provided at a first voltage into the predetermined (constant) driving voltage.
  • the switched mode converter may be embodied as a buck converter or another suitable converter for converting a first DC voltage into a second DC voltage according to desired voltage conversion characteristics.
  • General operation of a buck converter is well known for a person skilled in the art - and also briefly described in context of the power converter portions 240.
  • the buck converter may be operated independently of the control signal 235-i, i.e. the driving circuit DRV is arranged to continuously operate the switch S to cause the buck converter to provide the driving voltage.
  • the operating power 117 supplied to the driver 620 may be provided directly at the desired driving voltage. Consequently, the voltage source portion 640 may be arranged to pass the input voltage as the driving voltage for provision of the driving currents 245-i and the voltage source portion 640 may hence be provided without power converter portion.
  • Figure 9 schematically illustrates a third exemplifying arrangement 400 as a variation of the first arrangement 100.
  • the difference to the arrangement 100 is that a controller entity is arranged to issue a single input control signal 115' instead of the input control signals 115-i applied in the arrangement 100, while a driver 420 of the arrangement 400 is arranged to receive the single input control signal 115' and to provide a single output current 125' instead of the output currents 125-i applied in the arrangement 100.
  • Figure 10 schematically illustrates a fourth exemplifying arrangement 500 as another variation of the first arrangement 100.
  • the difference to the arrangement 100 is that the controller entity 410 is arranged to issue the single input control signal 115'. While illustrated in Figure 10 as variation of the arrangement 100, respective variations may be provided on basis of the arrangement 100' as well.
  • the drivers 420 and 520 may be provided e.g. as a variation of any of the drivers 220, 320 and 620 described hereinbefore.
  • the difference to the drivers 220, 320 and 620 is that due to receiving the single input control signal 115' (instead of the plurality of control signals 115), the control portion 230 is configured to derive the duty cycles D i to be applied in the respective control signals 235-i on basis of the characteristics of the single input control signal 125'.
  • the driver 420 comprises an output portion configured to combine the driving currents 245 into a single output current 125', thereby providing the single output current 125' as a combined signal employing the effective duty cycle D out at the effective cycle frequency f out in accordance with the duty cycles D i , the cycle frequency f ctrl and the time offsets introduced to the control signals 245-i.
  • the drivers 420 and 520 are advantageous in that they may be provided as entities employing a smaller number of input lines for provision the input control signal(s) compared to drivers 220, 320 and 620.
  • the single input control signal 115' may provide one or more DALI commands or one or more commands according to the 1-10 V lighting control signaling specifying or requesting a desired light intensity level to be provided by (the combination of) the output currents 125 or by the single output current 125'.
  • the control portion 230 may be configured to apply respective predetermined mapping function to determine the corresponding desired duty cycle D in on basis of the specified/requested light intensity level.
  • the control portion 230 may be configured to derive the duty cycles D i for the respective control signals 235-i on basis of the value D in .
  • the single input control signal 115' may provide a DALI command or a command according the 1-10 V lighting control signaling addressed to the driver 420 or 520 as a whole, the command indicating a request to provide a desired light intensity level by the single output current 125' or the desired light intensity level by (the sum of) the plurality of output currents 125.
  • the control portion 230 may be configured to apply a (respective) predetermined mapping function to determine the duty cycle D in corresponding to the requested light intensity level, to select the duty cycles D i for the respective control signals 235-i on basis of the value D in e.g.
  • the driver 420 or 520 is provided with an indication of the desired light intensity level, while the control logic required to determine the actually applied duty cycles D i in the individual control signals 245-i is located in the control portion 230.
  • the operation of the driver 420 or 520 otherwise follows that of the driver 220 or 320 e.g. within framework of the arrangement 100 or the arrangement 100'.
  • the control portion 230 may be configured to set duty cycles D i such that their sum equals to the duty cycle D in , e.g.
  • D i D in / N, where N denotes the number of driving currents 245 applied in the driver 420 or 520. If the driver 420 or 520 is configured to distribute the time offsets evenly or essentially evenly over the overall cycle duration t c , this serves to ensure that only one of the output currents 125-i is active at any given moment of time, thereby contributing to the resulting color or color temperature of light provided by the single LED array 170' being perceived by a human observer as constant or essentially constant.
  • the single input control signal 115' providing a DALI command or a command according the 1-10 V lighting control signaling addressed to the driver 420 or 520 as a whole may indicate a request to provide the desired light intensity level in each of the output current 125-i. Consequently, the determined duty cycle D in corresponding to the requested light intensity level may be applied as the duty cycle D i for each of the control signals 235-i. Since in such a scenario the light intensity levels provided by the output currents 125-i are individually controlled outside the driver 520, the entity providing the requests (e.g. the control entity 110) is responsible for requesting the light intensity levels for the output currents 125-i such that their combined contribution results in desired overall light intensity level.
  • a separate DALI address may have been assigned to each output current 125-i, and the single input control signal 115' may provide a DALI command addressed to a certain output current 125-i or two or more DALI command addressed to respective two or more output currents 125-i, each command indicating a request to provide a desired light intensity level by the respective driving current 245-i.
  • the control portion 230 may be configured to apply a (respective) predetermined mapping function to determine the duty cycle D i corresponding to the requested light intensity level for the driving current 245-i, and to issue the control signals 235-i at respective duty cycles.
  • control logic for selecting the desired light intensity levels is located outside the driver 520 (e.g. in the controller entity 110), whereas the control logic required to determine the actually applied respective duty cycles D i is located in the control portion 230 of the driver 520.
  • the output currents of the driver 520 follow the commands/requests received in the input control signal 115', and hence the requesting entity (e.g. the control entity 110) is responsible for requesting the light intensity levels for the output currents 125-i such that their combined contribution results in desired overall light intensity level.
  • a driver apparatus comprising one or more power source portions for providing two or more driving currents 245, the method comprising issuing two or more control signals 235 for controlling the provision of two or more driving currents 245, each control signal 235 exhibiting a respective duty cycle D i at a first cycle frequency f ctrl , wherein the two or more control signals 235 are synchronized control signals exhibiting predetermined time offsets with respect to each other for provision of the two or more driving currents 245 in different phases.
  • the control portion 230 of the driver apparatus 220, 320, 420, 520, 620 may be provided by hardware means, by software means, or by combination of hardware and software means.
  • the control portion 230 may be provided as an integrated circuit (IC) or as a processor carrying out instructions stored in a memory, which instructions control provision of the control signals 235 as described hereinbefore.
  • the IC or the processor may be provided with output lines (e.g. output pins) via which the control signals 235 are provided.
  • FIG 11 schematically illustrates an exemplifying apparatus 700 that may be employed for embodying at least the control portion 230 of the driver 220, 320, 420, 520, 620.
  • the apparatus 700 comprises a processor 710 and a memory 720, the processor 710 being configured to read from and write to the memory 720.
  • the apparatus 700 may further comprise further structural units or portions.
  • the processor 710 is illustrated as a single component, the processor 710 may be implemented as one or more separate components.
  • the memory 720 is illustrated as a single component, the memory 720 may be implemented as one or more separate components.
  • the memory 720 may store a computer program 750 comprising computerexecutable instructions that control the operation of the apparatus 700 when loaded into the processor 710 and executed by the processor 710.
  • the computer program 750 may include one or more sequences of one or more instructions.
  • the computer program 750 may be provided as a computer program code.
  • the processor 710 is able to load and execute the computer program 750 by reading the one or more sequences of one or more instructions included therein from the memory 720.
  • the one or more sequences of one or more instructions may be configured to, when executed by one or more processors, cause the apparatus 700 to implement the operations, procedures and/or functions described hereinbefore in context of the control portion 230.
  • the apparatus 700 may comprise at least one processor 710 and at least one memory 720 including computer program code for one or more programs, the at least one memory 720 and the computer program code configured to, with the at least one processor 710, cause the apparatus 700 to perform the operations, procedures and/or functions described hereinbefore in context of the control portion 230.
  • FIG 12 schematically illustrates an example circuit 800 that may be employed for embodying the control portion 230 of the driver 220, 320, 420, 520, 620.
  • the circuit 800 comprises three 'stages', arranged to derive the control signals CTRL 1 , CTRL 2 and CTRL 3 , respectively.
  • Each of the control signals CTRL i is based on a source control signal CTRL in and the reference signal REF i of the respective stage.
  • the source control signal CTRL in may a control signal derived on basis of a command or request received in the single input control signal 115' or on basis of command(s) or request(s) received in the plurality of control signals 115, exhibiting duty cycle corresponding the command(s)/request(s) at selected cycle frequency.
  • the control signals CTRL 1 , CTRL 2 and CTRL 3 may be provided as the control signals 235.
  • the first two stages comprise an amplifier AMP i , a resistor R i and a capacitor C i while the last stage comprises the AMP i , where the index i denotes the stage number.
  • the stages except the last one comprise the respective amplifier AMP i , the respective resistor R i and the respective capacitor C i while the last 'stage' comprises the AMP i .
  • the resistor R i and the capacitor C i at each stage implement the so-called RC circuit known in the art.
  • the components corresponding to the resistor R i and the capacitor Ci are selected to provide a desired delay in passing the input control signal CTRL in to the next stage, as described in more detail in the following.
  • the capacitor of the RC circuit is fully discharged after being disconnected from the voltage source for the period of t RC .
  • the RC circuit in each stage i of the circuit 800 provides an intermediate signal corresponding to the shape of the input control signal CTRL in , delayed by (i-1) * t diff to the amplifier AMP i of the respective stage and to the next stage i+1 of the circuit 800.
  • the amplifiers AMP i are arranged to generate the respective control signals CTRL i in accordance with the respective intermediate signal and the reference signal REFi.
  • the above example generalizes into an arrangement where the time shift between two consecutive stages is not the same across stages.
  • circuit 800 is illustrated hereinbefore with three stages, hence providing three control signals. However, the circuit 800 generalizes to any number of stages (two or more stages) and hence to any number (two or more) control signals CTRL i . Moreover, with suitable selection of components for each of the stages, such a circuit may be arranged to provide desired number of control signals 235 exhibiting desired phase differences with respect to each other.

Landscapes

  • Circuit Arrangement For Electric Light Sources In General (AREA)

Claims (11)

  1. Anordnung umfassend ein einzelnes Array (170') aus Leuchtdioden und eine Treibervorrichtung (120, 220, 320, 420, 520, 620) zum Ansteuern des einzelnen Arrays (170') aus Leuchtdioden, wobei das einzelne Array (170') aus Leuchtdioden entweder eine einzelne Leuchtdiode oder zwei oder mehr in Reihe geschaltete Leuchtdioden umfasst, wobei zwei oder mehr separate Ausgangsströme der Treibervorrichtung (120, 220, 320, 420, 520, 620) derart an das einzelne Array (170') aus Leuchtdioden gekoppelt sind, dass ihre Summe ausgelegt ist zum Ansteuern des einzelnen Arrays aus Leuchtdioden, wobei die Treibervorrichtung (120, 220, 320, 420, 520, 620) umfasst:
    einen oder mehrere Stromquellenabschnitte (240-1, 240-2, 240-n) zum Liefern von zwei oder mehr Ansteuerströmen (245-1, 245-2, 245-n) als die jeweiligen zwei oder mehr separaten Ausgangsströme der Treibervorrichtung (120, 220, 320, 420, 520, 620), und
    einen Steuerabschnitt (230) zum Ausgeben von zwei oder mehr Steuersignalen (235-1, 235-2, 235-n) zum Steuern der Lieferung der zwei oder mehr Ansteuerströme (245-1, 245-2, 245-n), wobei jedes Steuersignal ein jeweiliges Tastverhältnis mit einer ersten Zyklusfrequenz aufweist,
    wobei der Steuerabschnitt (230) ausgelegt ist zum Ausgeben der zwei oder mehr Steuersignale (235-1, 235-2, 235-n) als synchronisierte Steuersignale in vorbestimmten Zeitoffsets bezüglich einander für die Lieferung der zwei oder mehr jeweiligen Ansteuerströme (245-1, 245-2, 245-n) in verschiedenen Phasen, und
    wobei der Steuerabschnitt (230) ausgelegt ist zum
    Empfangen eines einzelnen Befehls oder einer einzelnen Anforderung (115'), die einen angeforderten Lichtintensitätspegel anzeigt, der durch die Summe aus den zwei oder mehr Ansteuerströmen (245-1, 245-2, 245-n) geliefert werden soll,
    Ableiten eines Tastverhältnisses entsprechend dem angeforderten Lichtintensitätspegel durch Verwenden einer vordefinierten Abbildungsfunktion,
    Einstellen der jeweiligen Tastverhältnisse für die zwei oder mehr Steuersignale (235-1, 235-2, 235-n), so dass ihre Summe gleich dem abgeleiteten Tastverhältnis ist, und
    Ausgeben der zwei oder mehr Steuersignale (235-1, 235-2, 235-n) mit den jeweils eingestellten Tastverhältnissen.
  2. Anordnung nach Anspruch 1,
    wobei der Steuerabschnitt (230) ausgelegt ist zum Ausgeben mindestens eines Quellsteuersignals (CTRLin), und
    Anwenden einer Zeitverschiebung auf das mindestens eine Quellsteuersignal (CTRLin) zum Erzeugen der zwei oder mehr Steuersignale (235-1, 235-2, 235-n), die die vorbestimmten Zeitoffsets bezüglich einander aufweisen.
  3. Anordnung nach Anspruch 1 oder 2, wobei der Steuerabschnitt (230) ausgelegt ist zum Ausgeben der zwei oder mehr Steuersignale (235-1, 235-2, 235-n) in gleichmäßig verteilten Zeitoffsets.
  4. Anordnung nach Anspruch 3, wobei die Treibervorrichtung ausgelegt ist zum Liefern einer vorbestimmten Anzahl N von Ansteuerströmen (245-i), und wobei der Steuerabschnitt (230) ausgelegt ist zum Ausgeben der jeweiligen zwei oder mehr Steuersignale (235-i) in jeweiligen Zeitoffsets von i/N, wobei i=1, ... N, einer Gesamtzyklusdauer.
  5. Anordnung nach einem der Ansprüche 1 bis 4,
    wobei der eine oder die mehreren Stromquellenabschnitte (240-1, 240-2, 240-n) zwei oder mehr jeweilige Leistungswandlerabschnitte (240-1, 240-2, 240-n) umfassen, die ausgelegt sind zum Umwandeln von an die Treibervorrichtung gelieferter Arbeitsleistung (117) in die jeweiligen zwei oder mehr Ansteuerströme (245-1, 245-2, 245-n), und
    wobei der Steuerabschnitt (230) ausgelegt ist zum Ausgeben der zwei oder mehr Steuersignale (235-1, 235-2, 235-n) an die jeweiligen zwei oder mehr Leistungswandlerabschnitte (240-1, 240-2, 240-n), um zu bewirken, dass der jeweilige Leistungswandlerabschnitt die Lieferung des jeweiligen Ansteuerstroms gemäß dem jeweiligen Steuersignal aktivieren und deaktivieren kann.
  6. Anordnung nach einem der Ansprüche 1 bis 4,
    wobei der eine oder die mehreren Stromquellenabschnitte (240-1, 240-2, 240-n) zwei oder mehr jeweilige Leistungswandlerabschnitte (240-1, 240-2, 240-n) umfassen, die ausgelegt sind zum Umwandeln von an die Treibervorrichtung gelieferter Arbeitsleistung (117) in die jeweiligen zwei oder mehr Ansteuerströme (245-1, 245-2, 245-n), und
    wobei der Steuerabschnitt (230) ausgelegt ist zum Ausgeben der zwei oder mehr Steuersignale (235-1, 235-2, 235-n) zum Steuern jeweiliger zwei oder mehr Schalter (350), die angeordnet sind, um die Lieferung der jeweiligen Ansteuerströme (245-1, 245-2, 245-n) von dem jeweiligen Leistungswandlerabschnitt (240-1, 240-2, 240-n) gemäß dem jeweiligen Steuersignal (235-1, 235-2, 235-n) zu aktivieren und zu deaktivieren.
  7. Anordnung nach einem der Ansprüche 1 bis 4,
    wobei der eine oder die mehreren Stromquellenabschnitte (240-1, 240-2, 240-n) einen Spannungsquellenabschnitt (640) umfassen, der ausgelegt ist zum Liefern einer konstanten Ansteuerspannung zur Lieferung der zwei oder mehr Ansteuerströme (245-1, 245-2, 245-n), und
    wobei der Steuerabschnitt (230) ausgelegt ist zum Ausgeben der zwei oder mehr Steuersignale (235-1, 235-2, 235-n) zum Steuern jeweiliger zwei oder mehr Schalter (350), die angeordnet sind zum Steuern der Lieferung der konstanten Ansteuerspannung zum Liefern der jeweiligen Ansteuerströme (245-1, 245-2, 245-n) gemäß dem jeweiligen Steuersignal (235-1, 235-2, 235-n).
  8. Anordnung nach Anspruch 7, ausgelegt zum Empfangen einer Eingangsspannung (117), wobei der Spannungsquellenabschnitt (640) einen Leistungswandlerabschnitt zum Umwandeln der Eingangsspannung (117) in die konstante Ansteuerspannung umfasst.
  9. Anordnung nach einem der Ansprüche 1 bis 8, wobei die zwei oder mehr Steuersignale (235-1, 235-2, 235-n) eine Reihe von Zyklen umfassen, wobei jeder Zyklus aus einer aktiven Periode und einer inaktiven Periode gemäß dem jeweiligen Tastverhältnis und der ersten Zyklusfrequenz besteht.
  10. Anordnung nach Anspruch 8,
    wobei die zwei oder mehr Steuersignale (235-1, 235-2, 235-n) als Impulsbreitenmodulationssignale geliefert werden.
  11. Verwendung einer Treibervorrichtung (120, 220, 320, 520, 620) und einer Summe aus zwei oder mehr separaten, durch die Treibervorrichtung (120, 220, 320, 520, 620) gelieferten separaten Ausgangsströme zum Ansteuern eines einzelnen Arrays (170') aus Leuchtdioden, wobei das einzelne Array (170') aus Leuchtdioden entweder eine einzelne Leuchtdiode oder zwei oder mehr in Reihe geschaltete Leuchtdioden umfasst, wobei die Treibervorrichtung (120, 220, 320, 520, 620) umfasst:
    einen oder mehrere Stromquellenabschnitte (240-1, 240-2, 240-n) zum Liefern von zwei oder mehr Ansteuerströmen (245-1, 245-2, 245-n) als die jeweiligen zwei oder mehr separaten Ausgangsströme der Treibervorrichtung (120, 220, 320, 420, 520, 620), und
    einen Steuerabschnitt (230) zum Ausgeben von zwei oder mehr Steuersignalen (235-1, 235-2, 235-n) zum Steuern der Lieferung der zwei oder mehr Ansteuerströme (245-1, 245-2, 245-n), wobei jedes Steuersignal ein jeweiliges Tastverhältnis mit einer ersten Zyklusfrequenz aufweist,
    wobei der Steuerabschnitt (230) ausgelegt ist zum Ausgeben der zwei oder mehr Steuersignale (235-1, 235-2, 235-n) als synchronisierte Steuersignale in vorbestimmten Zeitoffsets bezüglich einander für die Lieferung der zwei oder mehr jeweiligen Ansteuerströme (245-1, 245-2, 245-n) in verschiedenen Phasen, und
    wobei der Steuerabschnitt (230) ausgelegt ist zum
    Empfangen eines einzelnen Befehls oder einer einzelnen Anforderung (115'), die den angeforderten Lichtintensitätspegel anzeigt, durch die Summe aus den zwei oder mehr Ansteuerströmen (245-1, 245-2, 245-n),
    Ableiten eines Tastverhältnisses entsprechend dem angeforderten Lichtintensitätspegel durch Verwenden einer vordefinierten Abbildungsfunktion,
    Einstellen der jeweiligen Tastverhältnisse für die zwei oder mehr Steuersignale (235-1, 235-2, 235-n), so dass ihre Summe gleich dem abgeleiteten Tastverhältnis ist, und
    Ausgeben der zwei oder mehr Steuersignale (235-1, 235-2, 235-n) mit den jeweils eingestellten Tastverhältnissen.
EP13171212.7A 2013-06-10 2013-06-10 Ansteuerung für eine Lichtquelle Active EP2814300B1 (de)

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ES2604304B1 (es) * 2015-09-03 2018-02-22 Universidad De Málaga Dispositivo de iluminación a base de LEDs con control de dosis automatizado para fotodiagnóstico de enfermedades cutáneas relacionadas con la exposición lumínica, aplicaciones y métodos relacionados
DE102017215736A1 (de) * 2017-09-07 2019-03-07 Osram Gmbh Schaltnetzteil mit mehreren ausgangsstufen
DE102018126249B4 (de) * 2018-10-22 2023-01-26 Infineon Technologies Ag Verfahren zum ansteuern mehrerer lichtemitierender dioden und ansteuerschaltung

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008034242A1 (en) * 2006-09-20 2008-03-27 Tir Technology Lp Light emitting element control system and lighting system comprising same

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6501234B2 (en) * 2001-01-09 2002-12-31 02 Micro International Limited Sequential burst mode activation circuit
US8519680B2 (en) * 2003-07-07 2013-08-27 Rohm Co., Ltd. Load driving device, and lighting apparatus and liquid crystal display device using the same
WO2008102479A1 (ja) * 2007-02-21 2008-08-28 Sharp Kabushiki Kaisha 負荷駆動回路、集積回路、ｄｃ－ｄｃコンバータ、および負荷駆動方法
US20090225020A1 (en) * 2008-03-07 2009-09-10 O2Micro, Inc. Backlight controller for driving light sources
TWI420965B (zh) * 2009-05-26 2013-12-21 Richtek Technology Corp 具有移相調光功能之ｌｅｄ控制器及ｌｅｄ移相調光電路與相關方法
US20120098869A1 (en) * 2010-10-22 2012-04-26 Himax Analogic, Inc. Light Emitting Diode Circuit, Light Emitting Diode Driving Circuit, and Method for Driving Light Emitting Diode Channels

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2008034242A1 (en) * 2006-09-20 2008-03-27 Tir Technology Lp Light emitting element control system and lighting system comprising same

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