EP2801024A4 - Réduction du nombre d'opérations de lecture/écriture effectuées par une cpu pour dupliquer des données sources afin de permettre un traitement parallèle des données sources - Google Patents

Réduction du nombre d'opérations de lecture/écriture effectuées par une cpu pour dupliquer des données sources afin de permettre un traitement parallèle des données sources

Info

Publication number
EP2801024A4
EP2801024A4 EP12864444.0A EP12864444A EP2801024A4 EP 2801024 A4 EP2801024 A4 EP 2801024A4 EP 12864444 A EP12864444 A EP 12864444A EP 2801024 A4 EP2801024 A4 EP 2801024A4
Authority
EP
European Patent Office
Prior art keywords
source data
cpu
read
reducing
parallel processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP12864444.0A
Other languages
German (de)
English (en)
Other versions
EP2801024A1 (fr
Inventor
Yen Hsiang Chew
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of EP2801024A1 publication Critical patent/EP2801024A1/fr
Publication of EP2801024A4 publication Critical patent/EP2801024A4/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory
    • G06F9/30043—LOAD or STORE instructions; Clear instruction
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3824—Operand accessing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/46—Multiprogramming arrangements
    • G06F9/54—Interprogram communication
    • G06F9/544—Buffers; Shared memory; Pipes
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/127—Updating a frame memory using a transfer of data from a source area to a destination area
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/001—Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Image Processing (AREA)
EP12864444.0A 2012-01-06 2012-12-27 Réduction du nombre d'opérations de lecture/écriture effectuées par une cpu pour dupliquer des données sources afin de permettre un traitement parallèle des données sources Withdrawn EP2801024A4 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
MYPI2012000073 2012-01-06
PCT/US2012/071721 WO2013103571A1 (fr) 2012-01-06 2012-12-27 Réduction du nombre d'opérations de lecture/écriture effectuées par une cpu pour dupliquer des données sources afin de permettre un traitement parallèle des données sources

Publications (2)

Publication Number Publication Date
EP2801024A1 EP2801024A1 (fr) 2014-11-12
EP2801024A4 true EP2801024A4 (fr) 2016-08-03

Family

ID=48745377

Family Applications (1)

Application Number Title Priority Date Filing Date
EP12864444.0A Withdrawn EP2801024A4 (fr) 2012-01-06 2012-12-27 Réduction du nombre d'opérations de lecture/écriture effectuées par une cpu pour dupliquer des données sources afin de permettre un traitement parallèle des données sources

Country Status (4)

Country Link
US (1) US9864635B2 (fr)
EP (1) EP2801024A4 (fr)
CN (1) CN104054049B (fr)
WO (1) WO2013103571A1 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9864635B2 (en) 2012-01-06 2018-01-09 Intel Corporation Reducing the number of read/write operations performed by a CPU to duplicate source data to enable parallel processing on the source data
CN106257434B (zh) * 2015-06-16 2019-04-30 深圳市中兴微电子技术有限公司 一种基于增强型外设互连协议总线的数据传输方法及装置
KR102548581B1 (ko) * 2016-01-26 2023-06-29 삼성전자주식회사 데이터 처리 속도를 높이는 터치 스크린 컨트롤러, 및 이를 포함하는 터치 시스템
US10141972B2 (en) 2016-01-26 2018-11-27 Samsung Electronics Co., Ltd. Touch screen controller for increasing data processing speed and touch system including the same
KR102583787B1 (ko) * 2018-11-13 2023-10-05 에스케이하이닉스 주식회사 데이터 저장 장치 및 동작 방법, 이를 포함하는 스토리지 시스템

Citations (2)

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US20040085322A1 (en) * 2002-10-30 2004-05-06 Alcorn Byron A. System and method for performing BLTs
US7019752B1 (en) * 2003-06-04 2006-03-28 Apple Computer, Inc. Method and apparatus for frame buffer management

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US6173389B1 (en) 1997-12-04 2001-01-09 Billions Of Operations Per Second, Inc. Methods and apparatus for dynamic very long instruction word sub-instruction selection for execution time parallelism in an indirect very long instruction word processor
US6100906A (en) * 1998-04-22 2000-08-08 Ati Technologies, Inc. Method and apparatus for improved double buffering
US6862635B1 (en) * 1998-11-13 2005-03-01 Cray Inc. Synchronization techniques in a multithreaded environment
US6785751B1 (en) * 2000-09-19 2004-08-31 Intel Corporation Method and apparatus for minimizing bus contention for I/O controller write operations
US20040078630A1 (en) * 2002-06-28 2004-04-22 Niles Ronald Steven System and method for protecting data
US7477205B1 (en) * 2002-11-05 2009-01-13 Nvidia Corporation Method and apparatus for displaying data from multiple frame buffers on one or more display devices
US7617369B1 (en) * 2003-06-30 2009-11-10 Symantec Operating Corporation Fast failover with multiple secondary nodes
US20050050115A1 (en) * 2003-08-29 2005-03-03 Kekre Anand A. Method and system of providing cascaded replication
JP2006065697A (ja) * 2004-08-27 2006-03-09 Hitachi Ltd 記憶デバイス制御装置
JP4456123B2 (ja) * 2004-12-02 2010-04-28 富士通株式会社 データバッファ装置、キャッシュ装置、データバッファ制御方法
US8810480B2 (en) * 2006-08-04 2014-08-19 Apple Inc. Methods and apparatuses for controlling display devices
EP2095226A1 (fr) * 2006-12-11 2009-09-02 Nxp B.V. Unités fonctionnelles virtuelles pour processeurs vliw
KR101313330B1 (ko) * 2007-02-28 2013-09-27 삼성전자주식회사 이미지 티어링 효과를 방지할 수 있는 영상 표시 시스템 및그것의 영상 표시 방법
CN101344842B (zh) 2007-07-10 2011-03-23 苏州简约纳电子有限公司 多线程处理器及其多线程处理方法
US20110069833A1 (en) * 2007-09-12 2011-03-24 Smith Micro Software, Inc. Efficient near-duplicate data identification and ordering via attribute weighting and learning
WO2010007813A1 (fr) * 2008-07-16 2010-01-21 株式会社ソニー・コンピュータエンタテインメント Dispositif d'affichage d'image de type mobile, procédé de commande de celui-ci et support de mémoire d'informations
CN101639930B (zh) * 2008-08-01 2012-07-04 辉达公司 一连串绘图处理器处理绘图数据的方法及系统
US8749568B2 (en) * 2010-01-11 2014-06-10 Apple Inc. Parameter FIFO
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US9864635B2 (en) 2012-01-06 2018-01-09 Intel Corporation Reducing the number of read/write operations performed by a CPU to duplicate source data to enable parallel processing on the source data

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040085322A1 (en) * 2002-10-30 2004-05-06 Alcorn Byron A. System and method for performing BLTs
US7019752B1 (en) * 2003-06-04 2006-03-28 Apple Computer, Inc. Method and apparatus for frame buffer management

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
DAVID BLACK-SCHAFFER ET AL: "Block-Parallel Programming for Real-Time Embedded Applications", PARALLEL PROCESSING (ICPP), 2010 39TH INTERNATIONAL CONFERENCE ON, IEEE, PISCATAWAY, NJ, USA, 13 September 2010 (2010-09-13), pages 297 - 306, XP031773715, ISBN: 978-1-4244-7913-9 *
See also references of WO2013103571A1 *

Also Published As

Publication number Publication date
CN104054049A (zh) 2014-09-17
US20140310721A1 (en) 2014-10-16
CN104054049B (zh) 2018-04-13
EP2801024A1 (fr) 2014-11-12
US9864635B2 (en) 2018-01-09
WO2013103571A1 (fr) 2013-07-11

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