EP2718979B1 - Thin film solar module having integrated interconnections and method for producing the same - Google Patents

Thin film solar module having integrated interconnections and method for producing the same Download PDF

Info

Publication number
EP2718979B1
EP2718979B1 EP12731322.9A EP12731322A EP2718979B1 EP 2718979 B1 EP2718979 B1 EP 2718979B1 EP 12731322 A EP12731322 A EP 12731322A EP 2718979 B1 EP2718979 B1 EP 2718979B1
Authority
EP
European Patent Office
Prior art keywords
layer
substrate
deposited
solar module
barrier layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Not-in-force
Application number
EP12731322.9A
Other languages
German (de)
French (fr)
Other versions
EP2718979A1 (en
Inventor
Stefan Janz
Stefan Lindekugel
Stefan Reber
Joachim Jaus
Kai SCHILLINGER
Thomas RACHOW
Jonas Bartsch
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fraunhofer Gesellschaft zur Forderung der Angewandten Forschung eV
Albert Ludwigs Universitaet Freiburg
Original Assignee
Fraunhofer Gesellschaft zur Forderung der Angewandten Forschung eV
Albert Ludwigs Universitaet Freiburg
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fraunhofer Gesellschaft zur Forderung der Angewandten Forschung eV, Albert Ludwigs Universitaet Freiburg filed Critical Fraunhofer Gesellschaft zur Forderung der Angewandten Forschung eV
Publication of EP2718979A1 publication Critical patent/EP2718979A1/en
Application granted granted Critical
Publication of EP2718979B1 publication Critical patent/EP2718979B1/en
Not-in-force legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/036—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes
    • H01L31/0392—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including thin films deposited on metallic or insulating substrates ; characterised by specific substrate materials or substrate features or by the presence of intermediate layers, e.g. barrier layers, on the substrate
    • H01L31/03921—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their crystalline structure or particular orientation of the crystalline planes including thin films deposited on metallic or insulating substrates ; characterised by specific substrate materials or substrate features or by the presence of intermediate layers, e.g. barrier layers, on the substrate including only elements of Group IV of the Periodic System
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/142—Energy conversion devices
    • H01L27/1421—Energy conversion devices comprising bypass diodes integrated or directly associated with the device, e.g. bypass diode integrated or formed in or on the same substrate as the solar cell
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/042—PV modules or arrays of single PV cells
    • H01L31/0445—PV modules or arrays of single PV cells including thin film solar cells, e.g. single thin film a-Si, CIS or CdTe solar cells
    • H01L31/046—PV modules composed of a plurality of thin film solar cells deposited on the same substrate
    • H01L31/0465—PV modules composed of a plurality of thin film solar cells deposited on the same substrate comprising particular structures for the electrical interconnection of adjacent PV cells in the module
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic System
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the invention relates to a thin-film-based solar module with integrated interconnection of at least two solar cells comprising an electrically non-conductive substrate or an electrically conductive substrate with an electrically non-conductive barrier layer on which a layer structure comprising at least one crystalline semiconductor layer having a first Doping and at least one crystalline semiconductor layer having a second, opposite to the first doping doping, is deposited.
  • the layer structure in this case has isolation trenches in which the emitter contacts and base contacts are deposited.
  • the invention relates to a method for producing such solar modules.
  • Such a concept is for example from the WO 2008/107205 known in the front side series-connected solar modules are described.
  • the US 5,639,314 A relates to a photovoltaic device with a plurality of interconnected photoelectric cells and a method for their preparation.
  • the method of manufacturing the three-dimensionally shaped photovoltaic device involves first forming a photovoltaic element on a flexible substrate, preferably while it is flat, and then deforming the substrate to achieve the three-dimensional shape.
  • a crystalline photovoltaic conversion layer is first formed on the flat substrate, then the layer is cut or split while the substrate remains uncut to form a plurality of separate adjacent photovoltaic elements on the substrate, and finally the substrate becomes the three-dimensional shape deformed.
  • the cutting can be done by laser irradiation.
  • Deformation may be performed by providing a shape memory element as the substrate or by bonding a shape memory element to the substrate and then returning the shape memory element to its previously stored three dimensional shape.
  • the adjacent photovoltaic elements may be electrically connected in series by applying bonding wires or an insulating film and then a conductive film in the cut regions between adjacent photovoltaic elements.
  • the separation trenches have a flank insulation in the form of a printed, vapor-deposited, deposited or grown nitridic or carbidic layer.
  • the substrate as a whole is completely encapsulated with the barrier layer, wherein the barrier layer consists of or substantially contains a nitridic layer or a carbide layer or combinations thereof, the barrier layer having a thickness of 100 nm to 100 ⁇ m.
  • the layer structure has a front-side insulation layer, which represents a passivation layer.
  • deposition is understood as meaning, in addition to vapor deposition, also a sprayed application, printing process and vapor deposition process.
  • Another essential advantage of the concept according to the invention is based on the integrated interconnection of the solar cells, which are completely variable from the surface, since one starts from a continuous substrate surface and divides it completely into solar cell fields. Due to the special solar cell and interconnection architecture very high efficiencies can be achieved for crystalline silicon, which can also be realized cost-effectively, since already the entire module surface can be processed.
  • the substrate consists of a material selected from the group of zirconium silicates, graphites, glass ceramics, silicate ceramics, oxide ceramics, in particular alumina, titania or silica, nitride ceramics, in particular silicon nitride or titanium nitride, mullites, porcelain, sintered silicon, sintered metals and their composites or contains these in the essential.
  • the layer structure is preferably removed by ablation, more preferably by means of liquid jet guided laser (LCP) or dry laser.
  • LCP liquid jet guided laser
  • a further preferred variant provides that at least one separating trench defines a bypass diode. These make it possible in the case of a defect of a solar cell, that this solar cell can be bridged, so that the function of the solar module is not limited on the whole.
  • the bypass diode is preferably via electrical contacts with the emitter contact and the basic contact.
  • the solar module in the region of the separation trenches one or more edge insulation, preferably to prevent short circuits, on.
  • the layer structure additionally has a front insulation layer.
  • the front-side insulation layer also has the function of a passivation layer.
  • the barrier layer according to the invention consists of a nitridic layer, in particular boron nitride or silicon nitride, or a carbidic layer, in particular silicon carbide or titanium carbide, or combinations thereof, or contains these substantially.
  • the substrate as a whole is completely encapsulated with the barrier layer.
  • edge isolation by means of a printed, evaporated, deposited or grown nitridic or carbidic layer takes place before step c).
  • the substrate as a whole is completely encapsulated with the barrier layer, wherein the barrier layer consists of or substantially contains a nitridic view or a carbide layer or combinations thereof, the barrier layer having a thickness of 100 nm to 100 ⁇ m.
  • a front-side insulation layer is deposited on the semiconductor layer between step b) and c), which represents a passivation layer.
  • a texturing of the substrate with a layer structure deposited thereon is carried out.
  • This is preferably implemented by plasma texture, gas phase texture or wet-chemical texture.
  • a further preferred embodiment provides that the removal of the layer structure in step b) takes place by means of ablation.
  • liquid-jet-guided laser processes (LCP) or dry laser processes are particularly preferred.
  • the emitter contacts and base contacts can preferably be made by vapor deposition, printing or sputtering of metals with subsequent firing of the contacts for making contact, in particular with an RTP oven or by laser firing.
  • a front-side insulation layer is deposited on the semiconductor layer between step b) and c).
  • the preparation of the at least one front-side insulation layer is preferably carried out by means of thermal oxidation of silicon or by deposition by means of plasma-enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD).
  • PECVD plasma-enhanced chemical vapor deposition
  • ALD atomic layer deposition
  • This laser cut is preferably produced by means of a liquid jet guided laser (LCP) or dry laser.
  • LCP liquid jet guided laser
  • flank insulation takes place before step c).
  • This flank insulation is realized according to the invention by means of a printed, vapor-deposited, deposited or grown nitridic or carbidic layer.
  • a further preferred embodiment provides that in at least one separating trench, a bypass diode is integrated, which are connected via electrical contacts to the emitter and the base.
  • Fig. 1 is a first solar module based on thin film with integrated interconnection of two solar cells shown in cross section.
  • a substrate which may be both electrically conductive and electrically non-conductive, completely surrounded by an encapsulation layer 2, which is electrically non-conductive in the present case.
  • a layer structure is deposited, which is deposited from a highly doped layer 3, a normal doped layer 3 'and a layer 4 of opposite highly doped layer 4 of crystalline silicon.
  • the layer structure is interrupted by a separation trench 5 which has been removed by ablation. In the separation trench 5 and partially on the layer structure of the emitter contact 7 and the base contact 8 are deposited.
  • an insulating layer or passivation layer 6 is deposited on the front side of the layer structure.
  • a variant of the solar module according to the invention is shown on a thin film basis.
  • the structure of substrate and layer structure corresponds here to the FIG. 1 , Additionally is in Fig. 2 nor an interruption of the layer structure by means of a laser section 5 'shown.
  • the base contact 8 additionally shows a laser-fired contact 8 '.
  • Fig. 3 is a plan view of a solar module according to the invention shown.
  • the base 11 and the emitter 12 of the individual solar cells are shown.
  • the figure also shows metal fingers for emitter contact 13.
  • the base contact 14 has laser-fired contacts 14 '.
  • a bypass diode 15 is integrated, which is connected via the contacts 16 'and 16 "with the base contacts 14.

Description

Die Erfindung betrifft ein Solarmodul auf Dünnschicht-Basis mit integrierter Verschaltung von mindestens zwei Solarzellen, die ein elektrisch nicht-leitfähiges Substrat oder ein elektrisch leitfähiges Substrat mit einer elektrisch nicht-leitfähigen Barriereschicht, auf dem eine Schichtstruktur, die mindestens eine kristalline Halbleiterschicht mit einer ersten Dotierung sowie mindestens eine kristalline Halbleiterschicht mit einer zweiten, zur ersten Dotierung entgegengesetzten Dotierung, abgeschieden ist, enthält. Die Schichtstruktur weist dabei Trenngräben auf, in denen die Emitterkontakte und Basiskontakte abgeschieden sind. Ebenso betrifft die Erfindung ein Verfahren zur Herstellung derartiger Solarmodule.The invention relates to a thin-film-based solar module with integrated interconnection of at least two solar cells comprising an electrically non-conductive substrate or an electrically conductive substrate with an electrically non-conductive barrier layer on which a layer structure comprising at least one crystalline semiconductor layer having a first Doping and at least one crystalline semiconductor layer having a second, opposite to the first doping doping, is deposited. The layer structure in this case has isolation trenches in which the emitter contacts and base contacts are deposited. Likewise, the invention relates to a method for producing such solar modules.

Der Photovoltaikmarkt weltweit ist derzeit von Solarzellen-Modulen aus kristallinem Wafer-Silicium dominiert. Da die technologische Entwicklung des zugehörigen Zellkonzeptes schon sehr weit fortgeschritten ist, ist der theoretisch mögliche Maximalwirkungsgrad bei Forschungs-Solarzellen bereits zu ca. 90% erreicht. Bei industriell in Serie gefertigten Si-Wafer-Solarzellen wird durch Skalierung und Anpassung der dafür verwendeten Technologien angestrebt, diesen Bestwirkungsgrad zu approximieren. Um einen weiteren Kostenreduktionssprung zu ermöglichen, ist eine grundlegende Änderung des Modulkonzeptes notwendig. Eine vielversprechende Möglichkeit dafür ist das Konzept des integriert verschalteten kristallinen Silicium Dünnschichtmoduls.The photovoltaic market worldwide is currently dominated by solar cell modules made of crystalline silicon wafers. Since the technological development of the associated cell concept is already well advanced, the theoretically possible maximum efficiency of research solar cells has already been reached at about 90%. For industrially mass-produced Si wafer solar cells, scaling and adaptation of the technologies used for this purpose are aimed at approximating this best efficiency. To enable a further cost reduction jump, a fundamental change of the module concept is necessary. A promising possibility for this is the concept of the integrated interconnected crystalline silicon thin-film module.

Ein derartiges Konzept ist beispielsweise aus der WO 2008/107205 bekannt, in der frontseitig serienverschaltete Solarmodule beschrieben sind.Such a concept is for example from the WO 2008/107205 known in the front side series-connected solar modules are described.

Dieses Konzept lehnt sich an die existierenden Dünnschichtkonzepte an, die integrierte Serienverschaltungen von streifenförmigen Solarzellen auf einem Glas-Superstrat realisieren. Die Übertragung dieser gängigen Konzepte auf z.B. kristalline Si-Dünnschichtsolarzellen, deren Halbleiterschicht nach dem Verfahren des Zonenschmelzens (RexWE: Rekristallisiertes Waferäquivalent) hergestellt wurde. Dieses besteht darin, eine elektrisch nicht leitende Platte z.B. mittels Atmosphärendruck Gasphasenabscheidung (APCVD) zu verkapseln und z.B. einseitig mit kristallinem Si (ebenfalls APCVD) zu beschichten. Danach wird diese feinkristalline Si Schicht mittels Zonenschmelzen (ZMR) rekristallisiert. Auf diese kristalline Vorlage wiederum wird nun epitaktisch (mit APCVD) Silicium mit einer anderen Dotierung abgeschieden. Hier treten jedoch folgende Probleme auf:

  • das RexWE-Verfahren ist ein Substrat-, kein Superstrat-Konzept. Damit muss die Verschaltung von der Vorderseite geschehen, nicht von der Rückseite
  • die elektronische Qualität des Halbleiters "kristallines Si" ist um ein vielfaches höher als die der klassischen Dünnschichtsolarzellen (amorphes Si, Cadmiumtellurid, Kupferindiumselenid). Aus diesem Grund darf im Strukturierungsprozess keine Schädigung eingebracht werden, was jedoch bei den klassischen Verfahren der Fall sein kann.
  • Höchste Wirkungsgrade zu erhalten, müssen Textur-, Passivierungs-, und lokale Kontaktierungstechniken in das Verschaltungskonzept eingebaut werden. Auch dies ist bei den klassischen Dünnschichttechniken, sowie bei ersten Ansätzen zur Verschaltung von c-Si-Schichtsystemen, nicht durchgehend realisierbar.
This concept is based on the existing thin-film concepts that realize integrated series interconnections of strip-shaped solar cells on a glass superstrate. The transfer of these common concepts to, for example, crystalline Si thin-film solar cells whose semiconductor layer was produced by the zone melting process (RexWE: Recrystallized Wafer Equivalent). This consists in encapsulating an electrically nonconductive plate, for example by means of atmospheric pressure vapor deposition (APCVD), and, for example, coating it on one side with crystalline Si (also APCVD). Thereafter, this fine-crystalline Si layer is recrystallized by zone melting (ZMR). In turn, epitaxial (with APCVD) silicon with a different doping is deposited on this crystalline template. Here, however, the following problems occur:
  • the RexWE process is a substrate, not a superstrate concept. Thus, the interconnection must be done from the front, not from the back
  • The electronic quality of the semiconductor "crystalline Si" is many times higher than that of the classical thin-film solar cells (amorphous Si, cadmium telluride, copper indium selenide). For this reason, no damage may be introduced in the structuring process, which may, however, be the case with the classical methods.
  • To obtain maximum efficiencies, texture, passivation, and local contacting techniques must be incorporated into the interconnection concept. This, too, can not be consistently realized in the classical thin-film techniques, as well as in the first approaches for the interconnection of c-Si layer systems.

Die US 5,639,314 A betrifft eine photovoltaische Vorrichtung mit mehreren miteinander verbundenen photoelektrischen Zellen sowie ein Verfahren zu deren Herstellung. Das Verfahren zum Herstellen der dreidimensional geformten photovoltaischen Vorrichtung umfasst zuerst das Bilden eines photovoltaischen Elements auf einem flexiblen Substrat, vorzugsweise während es flach ist, und dann das Verformen des Substrats, um die dreidimensionale Form zu erreichen. Vorzugsweise wird zuerst eine kristalline photovoltaische Umwandlungsschicht auf dem flachen Substrat gebildet, dann wird die Schicht geschnitten oder geteilt, während das Substrat ungeschnitten bleibt, um eine Vielzahl von getrennten benachbarten photovoltaischen Elementen auf dem Substrat zu bilden, und schließlich wird das Substrat in die dreidimensionale Form verformt.The US 5,639,314 A relates to a photovoltaic device with a plurality of interconnected photoelectric cells and a method for their preparation. The method of manufacturing the three-dimensionally shaped photovoltaic device involves first forming a photovoltaic element on a flexible substrate, preferably while it is flat, and then deforming the substrate to achieve the three-dimensional shape. Preferably, a crystalline photovoltaic conversion layer is first formed on the flat substrate, then the layer is cut or split while the substrate remains uncut to form a plurality of separate adjacent photovoltaic elements on the substrate, and finally the substrate becomes the three-dimensional shape deformed.

Das Schneiden kann durch Laserbestrahlung erfolgen. Das Verformen kann durchgeführt werden, indem ein Formgedächtniselement als das Substrat bereitgestellt wird oder ein Formgedächtniselement auf das Substrat gebondet wird und dann das Formgedächtniselement in seine zuvor gespeicherte dreidimensionale Form zurückgeführt wird. Die benachbarten photovoltaischen Elemente können elektrisch in Reihe miteinander verbunden werden, indem Bonddrähte oder ein isolierender Film und dann ein leitender Film in den geschnittenen Bereichen zwischen benachbarten photovoltaischen Elementen aufgebracht werden.The cutting can be done by laser irradiation. Deformation may be performed by providing a shape memory element as the substrate or by bonding a shape memory element to the substrate and then returning the shape memory element to its previously stored three dimensional shape. The adjacent photovoltaic elements may be electrically connected in series by applying bonding wires or an insulating film and then a conductive film in the cut regions between adjacent photovoltaic elements.

Ausgehend hiervon war es Aufgabe der vorliegenden Erfindung, Solarmodule mit integrierter Verschaltung und gleichzeitig möglichst geringem Materialabtrag herzustellen, wobei die Herstellung einfach zu handhaben und schnell durchzuführen sein soll.Based on this, it was an object of the present invention to produce solar modules with integrated interconnection and at the same time the lowest possible removal of material, the production should be easy to handle and to perform quickly.

Diese Aufgabe wird durch das Solarmodul mit den Merkmalen des Anspruchs 1 sowie durch das Verfahren zur Herstellung von Solarmodulen mit den Merkmalen des Anspruchs 5 gelöst. Die weiteren abhängigen Ansprüche zeigen vorteilhafte Weiterbildungen auf.This object is achieved by the solar module with the features of claim 1 and by the method for producing solar modules with the features of claim 5. The other dependent claims show advantageous developments.

Erfindungsgemäß wird ein Solarmodul auf Dünnschicht-basis mit integrierter Verschaltung von mindestens zwei Solarzellen bereitgestellt, das

  1. a) ein elektrisch nicht-leitfähiges Substrat; oder
  2. b) ein elektrisch leitfähiges Substrat;
mit einer elektrisch nicht-leitfähigen Barriereschicht, auf dem eine Schichtstruktur, die mindestens eine kristalline Halbleiterschicht mit einer ersten Dotierung sowie mindestens eine kristalline Halbleiterschicht mit einer zweiten, zur ersten Dotierung entgegengesetzten Dotierung enthält, abgeschieden ist, enthält. Dabei weist das Solarmodul isolierende Trenngräben zwischen den einzelnen Solarzellen auf. Dabei ist in den Trenngräben die Schichtstruktur entfernt. Zumindest in einem Teil der Trenngräben und zumindest auf Bereichen der Schichtstruktur sind mindestens ein Emitterkontakt und mindestens ein Basiskontakt mittels Gasphasenabscheidung, Spritzen, Sputtern, Drucken oder Aufdampfverfahren abgeschieden.According to the invention, a thin-film-based solar module with integrated interconnection of at least two solar cells is provided
  1. a) an electrically non-conductive substrate; or
  2. b) an electrically conductive substrate;
with an electrically non-conductive barrier layer on which a layer structure which contains at least one crystalline semiconductor layer with a first doping and at least one crystalline semiconductor layer with a second doping opposite to the first doping is deposited is, contains. The solar module has insulating separation trenches between the individual solar cells. In this case, the layer structure is removed in the separation trenches. At least in one part of the separation trenches and at least on regions of the layer structure, at least one emitter contact and at least one base contact are deposited by means of vapor deposition, spraying, sputtering, printing or vapor deposition.

Erfindungsgemäß weisen die Trenngräben eine Flankenisolation in Form einer gedruckten, aufgedampften, abgeschiedenen oder gewachsenen nitridischen oder carbidischen Schicht auf.According to the invention, the separation trenches have a flank insulation in the form of a printed, vapor-deposited, deposited or grown nitridic or carbidic layer.

Erfindungsgemäß ist das Substrat im Ganzen mit der Barriereschicht vollständig verkapselt, wobei die Barriereschicht aus einer nitridischen Schicht oder einer carbidischen Schicht oder Kombinationen hiervon besteht oder diese im Wesentlichen enthält, wobei die Barriereschicht eine Dicke von 100 nm bis 100 µm aufweist.According to the invention, the substrate as a whole is completely encapsulated with the barrier layer, wherein the barrier layer consists of or substantially contains a nitridic layer or a carbide layer or combinations thereof, the barrier layer having a thickness of 100 nm to 100 μm.

Erfindungsgemäß weist die Schichtstruktur eine frontseitige Isolationsschicht auf, die eine Passivierungsschicht darstellt.According to the invention, the layer structure has a front-side insulation layer, which represents a passivation layer.

Unter Abscheidung im Sinne der vorliegenden Erfindung werden neben einer Gasphasenabscheidung ebenso eine gespritzte Aufbringung, Druckverfahren sowie Aufdampfverfahren verstanden.For the purposes of the present invention, deposition is understood as meaning, in addition to vapor deposition, also a sprayed application, printing process and vapor deposition process.

Die vorliegende Erfindung basiert somit auf einer neuen Solarzellen-Architektur einer integrierten Verschaltung des wenige µm dünnen Siliziumschichtstapels auf dem Substrat. Dabei werden Techniken zum Ablatieren und Trennen des Schichtstapels sowie zu dessen Texturierung, Passivierung, Isolierung und Verschaltung eingesetzt. Bei der vorliegenden Erfindung sind daher die folgenden Aspekte hervorzuheben:

  • Effektiv texturierte Solarzellenvorderseite bei geringem Materialabtrag
  • Sehr effiziente Passivierung der Solarzellenfrontseite sowie der offenen Flanken der Schicht durch eine Passivierungs- und Antireflexionsschicht
  • Schädigungsarme Herstellung eines isolierenden Trenngrabens
  • Schädigungsarmes Freilegen des Basismaterials
  • Verschattungsarme Metallkontakte zur Serienverschaltung von Einzelstreifen
  • Rekombinationsarme Metallkontakte durch lokale, punkt- oder streifenförmige Metallkontakte, unter denen die Si-Schicht zur weiteren Verminderung der Rekombination hochdotiert ist.
  • Möglichkeit, integrierte Bypassdioden zu jeder Einzelzelle zu realisieren, die das Modul vor Zerstörung schützen und den Stromertrag optimieren.
The present invention is thus based on a new solar cell architecture of an integrated interconnection of the few μm thin silicon layer stack on the substrate. Thereby techniques become Ablating and separating the layer stack as well as its texturing, passivation, insulation and interconnection used. In the present invention, therefore, the following aspects are to be emphasized:
  • Effectively textured solar cell front with low material removal
  • Very efficient passivation of the solar cell front as well as the open flanks of the layer through a passivation and antireflection layer
  • Low-damage production of an insulating dividing trench
  • Low-damage exposure of the base material
  • Low shading metal contacts for series connection of individual strips
  • Low-recombination metal contacts by local, point or strip-shaped metal contacts, under which the Si layer is highly doped to further reduce the recombination.
  • Possibility of implementing integrated bypass diodes for each individual cell, which protect the module from destruction and optimize the current yield.

Ein weiterer wesentlicher Vorteil des erfindungsgemäßen Konzeptes basiert auf der integrierten Verschaltung der von der Fläche völlig variablen Solarzellen, da man von einer durchgängigen Substratfläche ausgeht und diese völlig frei in Solarzellenfelder einteilt. Durch die spezielle Solarzellen- und Verschaltungsarchitektur können für kristalline Silizium sehr hohe Wirkungsgrade erzielt werden, welche zudem kostengünstig realisiert werden können, da bereits die gesamte Modulfläche prozessiert werden kann.Another essential advantage of the concept according to the invention is based on the integrated interconnection of the solar cells, which are completely variable from the surface, since one starts from a continuous substrate surface and divides it completely into solar cell fields. Due to the special solar cell and interconnection architecture very high efficiencies can be achieved for crystalline silicon, which can also be realized cost-effectively, since already the entire module surface can be processed.

Die vorliegende Erfindung weist dabei gegenüber der aus dem Stand der Technik bekannten Silizium-Wafer-Technologie folgende Vorteile auf:

  • Einsatz sehr geringer Mengen von hochreinem kristallinem Si (nur wenige µm) bei trotzdem sehr hoher mechanischer Stabilität durch das Substrat,
  • Einfache Variation der Zellflächen für das optimale Strom/Spannungsverhältnis im Modul,
  • Großes Kostenreduktionspotential durch höheren Durchsatz und Ausbeute bei der Modulverschaltung sowie Einsparungen von Sekundärmaterialien wie zum Beispiel Glas, Backsheet oder Rahmenmaterialien,
  • Höhere Kundenakzeptanz durch homogeneres Erscheinungsbild.
The present invention has in this case compared to the known from the prior art silicon wafer technology following advantages:
  • Use of very small amounts of high-purity crystalline Si (only a few microns) with still very high mechanical stability through the substrate,
  • Simple variation of the cell areas for the optimal current / voltage ratio in the module,
  • Great cost reduction potential through higher throughput and yield in the module interconnection and savings of secondary materials such as glass, backsheet or frame materials,
  • Higher customer acceptance through more homogeneous appearance.

Vorzugsweise besteht das Substrat aus einem Material ausgewählt aus der Gruppe der Zirkonsilikate, Graphite, Glaskeramiken, Silikatkeramiken, Oxidkeramiken, insbesondere Aluminiumoxid, Titanoxid oder Siliciumoxid, Nitridkeramiken, insbesondere Siliciumnitrid oder Titannitrid, Mulliten, Porzellan, Sintersilicium, Sintermetalle sowie deren Verbunde oder enthält diese im Wesentlichen.Preferably, the substrate consists of a material selected from the group of zirconium silicates, graphites, glass ceramics, silicate ceramics, oxide ceramics, in particular alumina, titania or silica, nitride ceramics, in particular silicon nitride or titanium nitride, mullites, porcelain, sintered silicon, sintered metals and their composites or contains these in the essential.

In den Bereichen des Solarmoduls der isolierenden Trenngräben ist die Schichtstruktur vorzugsweise durch Ablation, besonders bevorzugt mittels Flüssigkeitsstrahl-geführtem Laser (LCP) oder Trockenlaser entfernt.In the regions of the solar module of the insulating separation trenches, the layer structure is preferably removed by ablation, more preferably by means of liquid jet guided laser (LCP) or dry laser.

Eine weitere bevorzugte Variante sieht vor, dass mindestens ein Trenngraben eine Bypassdiode definiert. Diese ermöglichen es im Falle des Defektes einer Solarzelle, dass diese Solarzelle überbrückt werden kann, so dass die Funktion des Solarmoduls im Ganzen nicht eingeschränkt wird. Die Bypassdiode ist dabei vorzugsweise über elektrische Kontakte mit dem Emitter-Kontakt und dem Basis-Kontakt verbunden.A further preferred variant provides that at least one separating trench defines a bypass diode. These make it possible in the case of a defect of a solar cell, that this solar cell can be bridged, so that the function of the solar module is not limited on the whole. The bypass diode is preferably via electrical contacts with the emitter contact and the basic contact.

Erfindungsgemäß weist das Solarmodul im Bereich der Trenngräben eine oder mehrere Flankenisolationen, vorzugsweise zur Verhinderung von Kurzschlüssen, auf.According to the invention, the solar module in the region of the separation trenches one or more edge insulation, preferably to prevent short circuits, on.

Erfindungsgemäß ist vorgesehen, dass die Schichtstruktur zusätzlich eine frontseitige Isolationsschicht aufweist. Erfindungsgemäß besitzt die frontseitige Isolationsschicht auch noch die Funktion einer Passivierungsschicht.According to the invention, it is provided that the layer structure additionally has a front insulation layer. According to the invention, the front-side insulation layer also has the function of a passivation layer.

Die Barriereschicht besteht erfindungsgemäß aus einer nitridischen Schicht, insbesondere Bornitrid oder Siliciumnitrid, oder einer carbidischen Schicht, insbesondere Siliciumcarbid oder Titancarbid, oder Kombinationen hiervon oder enthält diese im Wesentlichen.The barrier layer according to the invention consists of a nitridic layer, in particular boron nitride or silicon nitride, or a carbidic layer, in particular silicon carbide or titanium carbide, or combinations thereof, or contains these substantially.

Erfindungsgemäß ist das Substrat im Ganzen mit der Barriereschicht vollständig verkapselt.According to the invention, the substrate as a whole is completely encapsulated with the barrier layer.

Erfindungsgemäß wird ebenso ein Verfahren zur Herstellung eines Solarmoduls auf Dünnschicht-Basis mit integrierter Verschaltung von mindestens zwei Solarzellen bereitgestellt, das die folgenden Verfahrensschritte aufweist:

  1. a) Bereitstellung
    1. i) eines elektrisch nicht-leitfähigen Substrats; oder
    2. ii) eines elektrisch leitfähigen Substrats (bevorzugt 100-5000 µm Dicke) mit einer elektrisch nicht-leitfähigen Barriereschicht (100 nm bis 100 µm Dicke) mit darauf, bevorzugt mittels Atmosphärendruck-CVD, abgeschiedener und, bevorzugt teilweise mittels Zonenschmelzverfahren (ZMR) rekristallisierter, Schichtstruktur, die mindestens eine kristalline Halbleiterschicht (bevorzugt 0,1-50 µm Dicke) mit einer ersten Dotierung von z.B. 1x1016-5x1019 cm-3 Bor sowie mindestens eine kristalline Halbleiterschicht mit einer zweiten, zur ersten Dotierung entgegengesetzten Dotierung von z.B. 1x1018-2x1020 cm-3 Phosphor enthält,
  2. b) bereichsweise Entfernung der Schichtstruktur vom Substrat zur Erzeugung von isolierenden Trenngräben, vorzugsweise mit einer Breite von 10-1000 µm, und
  3. c) Abscheiden des Emitterkontaktes, vorzugsweise aus Silber, und des Basiskontaktes, vorzugsweise aus Aluminium, und bevorzugt mit einer Dicke von 1-10 µm in zumindest einem Teil der Trenngräben und zumindest auf Bereichen der Schichtstruktur.
The invention likewise provides a method for producing a thin-film-based solar module with integrated interconnection of at least two solar cells, comprising the following method steps:
  1. a) Provision
    1. i) an electrically non-conductive substrate; or
    2. ii) an electrically conductive substrate (preferably 100-5000 μm thickness) with an electrically non-conductive barrier layer (100 nm to 100 μm thickness) with thereon, preferably by means of atmospheric pressure CVD, deposited and preferably partially by zone melting method (ZMR) recrystallized, layer structure having at least one crystalline semiconductor layer (preferably 0.1-50 microns thick) with a first doping of eg 1x10 16 -5x10 19 cm -3 boron and at least one crystalline semiconductor layer having a second, opposite to the first doping doping of eg 1x10 18 -2x10 20 cm -3 phosphorus,
  2. b) area by area removal of the layer structure from the substrate for the production of insulating separation trenches, preferably with a width of 10-1000 microns, and
  3. c) depositing the emitter contact, preferably of silver, and the base contact, preferably of aluminum, and preferably with a thickness of 1-10 microns in at least a portion of the separation trenches and at least on areas of the layer structure.

Erfindungsgemäß erfolgt vor Schritt c) eine Flankenisolation mittels einer gedruckten, aufgedampften, abgeschiedenen oder gewachsenen nitridischen oder carbidischen Schicht.According to the invention, edge isolation by means of a printed, evaporated, deposited or grown nitridic or carbidic layer takes place before step c).

Erfindungsgemäß wird das Substrat im Ganzen mit der Barriereschicht vollständig verkapselt, wobei die Barriereschicht aus einer nitridischen Sicht oder einer carbidischen Schicht oder Kombinationen hiervon besteht oder diese im Wesentlichen enthält, wobei die Barriereschicht eine Dicke von 100 nm bis 100 µm aufweist.According to the invention, the substrate as a whole is completely encapsulated with the barrier layer, wherein the barrier layer consists of or substantially contains a nitridic view or a carbide layer or combinations thereof, the barrier layer having a thickness of 100 nm to 100 μm.

Erfindungsgemäß wird zwischen Schritt b) und c) eine frontseitige Isolationsschicht auf der Halbleiterschicht abgeschieden, die eine Passivierungsschicht darstellt.According to the invention, a front-side insulation layer is deposited on the semiconductor layer between step b) and c), which represents a passivation layer.

Vorzugsweise wird nach Schritt a) eine Texturierung des Substrats mit darauf abgeschiedener Schichtstruktur durchgeführt. Dies wird bevorzugt durch Plasmatextur, Gasphasentextur oder nasschemische Textur umgesetzt.Preferably, after step a), a texturing of the substrate with a layer structure deposited thereon is carried out. This is preferably implemented by plasma texture, gas phase texture or wet-chemical texture.

Eine weitere bevorzugte Ausführungsform sieht vor, dass die Entfernung der Schichtstruktur in Schritt b) mittels Ablation erfolgt. Hierbei sind besonders flüssigkeitsstrahlgeführte Laser-Verfahren (LCP) oder Trockenlaser-Verfahren bevorzugt.A further preferred embodiment provides that the removal of the layer structure in step b) takes place by means of ablation. In this case, liquid-jet-guided laser processes (LCP) or dry laser processes are particularly preferred.

Die Emitterkontakte und Basiskontakte können vorzugsweise mittels Aufdampfen, Drucken oder Sputtern von Metallen mit anschließendem Feuern der Kontakte zur Kontaktherstellung, insbesondere mit einem RTP-Ofen oder durch Laserfeuern erfolgen.The emitter contacts and base contacts can preferably be made by vapor deposition, printing or sputtering of metals with subsequent firing of the contacts for making contact, in particular with an RTP oven or by laser firing.

Erfindungsgemäß wird zwischen Schritt b) und c) eine frontseitige Isolationsschicht auf der Halbleiterschicht abgeschieden.According to the invention, a front-side insulation layer is deposited on the semiconductor layer between step b) and c).

Die Herstellung der mindestens einen frontseitigen Isolationsschicht erfolgt vorzugsweise mittels thermischer Oxidation von Silizium oder durch Abscheidung mittels plasmaverstärkter chemischer Gasphasenabscheidung (PECVD) oder Atomlagenabscheidung (ALD).The preparation of the at least one front-side insulation layer is preferably carried out by means of thermal oxidation of silicon or by deposition by means of plasma-enhanced chemical vapor deposition (PECVD) or atomic layer deposition (ALD).

Vor der Abscheidung der Isolationsschicht kann vorzugsweise mittels eines Laserschnittes eine Unterbrechung der oberen Halbleiterschicht, d.h. der Schicht mit der zweiten Dotierung, erreicht werden. Dieser Laserschnitt wird vorzugsweise mittels Flüssigkeitsstrahl-geführtem Laser (LCP) oder Trockenlaser erzeugt.Before the deposition of the insulating layer, it is possible to achieve an interruption of the upper semiconductor layer, ie the layer with the second doping, preferably by means of a laser cut. This laser cut is preferably produced by means of a liquid jet guided laser (LCP) or dry laser.

Erfindungsgemäß erfolgt vor Schritt c) eine Flankenisolation. Diese Flankenisolation wird erfindungsgemäß mittels einer gedruckten, aufgedampften, abgeschiedenen oder gewachsenen nitridischen oder carbidischen Schicht realisiert.According to the invention, a flank insulation takes place before step c). This flank insulation is realized according to the invention by means of a printed, vapor-deposited, deposited or grown nitridic or carbidic layer.

Eine weitere bevorzugte Ausführungsform sieht vor, dass in mindestens einem Trenngraben eine Bypass-Diode integriert wird, die über elektrische Kontakte mit dem Emitter und der Basis verbunden werden.A further preferred embodiment provides that in at least one separating trench, a bypass diode is integrated, which are connected via electrical contacts to the emitter and the base.

Anhand des nachfolgenden Beispiels und der nachfolgenden Figuren soll der erfindungsgemäße Gegenstand näher erläutert werden, ohne diesen auf die hier gezeigten spezifischen Ausführungsformen einschränken zu wollen.

Fig. 1
zeigt in einer schematischen Schnittdarstellung einen ersten Gegenstand.
Fig. 2
zeigt in einer schematischen Schnittdarstellung einen erfindungsgemäßen Gegenstand.
Fig. 3
zeigt eine Draufsicht eines erfindungsgemäßen Solarmoduls.
Reference to the following example and the following figures, the subject invention is to be explained in more detail, without wishing to limit this to the specific embodiments shown here.
Fig. 1
shows a schematic sectional view of a first object.
Fig. 2
shows a schematic sectional view of an article according to the invention.
Fig. 3
shows a plan view of a solar module according to the invention.

In Fig. 1 ist ein erstes Solarmodul auf Dünnschicht-Basis mit integrierter Verschaltung von zwei Solarzellen im Querschnitt dargestellt. Hierin ist ein Substrat 1, das sowohl elektrisch leitend als auch elektrisch nicht-leitend sein kann, vollständig von einer Verkapselungsschicht 2, die im vorliegenden Fall elektrisch nicht-leitend ist, umgeben. Auf der Verkapselungsschicht 2 ist eine Schichtstruktur abgeschieden, die aus einer hochdotierten Schicht 3, einer normal dotierten Schicht 3' und einer zur Schicht 3 entgegengesetzt hoch dotierten Schicht 4 aus kristallinem Silizium abgeschieden wird. Gleichzeitig ist die Schichtstruktur unterbrochen durch einen Trenngraben 5, der durch Ablation entfernt wurde. Im Trenngraben 5 sowie bereichsweise auf der Schichtstruktur sind der Emitterkontakt 7 und der Basiskontakt 8 abgeschieden. Weiterhin ist frontseitig zur Schichtstruktur noch eine Isolationsschicht bzw. Passivierungsschicht 6 abgeschieden.In Fig. 1 is a first solar module based on thin film with integrated interconnection of two solar cells shown in cross section. Herein, a substrate 1, which may be both electrically conductive and electrically non-conductive, completely surrounded by an encapsulation layer 2, which is electrically non-conductive in the present case. On the encapsulation layer 2, a layer structure is deposited, which is deposited from a highly doped layer 3, a normal doped layer 3 'and a layer 4 of opposite highly doped layer 4 of crystalline silicon. At the same time, the layer structure is interrupted by a separation trench 5 which has been removed by ablation. In the separation trench 5 and partially on the layer structure of the emitter contact 7 and the base contact 8 are deposited. Furthermore, an insulating layer or passivation layer 6 is deposited on the front side of the layer structure.

In Fig. 2 ist eine Variante des erfindungsgemäßen Solarmoduls auf Dünnschicht-Basis dargestellt. Der Aufbau von Substrat und Schichtstruktur entspricht hier der Figur 1. Zusätzlich ist in Fig. 2 noch eine Unterbrechung der Schichtstruktur mittels eines Laserschnitts 5' dargestellt. Ebenso zusätzlich weist die linke Solarzelle am Rand des Trenngrabens eine Flankenisolation 6' auf. Der Basiskontakt 8 zeigt zusätzlich einen lasergefeuerten Kontakt 8'.In Fig. 2 a variant of the solar module according to the invention is shown on a thin film basis. The structure of substrate and layer structure corresponds here to the FIG. 1 , Additionally is in Fig. 2 nor an interruption of the layer structure by means of a laser section 5 'shown. Likewise, in addition, the left solar cell at the edge of the separation trench on a flank insulation 6 '. The base contact 8 additionally shows a laser-fired contact 8 '.

In Fig. 3 ist eine Draufsicht eines erfindungsgemäßen Solarmoduls dargestellt. Hier sind die Basis 11 und der Emitter 12 der einzelnen Solarzellen dargestellt. Ebenso zeigt die Abbildung Metallfinger zur Emitterkontaktierung 13. Der Basiskontakt 14 weist lasergefeuerte Kontakte 14' auf. Zusätzlich ist eine Bypassdiode 15 integriert, die über die Kontakte 16' und 16" mit den Basiskontakten 14 verbunden ist.In Fig. 3 is a plan view of a solar module according to the invention shown. Here, the base 11 and the emitter 12 of the individual solar cells are shown. The figure also shows metal fingers for emitter contact 13. The base contact 14 has laser-fired contacts 14 '. In addition, a bypass diode 15 is integrated, which is connected via the contacts 16 'and 16 "with the base contacts 14.

Beispielexample

Im Folgenden wird eine mögliche Prozessfolge zur Herstellung eines integriert verschalteten kristallinen Si-Dünnschichtmoduls mit einigen Zusatzoptionen dargestellt:

  1. 1. Textur der Silicium Oberfläche mittels Plasmatextur
  2. 2. c-Si Ablation des gesamten Si-Stapels (14-50 µm) zur Zelltrennung mit geringer Oberflächenschädigung mittels LCP
  3. 3. Gezielte Ablation (0.1 bis 40 µm tief) des Emitters auf einer Breite von etwa 10-500 µm mit geringer Schädigung mittels LCP-Laser
  4. 4. Laserschnitt mittels LCP-Laser
  5. 5. Passivieren aller Silicium Oberflächen thermische Oxidation
  6. 6. Flankenisolation mittels oxidischer Inkjetpaste
  7. 7. Kontaktfinger am Emitter durch Aufdampfen von Metallen
  8. 8. Basiskontakt durch Aufdampfen von Metallen
  9. 9. Feuern der Kontakte im RTP Ofen
  10. 10. Laser-gefeuerte Kontakte am Basiskontakt Alternativ kann der Schritt 1 nach dem Schritt 3 durchgeführt werden, mit dem Vorteil, dass die Schritte 2 und 3 durch Nachätzen eventuell verbliebener Reste unterstützt werden können. Falls der Schichtaufbau bereits texturiert ist, oder keine Textur benötigt wird, weil z.B. ein effizienter diffuser Rückseitenspiegel auf Schicht 1 oder 2 eingebaut wurde, kann Schritt 1 auch ersatzlos entfallen.
The following is a possible process sequence for the production of an integrated interconnected crystalline Si thin-film module with some additional options:
  1. 1. Texture of the silicon surface by plasma texture
  2. 2. c-Si Ablation of the entire Si stack (14-50 μm) for cell separation with low surface damage by means of LCP
  3. 3. Targeted ablation (0.1 to 40 μm deep) of the emitter over a width of about 10-500 μm with little damage by means of LCP laser
  4. 4. Laser cutting by means of LCP laser
  5. 5. Passivate all silicon surfaces thermal oxidation
  6. 6. Flank insulation by means of oxidic inkjet paste
  7. 7. Contact fingers on the emitter by vapor deposition of metals
  8. 8. Basic contact by vapor deposition of metals
  9. 9. Fire the contacts in the RTP oven
  10. 10. Laser-fired contacts on the base contact Alternatively, step 1 may be performed after step 3, with the advantage that steps 2 and 3 can be assisted by copying any residuals left over. If the layer structure is already textured, or no texture is needed, for example, because an efficient diffuse back mirror was installed on layer 1 or 2, step 1 can also be omitted without replacement.

Claims (11)

  1. Thin-film solar module with integrated wiring of at least two solar cells comprising
    a) an electrically non-conductive substrate (1); or
    b) an electrically conductive substrate (1);
    having an electrically non-conductive barrier layer (2) on which a layer structure, which comprises at least one crystalline semiconductor layer (3) with a first doping and also at least one crystalline semiconductor layer (4) with a second doping opposite the first doping, is deposited,
    the solar module having insulating separating channels (5), in which the layer structure is removed, between the individual solar cells and, at least in a part of the separating channels (5) and at least on regions of the layer structure, an emitter contact (7) and a base contact (8) being deposited by means of vapour-phase deposition, injection, sputtering, printing or evaporation coating methods, characterised in that the separating channels have an edge insulation (6') in the form of a printed, evaporation-coated, deposited or grown nitride or carbide layer,
    the substrate being completely encapsulated in its entirety by the barrier layer,
    the barrier layer consisting of a nitride layer or a carbide layer or combinations hereof or essentially comprising these,
    the barrier layer having a thickness of 100 nm to 100 µm, and
    the layer structure having a front-side insulation layer (6) which represents a passivation layer.
  2. Solar module according to claim 1, characterised in that the substrate consists of a material selected from the group of zirconium silicates, graphites, glass ceramics, silicate ceramics, oxide ceramics, in particular aluminium oxide, titanium oxide or silicon oxide, nitride ceramics, in particular silicon nitride or titanium nitride, mullites, porcelain, sintered silicon, sintered metals and also composites thereof or essentially comprises these and/or the barrier layer consists of boron nitride or silicon nitride, silicon carbide or titanium carbide, or combinations hereof or essentially comprises these.
  3. Solar module according to one of the preceding claims, characterised in that at least one further separating channel (5) defines an integrated bypass diode (15) which are connected via electrical contacts (11, 12) to the emitter contact (7) and to the base contact (8).
  4. Solar module according to one of the preceding claims, characterised in that the electrically non-conductive substrate (1) is completely encapsulated by the barrier layer (2).
  5. Method for the production of a thin-film solar module having integrated wiring of at least two solar cells, with the following steps:
    a) providing an
    i) electrically non-conductive substrate (1); or
    ii) an electrically conductive substrate (1);
    having an electrically non-conductive barrier layer (2) with a layer structure deposited thereon, which comprises at least one crystalline semiconductor layer (3) with a first doping and also at least one crystalline semiconductor layer (4) with a second doping opposite the first doping,
    b) removing, in regions, the layer structure from the substrate in order to produce insulating separating channels, and
    c) depositing the emitter contact (7) and the base contact (8) in at least one part of the separating channels and at least on regions of the layer structure,
    characterised in that, before step c), an edge insulation is effected,
    in that the substrate is completely encapsulated in its entirety by the barrier layer,
    in that the barrier layer consists of a nitride layer or a carbide layer or combinations hereof or essentially comprises these,
    in that the barrier layer has a thickness of 100 nm to 100 µm,
    in that, between step b) and c), a front-side insulation layer (6), which represents a passivation layer, is deposited on the semiconductor layer (4) and
    in that, before step c), the edge insulation is effected by means of a printed, evaporation-coated, deposited or grown nitride or carbide layer.
  6. Method according to claim 5, characterised in that, after step a), texturing of the substrate (1) is effected with a layer structure deposited thereon, in particular a plasma texture, a vapour-phase texture or a wet-chemical texture.
  7. Method according to one of the claims 5 or 6, characterised in that, in step b), removal of the layer structure is effected by means of ablation, in particular by means of liquid-jet-guided laser (LCP) or dry laser.
  8. Method according to one of the claims 5 to 7, characterised in that production of the at least one front-side insulation layer (6) is effected by means of thermal oxidation of silicon or by deposition by means of plasma-enhanced chemical vapour-phase deposition (PECVD) or atomic layer deposition (ALD).
  9. Method according to one of the claims 5 to 8, characterised in that production of the emitter contact (7) and of the base contact (8) is effected by means of evaporation coating, printing or sputtering of metals with subsequent firing of the contacts for the contact production, in particular with an RTP furnace or by laser firing.
  10. Method according to one of the claims 5 to 9, characterised in that, after step b), a laser cut is effected by means of liquid-jet-guided laser (LCP) or dry laser.
  11. Method according to one of the claims 5 to 10 for the production of a solar module according to one of the claims 1 to 4.
EP12731322.9A 2011-06-07 2012-06-04 Thin film solar module having integrated interconnections and method for producing the same Not-in-force EP2718979B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102011103539A DE102011103539A1 (en) 2011-06-07 2011-06-07 Solar module with integrated interconnection and method for its production
PCT/EP2012/060513 WO2012168191A1 (en) 2011-06-07 2012-06-04 Solar module having integrated circuitry and method for producing same

Publications (2)

Publication Number Publication Date
EP2718979A1 EP2718979A1 (en) 2014-04-16
EP2718979B1 true EP2718979B1 (en) 2019-03-27

Family

ID=46456502

Family Applications (1)

Application Number Title Priority Date Filing Date
EP12731322.9A Not-in-force EP2718979B1 (en) 2011-06-07 2012-06-04 Thin film solar module having integrated interconnections and method for producing the same

Country Status (4)

Country Link
EP (1) EP2718979B1 (en)
DE (1) DE102011103539A1 (en)
ES (1) ES2732098T3 (en)
WO (1) WO2012168191A1 (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5639314A (en) * 1993-06-29 1997-06-17 Sanyo Electric Co., Ltd. Photovoltaic device including plural interconnected photoelectric cells, and method of making the same
DE19715138A1 (en) * 1997-04-13 1998-10-22 Fraunhofer Ges Forschung Method for producing an arrangement of individual solar cells connected in series or series
JP2002141536A (en) * 2000-08-23 2002-05-17 Nisshin Steel Co Ltd Thin film polycrystalline silicon solar cell substrate superior in heat resistance and manufacturing method thereof
US20070295394A1 (en) * 2006-06-27 2007-12-27 Biosolar, Inc. Method for building thin film flexible solar cells on bio-based plastic substrates
JP2011077246A (en) * 2009-09-30 2011-04-14 Fujifilm Corp Clad substrate, photoelectric conversion device, thin-film solar cell module, method of manufacturing the clad substrate, and method of manufacturing the thin-film solar cell module

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3727826A1 (en) * 1987-08-20 1989-03-02 Siemens Ag SERIES-CONNECTED THIN-LAYER SOLAR MODULE MADE OF CRYSTAL SILICON
JP2005101384A (en) * 2003-09-26 2005-04-14 Sanyo Electric Co Ltd Photovoltaic device and its manufacturing method
DE102004055225B4 (en) * 2004-11-16 2014-07-31 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Arrangement with solar cell and integrated bypass diode
DE102007011403A1 (en) 2007-03-08 2008-09-11 Fraunhofer-Gesellschaft zur Förderung der angewandten Forschung e.V. Front side series connected solar module
US7867812B2 (en) * 2008-07-11 2011-01-11 Duy-Phach Vu Method for production of thin semiconductor solar cells and integrated circuits
DE102008060404A1 (en) * 2008-07-30 2010-02-11 Helmholtz-Zentrum Berlin Für Materialien Und Energie Gmbh Single-sided contacted thin-film solar module with an inner contact layer
KR101627217B1 (en) * 2009-03-25 2016-06-03 엘지전자 주식회사 Sollar Cell And Fabrication Method Thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5639314A (en) * 1993-06-29 1997-06-17 Sanyo Electric Co., Ltd. Photovoltaic device including plural interconnected photoelectric cells, and method of making the same
DE19715138A1 (en) * 1997-04-13 1998-10-22 Fraunhofer Ges Forschung Method for producing an arrangement of individual solar cells connected in series or series
JP2002141536A (en) * 2000-08-23 2002-05-17 Nisshin Steel Co Ltd Thin film polycrystalline silicon solar cell substrate superior in heat resistance and manufacturing method thereof
US20070295394A1 (en) * 2006-06-27 2007-12-27 Biosolar, Inc. Method for building thin film flexible solar cells on bio-based plastic substrates
JP2011077246A (en) * 2009-09-30 2011-04-14 Fujifilm Corp Clad substrate, photoelectric conversion device, thin-film solar cell module, method of manufacturing the clad substrate, and method of manufacturing the thin-film solar cell module

Also Published As

Publication number Publication date
ES2732098T3 (en) 2019-11-20
EP2718979A1 (en) 2014-04-16
WO2012168191A1 (en) 2012-12-13
DE102011103539A1 (en) 2012-12-13

Similar Documents

Publication Publication Date Title
EP0905794B1 (en) Solar cell and method of fabrication
EP2168177B1 (en) Fabrication method of a thin-film solar cell module
EP1062689B1 (en) Solar cell arrangement and method of making a solar cell arrangement
EP2033228B1 (en) Single-sided contact solar cell with plated-through holes and method for producing it
EP0548863B1 (en) Method of fabricating a solar cell and solar cell
EP1421629B1 (en) Solar cell and method for production thereof
EP1279196A1 (en) Method for producing a solar cell, and solar cell produced according to said method
DE112014001192B4 (en) Process for producing photoactive devices with small bandgap active layers designed for improved efficiency
DE102011050089A1 (en) Method for producing electrical contacts on a solar cell, solar cell and method for producing a back-side contact of a solar cell
DE102011075352A1 (en) A method of back contacting a silicon solar cell and silicon solar cell with such backside contacting
WO2018041301A1 (en) Photovoltaic module with stacked solar cells connected up in series in integrated fashion, and method for the manufacture thereof
EP2718979B1 (en) Thin film solar module having integrated interconnections and method for producing the same
WO2011141139A2 (en) Method for producing a solar cell that can be contacted on one side from a silicon semiconductor substrate
WO2010092051A2 (en) Integral process, from wafer production to module manufacturing, for producing wafers, solar cells, and solar modules
EP2862203A2 (en) Method and production system for producing a photovoltaic module, and photovoltaic module
WO2014128032A1 (en) Semiconductor component, more particularly solar cell, and method for producing a metallic contact-making structure of a semiconductor component
DE4143084A1 (en) MIS, pn junction, thin film solar cell mfr.
EP2352171A1 (en) Solar cell configuration and thin film solar module and method for producing same
DE102011015283B4 (en) Production of a Semiconductor Device by Laser-Assisted Bonding and Semiconductor Device Manufactured Therewith
EP2442361A2 (en) Method for manufacturing interconnects in a thin film photovoltaic module and thin film photovoltaic module
DE102016110965B4 (en) Front and back side semiconductor device and method of making the same
DE102011052261B4 (en) Process for producing a solar cell, solar cell and solar module
EP2442360A2 (en) Method for manufacturing interconnects in a thin film photovoltaic module and thin film photovoltaic module
EP2831914B1 (en) Method for producing structured thin-layer photovoltaics
DE102013219844A1 (en) Method and device for producing a semiconductor component, in particular a photovoltaic cell

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20131203

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

DAX Request for extension of the european patent (deleted)
RIC1 Information provided on ipc code assigned before grant

Ipc: H01L 31/0465 20140101ALI20150708BHEP

Ipc: H01L 31/0392 20060101AFI20150708BHEP

Ipc: H01L 31/18 20060101ALI20150708BHEP

Ipc: H01L 27/142 20140101ALI20150708BHEP

17Q First examination report despatched

Effective date: 20151030

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: EXAMINATION IS IN PROGRESS

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: GRANT OF PATENT IS INTENDED

INTG Intention to grant announced

Effective date: 20181105

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE PATENT HAS BEEN GRANTED

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

Free format text: NOT ENGLISH

REG Reference to a national code

Ref country code: CH

Ref legal event code: EP

REG Reference to a national code

Ref country code: DE

Ref legal event code: R096

Ref document number: 502012014503

Country of ref document: DE

REG Reference to a national code

Ref country code: AT

Ref legal event code: REF

Ref document number: 1114062

Country of ref document: AT

Kind code of ref document: T

Effective date: 20190415

REG Reference to a national code

Ref country code: IE

Ref legal event code: FG4D

Free format text: LANGUAGE OF EP DOCUMENT: GERMAN

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190327

Ref country code: FI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190327

Ref country code: NO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190627

Ref country code: SE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190327

REG Reference to a national code

Ref country code: NL

Ref legal event code: MP

Effective date: 20190327

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: NL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190327

Ref country code: GR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190628

Ref country code: HR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190327

Ref country code: LV

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190327

Ref country code: BG

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190627

Ref country code: RS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190327

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: PT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190727

Ref country code: AL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190327

Ref country code: EE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190327

Ref country code: SK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190327

Ref country code: RO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190327

Ref country code: CZ

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190327

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: IT

Payment date: 20190709

Year of fee payment: 8

Ref country code: GB

Payment date: 20190624

Year of fee payment: 8

REG Reference to a national code

Ref country code: ES

Ref legal event code: FG2A

Ref document number: 2732098

Country of ref document: ES

Kind code of ref document: T3

Effective date: 20191120

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: PL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190327

Ref country code: SM

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190327

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190727

REG Reference to a national code

Ref country code: DE

Ref legal event code: R097

Ref document number: 502012014503

Country of ref document: DE

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190327

Ref country code: MC

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190327

REG Reference to a national code

Ref country code: CH

Ref legal event code: PL

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190327

26N No opposition filed

Effective date: 20200103

REG Reference to a national code

Ref country code: BE

Ref legal event code: MM

Effective date: 20190630

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: TR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190327

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20190604

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: BE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20190630

Ref country code: CH

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20190630

Ref country code: LU

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20190604

Ref country code: LI

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20190630

REG Reference to a national code

Ref country code: DE

Ref legal event code: R084

Ref document number: 502012014503

Country of ref document: DE

REG Reference to a national code

Ref country code: AT

Ref legal event code: MM01

Ref document number: 1114062

Country of ref document: AT

Kind code of ref document: T

Effective date: 20190604

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: AT

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20190604

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20200604

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20200604

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: CY

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190327

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190327

Ref country code: HU

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT; INVALID AB INITIO

Effective date: 20120604

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20210621

Year of fee payment: 10

Ref country code: DE

Payment date: 20210621

Year of fee payment: 10

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20200604

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: ES

Payment date: 20210722

Year of fee payment: 10

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20190327

REG Reference to a national code

Ref country code: DE

Ref legal event code: R119

Ref document number: 502012014503

Country of ref document: DE

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20220630

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20230103

REG Reference to a national code

Ref country code: ES

Ref legal event code: FD2A

Effective date: 20230802

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: ES

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20220605