DE102016110965B4 - Front and back side semiconductor device and method of making the same - Google Patents

Abstract

Semiconductor device having front and rear electrodes (2), comprising on a substrate (1) at least one contact layer for charge carriers of a conductivity type as the rear electrode (2), on which at least one active semiconductor layer (7) and a front-side electrode are arranged, and at least one intermediate layer (3, 5) is arranged between the rear electrode (2) and the at least one active semiconductor layer (7), characterized in that between the rear electrode (2) and the at least one active semiconductor layer (7) at least one first ( 3) and a second (5) electrically insulating dielectric interlayer and arranged between them at least one electrically conductive layer (4) are arranged and wherein the two electrically insulating dielectric layers (3, 5) contact openings (6) and wherein the contact openings (6 ) of the second electrically insulating dielectric layer (5) ang are arranged to those of the first electrically insulating dielectric layer (3), so that diffusion of impurities from the backside electrode (2) into the active semiconductor layer (7) is reduced and so that the backside electrode (2) is formed over the entire area and the at least one active semiconductor layer (7) are electrically conductively connected, and wherein the electrically conductive layer (4) is formed of a higher doped semiconductor than the at least one active semiconductor layer (7) and the doping is between 1 × 10 cm and 1 × 10 cm.

Description

The invention relates to a semiconductor device with front and rear electrode and a method for its preparation.

Semiconductor devices are electronic devices made of semiconductor materials and / or structures made of various semiconductor materials, i. Materials of different conductivity type, as well as metals and insulators exist. Their mode of action or function is based on the behavior, in particular the movement, of charge carriers. According to the state of the art, there are a large number of semiconductor components with different functions and thus with different layer arrangements having on a substrate at least one contact layer for charge carriers of a conductivity type, on which one or more active semiconductor layers and a further contact layer for charge carriers of the opposite conductivity type are arranged are.

Depending on the layer arrangement in a semiconductor device and according to its function, the person skilled in the art will arrange contacts on the front and back of the semiconductor device or contact the semiconductor device on one side, i. position both contacts on the front or back. In order to realize a low-defect semiconductor layer, the contacts applied during the further processing of the semiconductor component should not entail undesired diffusion of impurities from the contact material or from the substrate. Depending on the function of the semiconductor device, the contacts should meet further requirements, for example, they should ensure a good optical reflection and survive the possibly necessary in the further processing of the semiconductor device high temperatures. For the realization of these objectives and for the improvement of further selected properties of the semiconductor device, functional layers, adjacent to the contact layers, are also known in the general state of the art.

In the following, some known prior art contact systems for different semiconductor device arrangements will be described.

Both sides contacted semiconductor devices can be made of p-type or n-type conductive silicon. Often, they are realized as a semiconductor diode which, when at least one of the contacts is translucent, as a photodiode (light detector) or as a solar cell (for energy conversion) is used. The silicon is usually contacted on both sides in the form of a crystalline wafer, but can also, as in this invention, be applied as a silicon layer on a substrate.

One possibility for rear-side contacting for silicon wafer solar cells contacted on both sides has been realized by Fraunhofer ISE with the TOPCon (Tunnel Oxide Passivated Contact) technology (see for example http://www.bine.info/themen/erneuerbareenergien/photovoltaik/news/weltrekord -first-sided-contacted-silicon-solar cells / retrieved on 09.06.2016 or Solar Energy Materials & Solar Cells 131 (2014) 100-104). The generated backside contact is selective and passivates the silicon layer. The whole-area passivation layer is very thin (1 to 2 nm), so that the charge carriers can tunnel through it. A thin layer of highly doped silicon also applied over the entire surface of the passivation layer, in combination with the underlying layers, enables a lossless outflow of the current from the solar cell.

However, most of the prior art publications follow the path of structuring one or more superimposed layers for improved contacting of the respective semiconductor device.

In WO 2013/067 998 A1 [0008] In the prior art, a surface-passivated backside semiconductor wafer solar cell having a front side electrode pattern is provided and the back surface of the semiconductor wafer is surface-passivated with a layer. On the passivation layer is deposited a backside metal electrode structure containing sintered metal particles. Via a multiplicity of local contact regions, which are realized through openings of the passivation layer, which may also be designed as a thin-film stack, the back-side metal electrode structure, which is not applied over the whole area, contacts the semiconductor wafer. The openings occupy an area of less than 5% of the rear surface.

In the semiconductor device used in GB 2 471 732 A and also relates to a wafer-based solar cell contacted on both sides, a first dielectric layer of silicon dioxide (SiO ₂ ) and a second dielectric layer of silicon nitride (SiN _x ) are arranged on the wafer back side. The wafer has opposing conductivities produced on its front and back surfaces by doping. On the second dielectric layer, a sacrificial layer is applied and thereon a metal layer which forms the backside contact. Via openings in the contact layer and the two dielectric layers, contact is made with the back surface of defined conductivity of the wafer. During a temperature treatment of> 577 ° C, the metal electrode layer reacts and is melted together with the sacrificial layer, forming an alloy. This alloy ensures a very good adhesion between the metal layer and the sacrificial layer on the one hand and on the other hand between the sacrificial layer and the second dielectric layer.

In DE 38 15 512 A1 is described on both sides contacted solar cell with reduced recombination rate of the charge carriers. For this purpose, an insulation layer provided with openings is arranged over the entire area on the rear side of the positive-conducting (p-type) semiconductor body and the contact layer. Starting from the openings, highly doped p ⁺ regions are formed in the semiconductor body. The openings are filled with contact material and form an ohmic contact with the semiconductor body.

At the in US 2015/0 214 391 A1 In the illustrated two-sided contacted solar cell, a passivation film is disposed on the back surface of the p-type Si substrate having a plurality of openings. The passivation film is formed of alumina (Al ₂ O ₃ ) or niobium dioxide (NbO ₂ ). In addition, a layer doped with a group III element, for example aluminum or boron, as BSF layer (back surface field) is optionally arranged between the passivation film and the back surface of the Si substrate. The rear electrode is connected to the back surface of the Si substrate through the plurality of punctiform or line-shaped openings.

In Solar Energy Materials & Solar Cells 117 (2013) 505-511 describes a back contact structure for CIGS (copper indium gallium diselenide) thin film solar cells. By combining the passivation of the back surface of the semiconductor layer with nanometer local point contacts, the back contact area is to be reduced. The open circuit voltage could thus be significantly improved compared to a non-passivated back surface of the semiconductor layer.

In Solar Energy 77 (2004) 857-863, MA Green et al. Describe a point contact scheme for a single-sidedly contacted silicon-based thin-film solar cell in superstrate configuration. Although the one-sided contacted layer arrangement can be produced with methods known from thin-film technology, it is relatively complicated, since the contacts of the two charge carrier types have to be separated, interleaved and manufactured by suitable structuring methods. The method for producing a single-sided contacted thin-film solar cell assembly also includes a high-temperature step of crystallizing an amorphous silicon layer into a polycrystalline one.

At the in US 4,395,583 A described arrangement for an optimized back contact, the p ⁺ layer of a pp ⁺ junction is provided with holes. On this p ⁺ layer is a - also provided with microholes - Metalloxidschicht arranged. Aluminum is deposited on this layer to form electrical contacts with the p ⁺ layer.

A solar cell having a transparent front electrode and a window layer, an absorber layer and a backside electrode on a conductive substrate is shown in FIG US 2009/0 301 543 A1 disclosed. The solar cell also has a plurality of contact holes in the substrate, which may also be electrically separated from the substrate by an insulating layer. The contact holes may also serve to contact a front electrode of a cell with the back electrode of an adjacent cell.

US 2007/0 295 399 A1 discloses a solar cell in which an absorber layer is provided on both sides with a passivation layer. In the back passivation layer, a first contact is formed by first point contacts having a conductivity type opposite to the absorber layer. In addition to this, also by point contacts, a second contact is formed, which is electrically isolated from the first contact. The point contacts are formed by metal-filled holes in the passivation layer.

Staggered contact gratings embedded between PN junctions of a multiple solar cell disclosed US 2012/0 060 908 A1 , The contact grid thereby form a combination of insulating and serial electrical connection between the adjacent junctions. They are designed as point contacts in conjunction with conductive layers.

The object of the invention is now to provide a further solution for a semiconductor device contacted on both sides with a layer arrangement which is improved in comparison with the prior art for the back contact, whereby the surfaces of the active layers of the semiconductor device are passivated and at the same time ensures good optical properties become. In addition, the back contact for the processing of certain semiconductor devices to be at least 1414 ° C temperature stable. Furthermore, a corresponding method for producing such a semiconductor device is to be specified.

The object is solved by the features of independent claims 1 and 11.

In this case, in a semiconductor device according to the prior art, having on a substrate at least one contact layer for charge carriers of a conductivity type as the backside electrode on which at least one active semiconductor layer and a front-side electrode are arranged, and between the back electrode and the at least one active Semiconductor layer is arranged at least one intermediate layer, according to the invention at least two electrically insulating dielectric intermediate layers and disposed therebetween applied at least one electrically conductive layer, wherein the electrically insulating dielectric layers staggered contact openings have, so that the rear electrode, which is formed over the entire surface, and the at least one active semiconductor layer are electrically conductively connected.

Such a layer system prevents the diffusion of impurities from, for example, the backside electrode into the at least one active semiconductor layer and passivates the back surface of the at least one active semiconductor layer while ensuring good optical properties through its properties as a Bragg reflector. The formation of a rear side field in the layer arrangement also improves the electrical back contact. The use of such a layer system is possible for semiconductor components of various functions, in particular in those in which the properties mentioned are to be ensured.

With regard to the electrically conductive layer arranged between the two dielectric layers, provision is made for them to be formed from a semiconductor layer which has a higher doping than for the at least one active semiconductor layer, the doping being between 1 × 10 ¹⁹ cm ^-3 and 1 × 10 ²¹ cm ^-3 and the layer thickness of the conductive layer is between 50 nm and 100 nm. The highly doped semiconductor layer contributes to the quality improvement of the back contact layer.

The following embodiments of the invention relate to the individual layers in the semiconductor device.

It is thus provided that the at least one active semiconductor layer is formed from crystalline silicon. Preferred for this purpose is an Si layer applied, for example, by means of PECVD or electrode beam evaporation and subsequently produced by liquid-phase crystallization. The thickness of the at least one active semiconductor layer is between 5 μm and 40 μm.

In other embodiments, the substrate is made of glass and the back electrode is formed of a refractory metal or the substrate and the back electrode are replaced by a metal foil.

For the rear electrode is provided to form these from a refractory metal, preferably molybdenum. Their layer thickness should be between 100 nm and 1 μm.

Further embodiments relate to the at least two dielectric layers which are formed from SiOx or SiN _x or silicon oxynitride (SiO _x N _y ) or Al ₂ O ₃ or silicon carbide (SiC _x ). The layer thickness of the at least two dielectric layers is in each case between 50 nm and 400 nm.

In embodiments - concerning the mutually offset contact openings in the at least two dielectric layers - is provided to form them point or line-shaped. The contact openings have a typical distance from one another of 0.5 .mu.m to 500 .mu.m and correspondingly a diameter of 50 nm to 50 .mu.m and a width of 50 nm to 50 .mu.m.

Furthermore, in one embodiment, the surface facing away from the substrate of the at least one active semiconductor layer is textured. This serves for the improved coupling of light into the active semiconductor layer.

With the features of the invention, it is particularly advantageous to form a silicon thin-film solar cell in substrate configuration contacted on both sides. This silicon thin film solar cell may then comprise, for example, an active semiconductor layer of liquid phase crystallized silicon of a conductivity type constituting the absorber layer and a second active semiconductor layer of silicon having a conductivity type opposite to the absorber layer forming the emitter layer. The backside electrode is a high temperature resistant conductive layer and the front side electrode is formed of a transparent conductive material. To improve the light capture, the surface of the absorber layer facing away from the substrate may be textured.

For multi-junction solar cells as well, the layer arrangement described can be made of all-over formed back electrode and two electrically insulating dielectric intermediate layers, between which at least one electrically conductive layer is arranged, wherein the electrically insulating dielectric layers have mutually staggered contact openings. The bottom cell is a Si-based thin-film cell, the top cell can then For example, again be a silicon solar cell, but also a perovskite solar cell.

The method for producing a semiconductor component according to the invention comprises the following method steps: application of a back-side full-area electrode layer to a substrate, then producing a first electrically insulating dielectric layer with contact openings to the underlying back electrode, applying an electrically conductive layer to the first electrically insulating dielectric layer, then producing a second electrically insulating dielectric layer having contact openings to the underlying conductive layer, wherein the contact openings in the two dielectric layers are staggered, then producing at least one active semiconductor layer and finally applying a front-side electrode.

In this case, the application of the full-surface back electrode layer by means of PVD (physical vapor deposition - physical vapor deposition) take place. The first dielectric layer is deposited thereon by PECVD (Plasma Enhanced Chemical Vapor Deposition) or again by PVD at a deposition temperature in the range of 200 ° C to 600 ° C. As provided in embodiments of the invention, the material used for the first dielectric layer is SiOx or SiN _x or SiO _x N _y or Al ₂ O ₃ or SiCx and deposited to a thickness between 50 nm and 400 nm. The following contact opening, ie the introduction of punctiform or linear openings into the first dielectric layer, can take place by means of laser, photo or nanoimprint lithography or by deposition of particles on the surface of the rear electrode layer, ie before the application of the dielectric layer. But also printing methods such as screen printing and inkjet printing can be used to produce the contact openings. As provided in further embodiments, the punctiform contact openings are produced with a diameter of 50 nm to 50 microns and a distance from each other of 0.5 microns to 500 microns and the line-shaped contact openings with a width of 50 nm to 50 microns and a distance from each other 0.5 μm to 500 μm. Thereafter, the deposition of the electrically conductive layer by means of PECVD or electron beam evaporation at deposition temperatures between 200 ° C and 600 ° C, for which in particular a higher doped semiconductor material (eg silicon) is used as for the at least one active semiconductor layer, wherein the doping is between 1 × 10 ¹⁹ cm ^-3 and 1 × 10 ²¹ cm ^-3 and the layer thickness of this conductive layer is between 50 nm and 100 nm. The method steps for applying the second dielectric layer and producing the contact openings in this layer, which are offset from the contact openings of the first dielectric layer, are analogous to the method steps described for the first dielectric layer. Now, the application of a semiconductor layer takes place. With regard to the semiconductor layer, it is provided in embodiments that, for the deposition of the semiconductor layer, an Si layer with a thickness of 5 μm to 40 μm is first applied by means of PECVD or electron beam evaporation and then crystallized. The crystallization of the silicon layer is carried out by liquid phase crystallization by means of laser beam in air or in vacuum or in an inert gas or by means of electron beam in a vacuum. For this reason, therefore, high-temperature resistant layers between the substrate and the semiconductor layer are necessary. On the second semiconductor layer, an emitter layer having a conductivity type opposite to the first active semiconductor layer, a front-side electrode layer made of a transparent conductive oxide, for example indium tin oxide or zinc oxide, is deposited by PVD or evaporation. In addition, a grid structure can also be applied as a further component of the front-side electrode.

In one embodiment, it is provided to expose the back-side electrode after the application of the front-side electrode.

With the method according to the invention, it is now also possible to contact a semiconductor component based on liquid-phase crystallized silicon as an active semiconductor layer on two sides, which makes the method easier to handle and less expensive. The staggered positioning of the openings in the two dielectric layers requires less accuracy in introducing the openings, the materials used also allow process steps at high temperatures.

The invention will be described in an embodiment with reference to FIGS.

• 1 eine schematische Darstellung einer erfindungsgemäßen Silizium-Dünnschicht-Solarzelle in Substratkonfiguration;
• 2 eine Draufsicht auf eine mögliche Verteilung von Punktkontakten in den beiden dielektrischen Schichten;
• 3 eine Draufsicht auf eine mögliche Verteilung von linienförmigen Kontakten in den beiden dielektrischen Schichten.

Show

• 1 a schematic representation of a silicon thin-film solar cell according to the invention in substrate configuration;
• 2 a plan view of a possible distribution of point contacts in the two dielectric layers;
• 3 a plan view of a possible distribution of linear contacts in the two dielectric layers.

In the 1 schematically is a silicon thin film solar cell in substrate configuration shown, wherein the absorber layer 7 of n-type liquid-phase crystallized silicon (layer thickness 15 microns) and the adjacent hetero emitter layer not shown - from an intrinsic and a p-type amorphous hydrogen-containing silicon layer (layer thickness of the intrinsic layer 5 nm, the p-type layer 10 nm) is formed. The back electrode 2 , so arranged on a glass substrate 1 , is a high-temperature-resistant conductive layer and formed of molybdenum in a thickness of 400 nm. Between back electrode 2 and absorber layer 7 are two electrically insulating dielectric interlayers 3 . 5 each with a thickness of 150 nm and between them a highly doped n-type Si semiconductor layer 4 arranged with a thickness of 50 nm. The to the molybdenum layer 2 adjacent intermediate layer 3 is formed of SiO ₂ , which is the liquid phase crystallized silicon absorber layer 7 adjacent intermediate layer 5 also made of SiO ₂ . The highly doped semiconductor layer 4 In this embodiment, an n ⁺⁺ doped crystalline 50 nm thick silicon layer is also produced by liquid-phase crystallization in the same crystallization step as the absorber layer. The two insulating dielectric interlayers 3 . 5 have mutually offset holes with a diameter of 1 micron, the contact openings 6 form and charge transport between the back Mo electrode 2 and the n-type liquid phase crystallized silicon absorber layer 7 guarantee. On the hetero emitter layer, a front electrode layer, not shown, is formed of a transparent conductive oxide (TCO), such as indium tin oxide (ITO), and of a thickness of 80 nm. Optionally, a metallic electrode grid may additionally be arranged on the ITO layer (not shown). In addition, the glass substrate 1 opposite surface of the absorber layer 7 have a texture for improving light trapping (also not shown).

The production of the described silicon thin-film solar cell arrangement is carried out with the following method steps:

On a glass substrate 1 First, the backside electrode 2 made of molybdenum by PVD. Subsequently, the first dielectric layer 3 made of SiO ₂ at a deposition temperature of 200 to 600 ° C. In this layer 3 become punctiform openings 6 introduced, which have a diameter of 1 micron and a distance of 100 microns. It becomes a conductive layer 4 deposited by PVD, which in this embodiment is a highly doped n ⁺⁺ silicon layer. On this layer 4 becomes the second dielectric layer 5 made of SiO ₂ applied, in which likewise by means of laser punctiform openings 6 be introduced. This takes place analogously to the method steps as already described for the first dielectric layer 3 have been described. It should be noted that the openings 6 in the first dielectric layer 3 and the openings 6 in the second dielectric layer 5 offset from each other, so that a transverse line of the charge carriers in the highly doped silicon layer 4 is guaranteed and the back electrode layer 2 with the absorber layer 7 the silicon thin-film solar cell assembly is electrically connected. For the production of the n-type crystalline silicon layer as absorber layer 7 First, a silicon layer is applied by means of PECVD and then subjected to liquid phase crystallization by means of a laser. At the same time, the intermediate layers reduce 3 . 5 the diffusion of impurities from the back electrode 2 in the absorber layer 7 , On the n-type crystalline silicon layer 7 For example, the hetero emitter layer comprising an intrinsic and a p-type amorphous hydrogen-containing silicon layer is deposited by PECVD (corresponding to 5 and 10 nm thicknesses). For the front electrode, indium tin oxide is applied to the hetero emitter layer by PVD. Optionally, the front-side electrode may have an additional electrode grid. The thickness of the ITO layer is 80 nm in this embodiment. When a textured surface of the silicon thin-film solar cell is provided on the light incident side, the absorber layer first becomes 7 structured by anisotropic etching (eg wet-chemically or dry by means of plasma) and the subsequent layers are deposited in accordance with the structure. The exposure of the rear electrode is carried out by means of laser ablation or back etching (eg by means of reactive ion etching with O ₂ and SF ₆ ) through the layers to the Mo layer.

The 2 and 3 In each case a possible arrangement of point and line-shaped arrangements of the contact openings in the two dielectric layers can be seen. In both cases, a periodic arrangement of the contact openings in each dielectric layer is shown (darker circles or lines are assigned to the dielectric layer adjacent to the back electrode, lighter filled the upper dielectric layer), but - as already described - an offset to one another exhibit. An illustrated periodic arrangement is not necessarily for the invention.

So far, only unilaterally contacted solar cells based on liquid-phase crystallized silicon are known. With the solution according to the invention, a technologically less expensive solar cell can be realized, since the described layer system comprising at least two dielectric layers with interposed highly conductive layer and in the dielectric layers staggered contact openings both a good passivation of the absorber layer, a good electrical contact and a reduction of Defects caused by reduction of impurities from the Mo layer as well as good electrical properties. The arrangement according to the invention enables series connection, as is usual in thin-film components, and does not require interlaced structures.

Claims (17)

Semiconductor device having front and rear electrodes (2), comprising on a substrate (1) at least one contact layer for charge carriers of a conductivity type as the rear electrode (2), on which at least one active semiconductor layer (7) and a front-side electrode are arranged, and at least one intermediate layer (3, 5) is arranged between the rear electrode (2) and the at least one active semiconductor layer (7), characterized in that between the rear electrode (2) and the at least one active semiconductor layer (7) at least one first ( 3) and a second (5) electrically insulating dielectric interlayer and arranged between them at least one electrically conductive layer (4) are arranged and wherein the two electrically insulating dielectric layers (3, 5) contact openings (6) and wherein the contact openings (6 ) of the second electrically insulating dielectric layer (5) offset ordered to those of the first electrically insulating dielectric layer (3), so that a diffusion of impurities from the back electrode (2) is reduced in the active semiconductor layer (7) and so that the rear electrode (2), which is formed over the entire surface , and the at least one active semiconductor layer (7) are electrically conductively connected, and wherein the electrically conductive layer (4) is formed of a more highly doped semiconductor than the at least one active semiconductor layer (7) and the doping is between 1 × 10 ¹⁹ cm ^-3 and 1 × 10 ²¹ cm ^-3 . Semiconductor device according to Claim 1 , characterized in that the at least one active semiconductor layer (7) is formed of crystalline silicon. Semiconductor device according to Claim 2 , characterized in that the crystalline silicon layer (7) is produced by means of liquid-phase crystallization and has a thickness of between 5 μm and 40 μm. Semiconductor device according to Claim 1 , characterized in that the substrate of glass (1) and the backside electrode (2) are formed of a refractory metal. Semiconductor device according to Claim 1 , characterized in that the substrate (1) and the backside electrode (2) are replaced by a metal foil. Semiconductor device according to Claim 1 , characterized in that the at least two dielectric layers (3, 5) of SiO _x or SiN _x or SiO _x N _y or Al ₂ O ₃ or SiCx are formed. Semiconductor device according to Claim 1 , characterized in that the layer thickness of the at least two dielectric layers (3, 5) is in each case between 50 nm and 400 nm. Semiconductor device according to Claim 1 , characterized in that the layer thickness of the electrically conductive layer (4) is between 50 nm and 100 nm. Semiconductor device according to Claim 1 , characterized in that the mutually offset contact openings (6) in the at least two dielectric layers (3, 5) are point or line-shaped and have a typical distance from each other of 0.5 microns to 500 microns and corresponding to a diameter of 50 nm to 50 microns and a width of 50 nm to 50 microns. Semiconductor device according to Claim 1 and at least one of the preceding claims, characterized in that the semiconductor device is formed as a silicon thin-film solar cell in substrate configuration. Method for producing a semiconductor device according to Claim 1 comprising the following method steps: applying a back-side full-area electrode layer (2) to a substrate (1), then producing a first electrically insulating dielectric layer (3) with contact openings (6) to the underlying back-side electrode, applying an electrical conductive layer (4) on the first electrically insulating dielectric layer (3), wherein the electrically conductive layer (4) of a higher doped semiconductor as an active semiconductor layer (7) is formed and the doping between 1 × 10 ¹⁹ cm ^-3 and 1 × 10 ²¹ cm ^-3 , - subsequently producing a second electrically insulating dielectric layer (5) with contact openings (6) to the underlying conductive layer (4), wherein the contact openings (6) of the second electrically insulating dielectric layer (5 ) are arranged offset to those of the first electrically insulating dielectric layer (3), so that e Ine diffusion of impurities from the back electrode (2) into an active semiconductor layer (7) is reduced, then producing at least one active semiconductor layer (7) and finally applying a front-side electrode. Method according to Claim 11 , characterized in that as material for the two dielectric layers (3, 5) SiO _x or SiN _x or SiO _x N _y or Al ₂ O ₃ or SiC _x is used. Method according to Claim 11 , characterized in that the at least two dielectric layers (3, 5) are each applied with a layer thickness between 50 nm and 400 nm. Method according to Claim 11 , characterized in that after the application of the front-side electrode, the rear-side electrode (2) is exposed. Method according to Claim 11 , characterized in that for the preparation of the active semiconductor layer (7) first a thin Si layer having a thickness of 5 .mu.m to 40 .mu.m applied and then crystallized by liquid phase crystallization by means of laser beam in air or in an inert gas or in vacuo or by electron beam , Method according to Claim 11 , characterized in that the contact openings (6) in the two electrically insulating dielectric layers (3, 5) punctiform or linear with a distance from each other of 0.5 microns to 500 microns and a diameter or width corresponding to 50 nm to 50 microns be executed. Method according to Claim 16 , characterized in that the point or line-shaped contact openings (6) in the two electrically insulating dielectric layers (3, 5) by means of laser or photo- or nanoimprint lithography or via nanoparticle deposition and subsequent etching are applied.

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