EP2698818A2 - Method and apparatus for processing a semiconductor workpiece - Google Patents
Method and apparatus for processing a semiconductor workpiece Download PDFInfo
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- EP2698818A2 EP2698818A2 EP13179849.8A EP13179849A EP2698818A2 EP 2698818 A2 EP2698818 A2 EP 2698818A2 EP 13179849 A EP13179849 A EP 13179849A EP 2698818 A2 EP2698818 A2 EP 2698818A2
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- workpiece
- pressure
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- torr
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- 238000000034 method Methods 0.000 title claims abstract description 56
- 238000012545 processing Methods 0.000 title claims abstract description 31
- 239000004065 semiconductor Substances 0.000 title claims abstract description 26
- 238000001816 cooling Methods 0.000 claims abstract description 14
- 238000004891 communication Methods 0.000 claims abstract description 13
- 239000012530 fluid Substances 0.000 claims abstract description 13
- 238000005086 pumping Methods 0.000 claims description 4
- 230000001419 dependent effect Effects 0.000 claims description 2
- 235000012431 wafers Nutrition 0.000 description 50
- 238000000151 deposition Methods 0.000 description 17
- 230000008021 deposition Effects 0.000 description 17
- 239000007789 gas Substances 0.000 description 17
- 238000005240 physical vapour deposition Methods 0.000 description 9
- 229910052751 metal Inorganic materials 0.000 description 7
- 239000002184 metal Substances 0.000 description 7
- 238000013459 approach Methods 0.000 description 6
- 238000005137 deposition process Methods 0.000 description 5
- 239000000463 material Substances 0.000 description 5
- 238000004544 sputter deposition Methods 0.000 description 4
- 238000012546 transfer Methods 0.000 description 4
- 239000004411 aluminium Substances 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- FFBHFFJDDLITSX-UHFFFAOYSA-N benzyl N-[2-hydroxy-4-(3-oxomorpholin-4-yl)phenyl]carbamate Chemical compound OC1=C(NC(=O)OCC2=CC=CC=C2)C=CC(=C1)N1CCOCC1=O FFBHFFJDDLITSX-UHFFFAOYSA-N 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000011261 inert gas Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000005334 plasma enhanced chemical vapour deposition Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229920000642 polymer Polymers 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 239000000758 substrate Substances 0.000 description 1
Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/687—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using mechanical means, e.g. chucks, clamps or pinches
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67098—Apparatus for thermal treatment
- H01L21/67109—Apparatus for thermal treatment mainly by convection
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
- C23C14/34—Sputtering
-
- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
- C23C16/44—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating
- C23C16/455—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the method of coating characterised by the method used for introducing gases into reaction chamber or for modifying gas flows in reaction chamber
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02612—Formation types
- H01L21/02617—Deposition types
- H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67242—Apparatus for monitoring, sorting or marking
- H01L21/67253—Process monitoring, e.g. flow or thickness monitoring
Definitions
- This invention relates to a method and apparatus for processing a semiconductor workpiece.
- Sputter deposition of metal films is widely used in the semiconductor and related industries. It is usually desirable to maximize the deposition rate of the sputtered film so that the number of wafers per hour that can be processed is as high as possible.
- Wafers of thickness less than 100 microns, typically of 30-50 microns thickness are fragile, and can warp easily.
- a particular problem is encountered when a relatively thick layer of metal is deposited on the wafer.
- the metal layer is often 2-10 microns thick, which places an additional stress on a fragile wafer.
- the present invention in at least some of its embodiments, provides a method for processing thinned, warped, insulative or otherwise problematic wafers at high deposition rate while maintaining a low process pressure.
- the invention is not limited to thinned, warped, insulative or other problematic wafers, and nor is it limited to the use of ESC devices to support and/or clamp the wafer.
- a method of processing a semiconductor workpiece having a front surface and a back surface including the steps of:
- P c2 may also be sufficiently high to enhance cooling of the workpiece.
- a method of processing a semiconductor workpiece having a front surface and a back surface including the steps of:
- the steps ii) and iii) may form a processing/cooling cycle which is performed repeatedly.
- the pressure differentials P b1 -P c1 and P b2 -P c2 may each be maintained at less than +1 Torr.
- the pressure differentials P b1 -P c1 and P b2 -P c2 may each be maintained in the range -0.5 to +0.5 Torr.
- step iii) the pressure differential P b2 -P c2 may be maintained at about 0 Torr.
- the chamber is in fluid communication with the back region during at least step iii) so that P b2 is substantially equal to P c2 .
- step ii) the pressure differential P b1 -P c1 may be maintained at about 0 Torr.
- the chamber may be in fluid communication with the back region during step ii) so that P b1 is substantially equal to P c1 .
- P c2 is in the range 0.5 to 20 Torr, preferably about 1 Torr.
- the workpiece may be clamped in place by the workpiece support.
- the workpiece support includes an electrostatic chuck.
- the workpiece is clamped by the electrostatic chuck. This can result in improved cooling and higher throughput.
- the workpiece is not clamped by the electrostatic chuck. It is possible to use other kinds of workpiece supports and clamping, such as mechanical clamps.
- the processing step may be a PVD (physical vapour deposition) process.
- the processing step is a non-PVD process, such as a chemical vapour deposition process (CVD), for example a plasma enhanced chemical vapour deposition process (PECVD), ion implantation or reactive ion etching.
- CVD chemical vapour deposition process
- PECVD plasma enhanced chemical vapour deposition process
- ion implantation or reactive ion etching reactive ion etching.
- the processing step may be a metal sputtering process, such as an aluminium sputtering process.
- the metal layer produced by the processing step can place a stress on the workpiece, particularly with thinned wafers.
- the relatively small pressure differentials associated with the present invention are particularly advantageous in preventing the workpiece from being subjected to further undesirable stress.
- the semiconductor workpiece may consist of at least one semiconductor material.
- the semiconductor workpiece may include at least one semiconductor material together with one or more non-semiconductor materials, such as insulators and metals.
- a non-semiconductor material such as a metal can place a stress on the workpiece.
- the semiconductor workpiece is a semiconductor wafer.
- the semiconductor wafer may be a thinned, warped, damaged, taped or insulative wafer, although the invention is not limited in this respect.
- the semiconductor workpiece may be processed to produce an integrated circuit (IC).
- IC integrated circuit
- a semiconductor processing apparatus including: a chamber; a workpiece support positioned in the chamber; a gas supply and pumping arrangement for providing a desired chamber gas pressure in the chamber and a desired back gas pressure in a back region which, in use, is in fluid communication with a rear surface of a semiconductor workpiece; and a control arrangement configured to control the semiconductor processing apparatus, including the gas supply and pumping arrangement, to perform a method according to the first or second aspects of the invention.
- Removing heat from a wafer during the deposition cycle in a PVD tool is a common problem. Ideally the temperature of the wafer is maintained at predetermined set point(s) during the PVD deposition cycle.
- FIG. 1 shows a simplified cross-section of a PVD deposition chamber 10 of known type having an electrostatic chuck (ESC) 12.
- ESC electrostatic chuck
- the apparatus further comprises a process gas inlet having a process inlet gas valve 1, a process gas outlet having a highvac valve 2 and a pump (not shown), and a back pressure inlet to the electrostatic chuck 12 which includes a back pressure supply valve 5 and a back pressure control valve 4 which controls back pressure to the process wafer.
- the apparatus further comprises an electrostatic chuck back pressure pump valve 3 which enables back pressure gas to be evacuated when valves 2 and 3 are open and valve 1 is closed.
- valve configuration During normal clamped processing the valve configuration would be as shown in Table 1.
- the cavity behind the wafer is maintained at ⁇ 10Torr (back pressure) while the PVD process is carried out at ⁇ 2mTorr.
- This configuration will allow a good thermal transfer between the wafer and the ESC but there is a significant pressure differential (5x10 3 ) which increases the tendency of certain wafer types to de-clamp.
- Table 1 Prior art ESC Process with Back Pressure Step Valve 1 Valve 2 Valve 3 Valve 4 Valve 5 Chamber Pressure Pc1 Back Pressure Pb1 ESC Deposition OPEN OPEN CLOSED OPEN OPEN 2 mTorr 10 Torr ON
- Table 3 ESC Deposition and Backfill Step Valve 1 Valve 2 Valve 3 Valve 4 Valve 5 Chamber Pressure Pc1/Pc2 Back Pressure Pb1/Pb2 ESC Deposition OPEN OPEN OPEN CLOSED 2 mTorr 2mTorr ON Backfill CLOSED CLOSED OPEN OPEN CLOSED 1 Torr 1 Torr ON
- Table 3 uses an ESC to clamp the wafer during the deposition cycle.
- Pb1-Pc1 is minimized by opening valve 4 while closing V5.
- a modified "Backfill" step is also used to maintain a small pressure differential between Pb2-Pc2 by opening valves 3 and 4. Using this technique it is possible to significantly lengthen the deposition step (dependent on wafer type) and shorten the cool step resulting in high throughput while avoiding the de-clamp issues associated with having a high pressure differential between the front and backside of the wafer.
- Chambers of known type can be adapted to perform the invention by providing suitable control of the valves 1-5. This can be conveniently implemented by controlling the operation of the valves during processing with a suitably adapted control system (not shown) which may operate in accordance with suitable software.
- a 15sec 1Torr cooldown step is significantly more efficient in reducing the temperature of that wafer than a 10Torr backfill step, 160 vs 182°C, while clamping at base pressure also achieves a slight improvement over the unclamped process - 210-216°C.
- the chamber and the wafer backside region may not be in fluid communication, but instead each form part of separate gas supply systems.
- the gas pressures of these separate gas supply systems can be set and maintained so that the pressures experienced by the front and back faces of the wafer are equal, or are set to achieve a desired pressure differential in accordance with the invention.
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Chemical & Material Sciences (AREA)
- Chemical Kinetics & Catalysis (AREA)
- Materials Engineering (AREA)
- Mechanical Engineering (AREA)
- Metallurgy (AREA)
- Organic Chemistry (AREA)
- General Chemical & Material Sciences (AREA)
- Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)
- Physical Vapour Deposition (AREA)
- Drying Of Semiconductors (AREA)
Abstract
i) placing the back surface of the workpiece on a workpiece support in a chamber so that the front surface of the workpiece faces into the chamber for processing, the chamber having an associated chamber gas pressure, and the back surface is in fluid communication with a back region having an associated back gas pressure;
ii) performing a workpiece processing step at a first chamber pressure Pc1 and a first back pressure Pb1, wherein Pc1 and Pb1 give rise to a pressure differential, Pb1-Pc1, which is maintained so as to avoid a pressure induced loss of contact between the workpiece and the workpiece support; and
iii) performing a workpiece cooling step at a second chamber pressure Pc2 and a second back pressure Pb2, wherein Pc2 and Pb2 are higher than Pc1 and Pb1, respectively, at least Pb2 being sufficiently high to enhance cooling of the workpiece, and wherein Pc2 and Pb2 give rise to a pressure differential, Pb2-Pc2, which is maintained so as to avoid a pressure-induced loss of contact between the workpiece and the workpiece support.
Description
- This invention relates to a method and apparatus for processing a semiconductor workpiece.
- Sputter deposition of metal films is widely used in the semiconductor and related industries. It is usually desirable to maximize the deposition rate of the sputtered film so that the number of wafers per hour that can be processed is as high as possible.
- However, high deposition rate PVD (physical vapour deposition) processes present IC (integrated circuit) manufacturers with integration issues. As the power supplied to the sputter target increases so does the ability of the hot plasma and incoming energetic species to heat the wafer. For many applications it is necessary to keep the wafer temperature as low as possible to avoid affecting previously deposited materials that may be sensitive to elevated temperatures (e.g. polymers, adhesives, dielectrics, etc.).
- One existing solution involves the processing of the wafer on a cold electrostatic chuck (ESC). At process pressure the thermal transfer between the wafer and the ESC is very low, (M. Klick, M. Bernt, JVAC 24 (2006)). The industry standard approach to improve thermal conductivity between the substrate and the chuck is to use a backside gas pressure. However, for thinned, highly warped, damaged, taped, or insulative wafers it can be very problematic to generate a clamping force that is sufficient to keep the wafer clamped during the deposition process when a gas back pressure is used. This type of problematic wafer is commonly encountered in the IC packaging industry. For example, it is common to utilise thinned wafers of thickness less than 100 microns, typically of 30-50 microns thickness. Wafers of this type are fragile, and can warp easily. A particular problem is encountered when a relatively thick layer of metal is deposited on the wafer. The metal layer is often 2-10 microns thick, which places an additional stress on a fragile wafer.
- The present invention, in at least some of its embodiments, provides a method for processing thinned, warped, insulative or otherwise problematic wafers at high deposition rate while maintaining a low process pressure. However, the invention is not limited to thinned, warped, insulative or other problematic wafers, and nor is it limited to the use of ESC devices to support and/or clamp the wafer.
- According to a first aspect of the invention there is provided a method of processing a semiconductor workpiece having a front surface and a back surface, including the steps of:
- i) placing the back surface of the workpiece on a workpiece support in a chamber so that the front surface of the workpiece faces into the chamber for processing, the chamber having an associated chamber gas pressure, and the back surface is in fluid communication with a back region having an associated back gas pressure;
- ii) performing a workpiece processing step at a first chamber pressure Pc1 and a first back pressure Pb1, wherein Pc1 and Pb1 give rise to a pressure differential, Pb1-Pc1, which is maintained so as to avoid a pressure induced loss of contact between the workpiece and the workpiece support, and
- iii) performing a workpiece cooling step at a second chamber pressure Pc2 and a second back pressure Pb2, wherein Pc2 and Pb2 are higher than Pc1 and Pb1, respectively, at least Pb2 being sufficiently high to enhance cooling of the workpiece, and wherein Pc2 and Pb2 give rise to a pressure differential, Pb2-Pc2, which is maintained so as to avoid a pressure-induced loss of contact between the workpiece and the workpiece support.
- In step iii), Pc2 may also be sufficiently high to enhance cooling of the workpiece.
- According to a second aspect of the invention there is provided a method of processing a semiconductor workpiece having a front surface and a back surface, including the steps of:
- i) placing the back surface of the workpiece on a workpiece support in a chamber so that the front surface of the workpiece faces into the chamber for processing, the chamber having an associated chamber gas pressure, and the back surface is in fluid communication with a back region having an associated back gas pressure;
- ii) performing a workpiece processing step at a first chamber pressure Pc1 and a first back pressure Pb1, wherein Pc1 and Pb1 give rise to a pressure differential, Pb1-Pc1, which is maintained at less than +2 Torr.
- iii) performing a workpiece cooling step at a second chamber pressure Pc2 and a second back pressure Pb2, wherein Pc2 and Pb2 are higher than Pc1 and Pb1, respectively, Pb2 is greater than or equal to 0.5 Torr, and wherein Pc2 and Pb2 give rise to a pressure differential, Pb2-Pc2, which is maintained at less than +2 Torr.
- The steps ii) and iii) may form a processing/cooling cycle which is performed repeatedly.
- The pressure differentials Pb1-Pc1 and Pb2-Pc2 may each be maintained at less than +1 Torr.
- The pressure differentials Pb1-Pc1 and Pb2-Pc2 may each be maintained in the range -0.5 to +0.5 Torr.
- During step iii) the pressure differential Pb2-Pc2 may be maintained at about 0 Torr. In some embodiments the chamber is in fluid communication with the back region during at least step iii) so that Pb2 is substantially equal to Pc2.
- During step ii) the pressure differential Pb1-Pc1 may be maintained at about 0 Torr. The chamber may be in fluid communication with the back region during step ii) so that Pb1 is substantially equal to Pc1.
- In some embodiments Pc2 is in the range 0.5 to 20 Torr, preferably about 1 Torr.
- The workpiece may be clamped in place by the workpiece support.
- In some embodiments, the workpiece support includes an electrostatic chuck. Typically, the workpiece is clamped by the electrostatic chuck. This can result in improved cooling and higher throughput. However, in other embodiments the workpiece is not clamped by the electrostatic chuck. It is possible to use other kinds of workpiece supports and clamping, such as mechanical clamps.
- In some embodiments, the processing step may be a PVD (physical vapour deposition) process. In other embodiments, the processing step is a non-PVD process, such as a chemical vapour deposition process (CVD), for example a plasma enhanced chemical vapour deposition process (PECVD), ion implantation or reactive ion etching.
- The processing step may be a metal sputtering process, such as an aluminium sputtering process. The metal layer produced by the processing step can place a stress on the workpiece, particularly with thinned wafers. The relatively small pressure differentials associated with the present invention are particularly advantageous in preventing the workpiece from being subjected to further undesirable stress.
- The semiconductor workpiece may consist of at least one semiconductor material. Alternatively, the semiconductor workpiece may include at least one semiconductor material together with one or more non-semiconductor materials, such as insulators and metals. As noted above, a non-semiconductor material such as a metal can place a stress on the workpiece.
- Typically, the semiconductor workpiece is a semiconductor wafer. The semiconductor wafer may be a thinned, warped, damaged, taped or insulative wafer, although the invention is not limited in this respect.
- The semiconductor workpiece may be processed to produce an integrated circuit (IC).
- According to a third aspect of the invention there is provided a semiconductor processing apparatus including: a chamber; a workpiece support positioned in the chamber; a gas supply and pumping arrangement for providing a desired chamber gas pressure in the chamber and a desired back gas pressure in a back region which, in use, is in fluid communication with a rear surface of a semiconductor workpiece; and a control arrangement configured to control the semiconductor processing apparatus, including the gas supply and pumping arrangement, to perform a method according to the first or second aspects of the invention.
- Whilst the invention has been described above, it extends to any inventive combination of the features set out above, or in the following description, drawings or claims. For example, any feature described in relation to the first or second aspects of the invention may be incorporated in the third aspect of the invention and vice versa.
- The invention may be performed in various ways and specific embodiments will now be described, by way of example only, with reference to the accompanying drawings:-
-
Figure 1 is a semi-schematic diagram of an apparatus which can be used in conjunction with the invention; and -
Figure 2 shows wafer temperature (°C) as a function of time for different cool down steps during an aluminium deposition process. - Removing heat from a wafer during the deposition cycle in a PVD tool is a common problem. Ideally the temperature of the wafer is maintained at predetermined set point(s) during the PVD deposition cycle.
- The conventional way to remove heat from the wafer is to retain the wafer on the platen top by use of either a mechanical clamp or electrostatic chuck and pressurize a cavity on the backside of the wafer to ∼1 -15Torr with an inert gas such as He. The relatively high pressure He aids heat transfer from the wafer to the platen.
Figure 1 below shows a simplified cross-section of aPVD deposition chamber 10 of known type having an electrostatic chuck (ESC) 12. The apparatus further comprises a process gas inlet having a processinlet gas valve 1, a process gas outlet having ahighvac valve 2 and a pump (not shown), and a back pressure inlet to theelectrostatic chuck 12 which includes a backpressure supply valve 5 and a backpressure control valve 4 which controls back pressure to the process wafer. The apparatus further comprises an electrostatic chuck backpressure pump valve 3 which enables back pressure gas to be evacuated whenvalves valve 1 is closed. - During normal clamped processing the valve configuration would be as shown in Table 1. The cavity behind the wafer is maintained at ∼10Torr (back pressure) while the PVD process is carried out at ∼2mTorr. This configuration will allow a good thermal transfer between the wafer and the ESC but there is a significant pressure differential (5x103) which increases the tendency of certain wafer types to de-clamp. There are however a growing number of applications, such as thinned wafers and wafers on carriers, where the risk of electrostatic de-clamping makes this process not viable in a production environment. While mechanical clamps could be used they have significant problems related to particulate generation and as a result alternative approaches are typically preferred.
Table 1: Prior art ESC Process with Back Pressure Step Valve 1 Valve 2Valve 3Valve 4Valve 5Chamber Pressure Pc1 Back Pressure Pb1 ESC Deposition OPEN OPEN CLOSED OPEN OPEN 2 mTorr 10 Torr ON - For wafer types which risk de-clamping an alternative approach is to carry out a dedicated cool down step following (part of the) deposition process. In Table 2 we can see a chamber "backfill" process where the wafer temperature is allowed to rise to an acceptable value during the deposition step when the sputtering process is stopped followed by a "backfill" cool process step where the chamber pressure is raise to ∼1Torr. Heat is lost to the platen assembly and the chamber walls. The chamber pressure Pc2 of 1 Torr is achieved by leaving
valve 1 open after the deposition process is stopped until this backfill pressure is achieved. Then all the valves are operated as described in Table 2.Table 2: Prior art Backfill Process Step Valve 1 Valve 2Valve 3Valve 4Valve 5Chamber Pressure Pc1/Pc2 Back Pressure Pb1/Pb2 ESC Deposition OPEN OPEN CLOSED CLOSED CLOSED 2 mTorr None OFF Backfill CLOSED CLOSED CLOSED CLOSED CLOSED 1 Torr None OFF - This approach allows the wafer to be successfully processed but has significant productivity disadvantages. Thermal transfer to the platen is lost due to the absence of the ESC clamping force and the back pressure. Also, the deposition step must be kept short and the cool step long in order to maintain a low wafer temperature. This severely impacts the throughput of the process.
- A novel method of processing is thus proposed to safely process wafers that cannot employ the standard ESC approach of Table 1 but offers greater productivity compared to the "Backfill" approach described in Table 2.
Table 3: ESC Deposition and Backfill Step Valve 1 Valve 2Valve 3Valve 4Valve 5Chamber Pressure Pc1/Pc2 Back Pressure Pb1/Pb2 ESC Deposition OPEN OPEN OPEN OPEN CLOSED 2 mTorr 2mTorr ON Backfill CLOSED CLOSED OPEN OPEN CLOSED 1 Torr 1 Torr ON - The process described in Table 3 uses an ESC to clamp the wafer during the deposition cycle. However, unlike a conventional ECS process (Table 1), Pb1-Pc1 is minimized by opening
valve 4 while closing V5. A modified "Backfill" step is also used to maintain a small pressure differential between Pb2-Pc2 by openingvalves - Chambers of known type can be adapted to perform the invention by providing suitable control of the valves 1-5. This can be conveniently implemented by controlling the operation of the valves during processing with a suitably adapted control system (not shown) which may operate in accordance with suitable software.
- In
Figure 2 we can see the performance of various cool down steps as a function of time for a high power 16kW, 2 micron Al deposition process. The cool down step is carried out after each deposition cycle. The platen/ESC is controlled at 0°C while the wafers enter the chamber at 20°C. - It can be seen that a 15sec 1Torr cooldown step is significantly more efficient in reducing the temperature of that wafer than a 10Torr backfill step, 160 vs 182°C, while clamping at base pressure also achieves a slight improvement over the unclamped process - 210-216°C.
- Throughput comparisons for a high power 16kW, 3 micron, Al process with a thermal budget of less than 200°C than can be seen in Table 4. In both cases the Si wafers were bonded onto glass carrier wafers which had a polyimide protective tape on the glass face touching the platen assembly. The conventional backfill process requires multiple cooling steps to maintain the necessary film morphology and thermal budget control while the novel process only requires two relatively short backfill steps (where no deposition is taking place) and as such provides greater productivity.
Table 4. Throughput comparison between backfill and novel process (wph = wafers per hour). Process Number of backfills Throughput (wph) Standard backfill process 1 x 120seconds 4.9 4 x 30 seconds 1 x 60 seconds Novel process 2 x 20seconds 9.1 - The use of an equalized pressure at the front and back of the wafer in conjunction with ESC clamping enables the safe handling of warped wafers, provides better temperature control, and enables deposition to take place for a longer continuous period, in comparison to a prior art backfill process with no clamping. The use of pressurized backfills in combination with electrostatic clamping increases the efficiency of cooling and can result in higher throughput.
- From an operational point of view, it is convenient to equalise the chamber pressure and the back pressure by opening
valves
Claims (15)
- A method of processing a semiconductor workpiece having a front surface and a back surface, including the steps of:i) placing the back surface of the workpiece on a workpiece support in a chamber so that the front surface of the workpiece faces into the chamber for processing, the chamber having an associated chamber gas pressure, and the back surface is in fluid communication with a back region having an associated back gas pressure;ii) performing a workpiece processing step at a first chamber pressure Pc1 and a first back pressure Pb1, wherein Pc1 and Pb1 give rise to a pressure differential, Pb1-Pc1, which is maintained so as to avoid a pressure induced loss of contact between the workpiece and the workpiece support; andiii) performing a workpiece cooling step at a second chamber pressure Pc2 and a second back pressure Pb2, wherein Pc2 and Pb2 are higher than Pc1 and Pb1, respectively, at least Pb2 being sufficiently high to enhance cooling of the workpiece, and wherein Pc2 and Pb2 give rise to a pressure differential, Pb2-Pc2, which is maintained so as to avoid a pressure-induced loss of contact between the workpiece and the workpiece support.
- A method accordingly to claim 1 in which, in step iii), Pc2 is sufficiently high to enhance cooling of the workpiece.
- A method of processing a semiconductor workpiece having a front surface and a back surface, including the steps of:i) placing the back surface of the workpiece on a workpiece support in a chamber so that the front surface of the workpiece faces into the chamber for processing, the chamber having an associated chamber gas pressure, and the back surface is in fluid communication with a back region having an associated back gas pressure;ii) performing a workpiece processing step at a first chamber pressure Pc1 and a first back pressure Pb1, wherein Pc1 and Pb1 give rise to a pressure differential, Pb1-Pc1, which is maintained at less than +2 Torr.iii) performing a workpiece cooling step at a second chamber pressure Pc2 and a second back pressure Pb2, wherein Pc2 and Pb2 are higher than Pc1 and Pb1, respectively, Pb2 is greater than or equal to 0.5 Torr, and wherein Pc2 and Pb2 give rise to a pressure differential, Pb2-Pc2, which is maintained at less than +2 Torr.
- A method according to any one of claims 1 to 3 in which the pressure differentials Pb1-Pc1 and Pb2-Pc2 are each maintained at less than +1 Torr.
- A method according to any one of claims 1 to 4 in which the pressure differentials Pb1-Pc1 and Pb2-Pc2 are each maintained in the range -0.5 to +0.5 Torr.
- A method according to any previous claim in which during step iii) the pressure differential Pb2-Pc2 is maintained at about 0 Torr.
- A method according to claim 6 in which during step iii) the chamber is in fluid communication with the back region so that Pb2 is substantially equal to Pc2.
- A method according to any previous claim in which during step ii) the pressure differential Pb1-Pc1 is maintained at about 0 Torr.
- A method according to claim 8 in which during step ii) the chamber is in fluid communication with the back region so that Pb1 is substantially equal to Pc1.
- A method according to any previous claim in which Pc2 is in the range 0.5 to 20 Torr, preferably about 1 Torr.
- A method according to any previous claim in which the workpiece is clamped in place by the workpiece support.
- A method according to any previous claim in which the workpiece support includes an electrostatic chuck.
- A method according to claim 12 when dependent on claim 11 in which the workpiece is clamped by the electrostatic chuck.
- A method according to any previous claim in which the semiconductor workpiece is a semiconductor wafer, which is a thinned, warped, damaged, taped or insulative wafer.
- A semiconductor processing apparatus including: a chamber; a workpiece support positioned in the chamber; a gas supply and pumping arrangement for providing a desired chamber gas pressure in the chamber and a desired back gas pressure in a back region which, in use, is in fluid communication with a rear surface of a semiconductor workpiece; and a control arrangement configured to control the semiconductor processing apparatus, including the gas supply and pumping arrangement, to perform a method according to any of claims 1 to 18.
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US201261682379P | 2012-08-13 | 2012-08-13 | |
US201361779162P | 2013-03-13 | 2013-03-13 | |
GBGB1305674.2A GB201305674D0 (en) | 2013-03-28 | 2013-03-28 | Method and apparatus for processing a semiconductor workpiece |
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EP2698818A3 EP2698818A3 (en) | 2017-11-22 |
EP2698818B1 EP2698818B1 (en) | 2020-10-28 |
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EP (1) | EP2698818B1 (en) |
JP (1) | JP6325212B2 (en) |
KR (1) | KR102122100B1 (en) |
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US11987874B2 (en) * | 2019-01-23 | 2024-05-21 | Semiconductor Components Industries, Llc | Backside metal formation methods and systems |
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DE3633386A1 (en) | 1986-10-01 | 1988-04-14 | Leybold Ag | Method and device for treating substrates in a vacuum |
US6193811B1 (en) * | 1999-03-03 | 2001-02-27 | Applied Materials, Inc. | Method for improved chamber bake-out and cool-down |
JP4287579B2 (en) * | 2000-08-02 | 2009-07-01 | パナソニック株式会社 | Plasma processing apparatus and method |
JP4578701B2 (en) * | 2001-02-26 | 2010-11-10 | キヤノンアネルバ株式会社 | Substrate processing method |
JP4153708B2 (en) * | 2002-03-12 | 2008-09-24 | 東京エレクトロン株式会社 | Etching method |
JP2007502547A (en) * | 2003-05-30 | 2007-02-08 | 東京エレクトロン株式会社 | Method and system for etching a HIGH-K dielectric material. |
TWI304230B (en) * | 2003-05-30 | 2008-12-11 | Tokyo Electron Ltd | Method and system for etching a high-k dielectric material |
US20050118830A1 (en) * | 2003-11-29 | 2005-06-02 | Appleyard Nicholas J. | Method of processing a workpiece |
US7297894B1 (en) * | 2006-09-25 | 2007-11-20 | Tokyo Electron Limited | Method for multi-step temperature control of a substrate |
JP5247175B2 (en) * | 2008-02-06 | 2013-07-24 | 株式会社アルバック | Vacuum processing equipment |
CN102217055B (en) * | 2008-11-21 | 2013-09-18 | 芝浦机械电子株式会社 | Substrate processing method and substrate processing apparatus |
US20100247804A1 (en) * | 2009-03-24 | 2010-09-30 | Applied Materials, Inc. | Biasable cooling pedestal |
CN102568991B (en) * | 2010-12-17 | 2014-09-24 | 中芯国际集成电路制造(上海)有限公司 | Gas pipeline system of reaction chamber and control method of gas pipeline system |
US9793144B2 (en) * | 2011-08-30 | 2017-10-17 | Evatec Ag | Wafer holder and temperature conditioning arrangement and method of manufacturing a wafer |
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US8728953B2 (en) | 2014-05-20 |
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TW201413016A (en) | 2014-04-01 |
CN103762161A (en) | 2014-04-30 |
JP2014037627A (en) | 2014-02-27 |
EP2698818A3 (en) | 2017-11-22 |
US20140045340A1 (en) | 2014-02-13 |
CN103762161B (en) | 2017-10-31 |
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EP2698818B1 (en) | 2020-10-28 |
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