EP2625597A1 - Système d'ordonnancement de l'exécution de taches cadence par un temps logique vectoriel - Google Patents
Système d'ordonnancement de l'exécution de taches cadence par un temps logique vectorielInfo
- Publication number
- EP2625597A1 EP2625597A1 EP11771245.5A EP11771245A EP2625597A1 EP 2625597 A1 EP2625597 A1 EP 2625597A1 EP 11771245 A EP11771245 A EP 11771245A EP 2625597 A1 EP2625597 A1 EP 2625597A1
- Authority
- EP
- European Patent Office
- Prior art keywords
- task
- tasks
- occurrence
- data
- vector
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Ceased
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/48—Program initiating; Program switching, e.g. by interrupt
- G06F9/4806—Task transfer initiation or dispatching
- G06F9/4812—Task transfer initiation or dispatching by interrupt, e.g. masked
- G06F9/4831—Task transfer initiation or dispatching by interrupt, e.g. masked with variable priority
- G06F9/4837—Task transfer initiation or dispatching by interrupt, e.g. masked with variable priority time dependent
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/02—Comparing digital values
- G06F7/026—Magnitude comparison, i.e. determining the relative order of operands based on their numerical value, e.g. window comparator
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
- G06F2207/3804—Details
- G06F2207/3808—Details concerning the type of numbers or the way they are handled
- G06F2207/3812—Devices capable of handling different types of numbers
- G06F2207/382—Reconfigurable for different fixed word lengths
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
- G06F2207/3804—Details
- G06F2207/3808—Details concerning the type of numbers or the way they are handled
- G06F2207/3828—Multigauge devices, i.e. capable of handling packed numbers without unpacking them
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
- G06F7/60—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers
- G06F7/72—Methods or arrangements for performing computations using a digital non-denominational number representation, i.e. number representation without radix; Computing devices using combinations of denominational and non-denominational quantity representations, e.g. using difunction pulse trains, STEELE computers, phase computers using residue arithmetic
Definitions
- the invention relates to the scheduling of the execution of interrelated tasks in a multi-tasking system, particularly in the context of the execution of tasks of a data flow process that may include control dependent on the data.
- a recurring problem in multi-tasking systems is the scheduling of tasks, that is, the execution of each task at a time when all the conditions required by the task are met. These conditions include the availability of data consumed by the task and the availability of space to receive the data produced by the task, in the case of data stream type processing.
- a method of executing several interdependent tasks on a multi-tasking system comprising the steps of: associating with each task a logical time vector indicative of the dependencies of the task with respect to a set of tasks. other tasks, and to define a partial order relation on the set of logical time vectors, so that a successor task which depends on the execution of an occurrence of a predecessor task has a vector greater than that the predecessor task; perform the task except if its vector is greater than the vector of any of the other tasks; and update the vector of a completed task to reflect the dependencies of a new occurrence of the completed task.
- the method comprises the following steps: associating with each task a dependency counter indicative of the number of conditions to be satisfied in order to execute an occurrence of the task; when a task is completed, decrement the dependency counter of each task having a vector greater than that of the completed task; update the vector of the completed task to reflect the dependencies of a new occurrence of the task; incrementing the dependency counter of the completed task for each task whose vector is less than that of the completed task; and incrementing the dependency counter of each task having a vector greater than that of the completed task.
- the logical time vector of a current task comprises a component associated with each possible task. The component associated with the current task contains the instance number of the current task. A component associated with another task identifies the occurrence of that other task that must be completed before the current task can be executed, a null component indicating that the current task does not depend on the task associated with the null component.
- a processor module is provided with a module for comparing two Nm bit data, comprising a comparison output indicative of an order relationship between the two data, said output being defined by a table comprising rows associated with the consecutive possible values of the first data item and columns associated with the consecutive possible values of the second data item, where each row comprises a state 1 at the intersection with the column associated with the same value followed by a series of states 0.
- the series of states 0 is followed by a series of states 1 completing the row in a circular manner, the number of states 0 being the same for each row and less than half of the maximum value of the data.
- a comparator of two vectors in a partial order relationship wherein each vector comprises components having a number of bits multiple of Nm, comprises a plurality of comparison modules of the aforementioned type, connected in a chain by carry propagation terminals ; a gate disposed between the retaining propagation terminals of two consecutive modules, capable of interrupting the carry propagation between said consecutive modules in response to an active state of a signal determining a boundary between components; and a gate disposed at the comparison output, adapted to inhibit the taking into account of the state of this output in response to an inactive state of the boundary determination signal.
- each module comprises a equality output indicative of the equality of the data presented to the module
- the comparator comprises logic intended to establish an active indication if and only if all the comparison outputs of the modules are active and the equality output of at least one module is inactive.
- FIG. Basic example of a sequence of tasks to be performed in a data stream process is a graph showing the dependencies between different occurrences of each task of Figure 1;
- FIG. 3 corresponds to the graph of FIG. 2, where each occurrence of a task is numbered by a logical time vector used to identify the dependencies between occurrences of the tasks;
- FIG. 4 shows the graph of FIG. 3 with different execution times for certain task occurrences; Fig.
- FIG. 5 shows an example of a succession of tasks in a data flow type process, with two alternative execution tasks;
- Figure 6 is a graph numbered by logical time vectors of the occurrences of the tasks of Figure 5;
- FIG. 7 is a graph representing an exemplary execution trace of a processing corresponding to FIG. 5, numbered by logical time vectors and dependency counter values;
- FIG. 8 represents a graph of another execution trace case; and
- FIG. 9 schematically represents a vector comparator embodiment according to a partial order.
- task means a generic set of treatments.
- execution of the task, or an “occurrence” of the task, is meant the execution of the task on a specific set of data (in a data stream type processing, consecutive occurrences of the same task on consecutive datasets of an incoming stream).
- Logical time vectors are associated with each task and reflect the dependencies of the current occurrence of the task.
- Logical time vectors associated with a partial order relationship, have been used to date events passed from one process to another, so that each process that receives events by distinct ways can reorder them causally.
- a logical time vector is normally used to identify and relatively date an event that occurred in the past.
- logical time vectors are used in the present application to determine from what moment a task can be executed.
- logical time vectors are used to constrain the order of task execution, that is, to organize events in the future.
- FIG. 1 represents an elementary flow-type processing.
- a task A provides data to a task B, which processes it and delivers the result to a task C.
- the tasks communicate their data via buffers (FIFO), whose depth is 3 in this example.
- FIFO buffers
- the conditions for performing these tasks are as follows.
- Task A can only run if the first buffer is not full.
- Task B can only execute if the first buffer is not empty and the second buffer is not full.
- Task C can only execute if the second buffer is not empty.
- FIG. 2 is a graph showing the dependencies between the occurrences of the tasks A, B and C.
- the rows correspond respectively to the tasks A, B and C.
- the consecutive circles in a row correspond to consecutive occurrences of the same task, numbered in FIG. circles.
- the columns correspond to consecutive execution cycles, assuming, for simplicity, that each occurrence of a task ends in one cycle.
- Arrows connect dependent occurrences. Each arrow means “must take place before”. In other words, in the graph as shown, each arrow must point to the right; it can not point to the left or be vertical.
- the arrows in solid lines correspond to dependencies imposed by the order of execution of the tasks.
- the dashed arrows correspond to the dependencies imposed by the (limited) depth of the buffers.
- FIG. 3 represents the graph of FIG. 2 where each occurrence of a task is annotated by a logical time vector according to the method referred to herein.
- a logical time vector is associated with each task, and updated at the end of each occurrence of the task. As the updates of these vectors correspond to incrementations, these vectors can also be called "logical clocks", denoted H.
- each vector or clock H comprises a component associated with each executable task on a multi-tasking system.
- An example of such a technique is described in the article [P. A. S. Ward, "An offline algorithm for dimensional-bound analysis," Proceeding of the 1999 IEEE International Conference on Parallel Processing, pp. 128-136.
- FIG. 3 there are three vectors H (A), H (B) and H (C) respectively assigned to the tasks A, B and C, and each vector has three components respectively assigned to the tasks A, B and vs.
- a component h. associated with a task Ti of a vector H (Tj) associated with a task Tj contains, for example, the occurrence of the task Ti necessary for the execution of the current occurrence of the task Tj.
- the component hj associated with the task Tj contains the occurrence of the task Tj that is running.
- a null component indicates that the current occurrence of the task associated with the vector does not depend on the task associated with the null component.
- the first component of the vector H (A), corresponding to task A contains 7, which is the current occurrence of task A .
- this occurrence of the task a requires that the first buffer memory ( Figure 1) has at least one location, that is to say, the 4 th instance of the task B has consumed a given in this buffer; the component (the 2 e ) associated with the task B in the vector H (A) contains 4.
- the 4 th occurrence of the task B requires that the second buffer memory have at least one location, that is, say that the 1 st occurrence of the task C has consumed data in this buffer; the component (the 3 e ) associated with the task C in the vector H (A) contains 1.
- Each vector is constructed from the graph by following the arrows of the occurrence to the nearest occurrence of each of the other tasks.
- the vector H (B) at time t7 contains (6, 6, 3)
- the vector H (C) contains (5, 5, 5). If there is no such arrow to follow backwards, the component is zero, which is the case for the first occurrences of the tasks A and B.
- the construction of the vectors proves simple to realize at the execution of an application implementing the tasks. We see that it is sufficient, starting from a certain occurrence (here the sixth for task A, the third for task B, and the first for task C), to systematically increment each component to each execution of the associated task.
- the initial and update conditions of the vector H (A) in FIG. 3 can be defined as follows:
- X ⁇ Y is true if and only if: whatever i is between 0 and n, we have Xi y., And there exists j between 0 and n such that xj ⁇ yj.
- Figure 4 shows the graph of Figure 3 modified to represent a case closer to reality.
- the first two occurrences of task B last twice as long as the other occurrences.
- the first occurrence of task C starts with a delay cycle
- the second occurrence of task C starts with two delay cycles
- the fifth occurrence of task A starts with a delay cycle.
- the logical time vector of a task remains constant over the number of cycles required for the execution of the associated task, which is seen for the first two occurrences of task B.
- a vector is updated at the moment where the task ends.
- the new value of the vector is in effect as soon as the associated task ends, and invariant during the waiting time for a new occurrence of the task (this is also the case during the waiting time for the execution of the first occurrence of tasks B and C).
- the graph can thus extend to infinity, and thus accommodate occurrences of any duration with any delay. This ensures the absence of interlocking.
- the logical time vectors are updated by systematic incrementation of their components.
- a refolding mechanism based on a partial order relation adapted to a subset of the natural numbers is preferably provided.
- the components of the vectors are defined modulo M, and the partial order relation between two vectors X (x, X2,... X n) and Y (yo, yi,. .. y n) is defined as :
- M and S are integers such that 2S ⁇ M, and M is greater than the maximum distance between components of a vector.
- the maximum difference is 6, for the vector H (A) from the seventh occurrence. This maximum difference is determinable from the moment when all the initial conditions have been taken into account, that is to say from the moment when we begin to increment all the components of all the vectors.
- the comparison of the components by the relation "less than” defined above is such that a value x is smaller than each of the next 3 (S) values, and greater than each of the previous 4 (M - S -1) values on the circle.
- S next 3
- M previous 4
- the logical time vector of each task is compared to each of the vectors of the other tasks, to know if the task can be executed. This represents significant computation resources if the number of tasks is important: the number of comparisons increases quadratically with the number of tasks.
- the result of the comparisons indicates that a task can be executed, it is possible that the task can not be executed immediately given the available computing resources (it will be said that the task is executable). It is therefore necessary to manage a list of executable tasks.
- K a dependency counter
- the content of the counter is equal to the number of conditions remaining to be satisfied; when the content becomes null, the task becomes executable.
- the scheduling process observes the contents of the dependency counters and starts the execution of each task whose counter is zero, or schedules the execution of these tasks if the resources do not allow to start their execution in parallel. .
- the vector H (T) is updated for the new occurrence of the task T.
- this can be done by incrementing each component of the vector as soon as the number of occurrences reaches a defined threshold value for the component in the initial conditions.
- K (T): K (T) + 1. In other words, all the conditions required for the execution of the new occurrence of the task T are identified, and they are counted in the dependency counter of the task T.
- K (Ta): K (Ta) + 1.
- the new conditions created by the new occurrence of the task T are identified for the other tasks Ta, and are counted in the dependency counters of these other tasks.
- the dependency counters can be made in hardware form and monitored in parallel by a zero content detection circuit.
- Logical time vectors can also be stored in dedicated registers, connected to comparators in hardware form, connected to increment and decrement the counters according to the aforementioned rules. (Of course, enough hardware counters and vector registers are provided to satisfy the number of separate tasks expected in the applications that are to be run on the system.) In this case, the system software (the scheduling process ) is only responsible for updating the vectors in the dedicated registers, the comparisons and updates of the counters being performed by hardware acceleration.
- Dependency counters provide an indication of impending execution, so they can be used, for example, to drive preload operations. In addition, it can be seen that the number of comparisons increases linearly according to the number of tasks.
- FIG. 5 shows a more complex example of a succession of tasks in a data flow type process with two execution tasks alternative.
- the task B of FIG. 1 here comprises two tasks, B and B ', of which only one is chosen for execution when the task A ends.
- Each data produced by an occurrence of the task A is pointed by a selection element SEL towards one of the tasks B and B '.
- the selection is performed by a CTL control data item, also produced by the task A, and stacked in a FIFO memory of the same depth as the FIFOs placed between the tasks A, B and C.
- This CTL control data is taken into account.
- a merge element MRG which chooses the output of the task B or B 'active to transmit it to the task C.
- FIG. 6 is a dependency graph corresponding to the case of FIG. 5, represented in the hypothesis simplified where the occurrences of tasks have the same duration and do not have a delay (like the graph of Figure 3).
- the values of the logical time vectors within the nodes representing the occurrences have been noted.
- the vectors here have four components.
- the folded vector notation was used with modulo 8 defined components.
- FIG. 5 represents an exemplary trace of execution of a processing according to the graph of FIG. 6.
- the nodes in solid line correspond to occurrences executed or running tasks.
- the dotted nodes correspond to occurrences that are pending execution.
- the first of these occurrences starts the first occurrence of task B that takes three cycles to complete. From the point of view of its vector and its dependency counter, it is considered that the first occurrence of the task B 'advances at the same time as the first occurrence of the task B.
- the fourth occurrence of task A, the second occurrence of task B / B ', actually B', and the first occurrence of task C can start in the fifth cycle.
- the counter K of the task C at the fifth cycle is decremented by 2, by twice applying the first step of updating the counters, once for task B, and once for task B '.
- the fourth occurrence of task A lasts 6 cycles, the second occurrence of task B 'lasts one cycle, and the first occurrence of task C lasts two cycles.
- the eighth cycle while the fourth occurrence of task A is still in progress, it was possible to complete the third occurrence of task B / B '(actually B) and start the second occurrence of task C.
- the fourth task B / B 'occurrence (actually B') must wait for the eleventh cycle, when the fourth occurrence of task A has ended.
- FIG. 8 is a trace of a simple example of execution of two tasks A and B where this fourth step is useful.
- the same representation conventions are used as in Figure 7.
- Each occurrence of a task A produces three data, each of which is consumed by a separate occurrence of task B.
- the FIFO between the tasks A and B has a depth of three data - it follows that each occurrence of the task A fills the FIFO memory at once.
- a second occurrence of the task A can start only after the third occurrence of the task B, which finishes freeing the FIFO.
- the second component of the vector H (A) is incremented by 3 at each execution of an occurrence of the task A, since the start of an occurrence of the task A is subordinated to the execution of three consecutive occurrences of task B.
- the first component of the vector H (B) is incremented only after each third execution of an occurrence of task B. This indicates that three consecutive occurrences of task B are subordinate to the same occurrence of Task A.
- N-1 logical time vector comparisons are made, where N is the number of tasks, and each comparison consists of comparing two by two at most N components. of vectors. The number of component comparisons increases quadratically with the number of tasks.
- FIG. 9 represents the first repetitive elements of an embodiment of a comparator of HA and HB logic time vectors that can satisfy these needs.
- a logical time vector is defined on a bounded number Nv of bits, for example 64, and that each component of this vector can be defined on a programmable number of bits, multiple of a minimum number Nm, for example 4.
- This number Nm determines the maximum number of components of a vector.
- the comparator of FIG. 9 comprises a series of comparison modules 10 connected to the chain. Each module 10 processes 4 bits of two components to compare two HA and HB vectors.
- a module 10 may be related, from the point of view of its external terminals, to a comparator based on a subtractor performing the sum of its input A and the complement to 2 ( ⁇ B + 1) of its input B.
- the modules 10 are conventional comparators.
- the logic table of these modules will be adapted to perform the comparison of folded values.
- the modules 10 are chained by their retaining outlets and their retaining inputs Co and Ci, so as to construct a comparator of two 64-bit data.
- the boundaries between the components of the vectors are defined using AND gates 12, a gate 12 being disposed between each retaining output Co of a module and the retaining input Ci of the following module.
- the holding input of the first module receives 0 (no holdback to take into account).
- Each gate 12 is controlled by a respective signal S (S0, S1, S2 7) whose active state (1) determines a boundary between components.
- the active state of the signal S blocks the gate 12, whereby the retention of the module 10 is not transmitted to the next module, and the following module does not propagate the comparison - this next module performs an independent comparison .
- An inactive signal S (0) makes the gate 12 pass and causes the chaining of two modules 10 by allowing the propagation of restraint. These two modules are thus associated with the same component.
- the four S signals are inactive, the four modules 10 are associated with a single component of 16 bits. If the signals S1 and S3 are active, the modules are associated with two separate components of 8 bits. If all the signals S are active, each module is associated with a distinct component of 4 bits.
- each signal S is applied to an inverting input of an OR gate 14, receiving on a second input the output GE of the corresponding module 10. When the signal S is inactive, the gate 14 does not propagate the output GE of the module - it is an intermediate comparison result which must not be taken into account.
- the inverted E outputs of the modules 10 arrive on an OR gate 18.
- the output of the gate 18 becomes active if at least one of the outputs E is inactive, that is to say if there is an inequality for at least one pair of components of HA and HB vectors (HA ⁇ HB).
- this gate 20 provides an active signal (HA> HB) if all the components of the vector HA are greater than or equal to their respective components of the vector HB (active gate 16 ), and that at least two respective components of the vectors HA and HB are unequal (therefore one strictly greater than the other).
- active gate 16 active gate 16
- each module 10 compare folded components.
- the table below provides, in the context of an example of aliasing, the values of the output GE according to all the possible values of A and B, indicated in decimal.
- n modules 10 are chained to correspond to a 4n bits component, despite the fact that each module 10 works independently on 4 bits, and therefore on values bounded at 15, all the chained modules, by transmission of reservoirs, work on values of 4n bits, limited to 2 4n - 1.
- a first set of components is compared.
- the output of the gate 20 is ignored and the states of the outputs of the gates 16 and 18 are stored for the next cycle, for example in flip-flops.
- the OR gate 18 receives as additional input the state (HA HB) -i previously stored for its output. Thus, if an inequality has been detected in the previous cycle, this detection is imposed on the current cycle. Furthermore, an additional AND gate 22 is interposed between the gates 16 and 20. The output of this gate 22 is active only if the output of the gate 16 and the previously stored state (HA HB) -i of this output are both active.
- the output of the gate 20 will be taken into account after a sufficient number of cycles to process all the components using the comparator.
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Abstract
Description
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Application Number | Priority Date | Filing Date | Title |
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FR1003964A FR2965946B1 (fr) | 2010-10-07 | 2010-10-07 | Systeme d'ordonnancement de l'execution de taches cadence par un temps logique vectoriel |
PCT/FR2011/052176 WO2012045942A1 (fr) | 2010-10-07 | 2011-09-21 | Système d'ordonnancement de l'exécution de taches cadence par un temps logique vectoriel |
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EP2625597A1 true EP2625597A1 (fr) | 2013-08-14 |
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EP11771245.5A Ceased EP2625597A1 (fr) | 2010-10-07 | 2011-09-21 | Système d'ordonnancement de l'exécution de taches cadence par un temps logique vectoriel |
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US (1) | US20130263152A1 (fr) |
EP (1) | EP2625597A1 (fr) |
JP (1) | JP2013539144A (fr) |
FR (1) | FR2965946B1 (fr) |
WO (1) | WO2012045942A1 (fr) |
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US10235190B2 (en) * | 2016-12-14 | 2019-03-19 | International Business Machines Corporation | Executing instructions to store context information based on routine to be executed |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
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US3938087A (en) * | 1974-05-31 | 1976-02-10 | Honeywell Information Systems, Inc. | High speed binary comparator |
US3927391A (en) * | 1975-03-25 | 1975-12-16 | Us Navy | Technique for ranking data observations |
EP0091214B1 (fr) * | 1982-04-02 | 1988-06-15 | Ampex Corporation | Comparateur de proportions pour signaux digitaux |
JP2739487B2 (ja) * | 1988-12-20 | 1998-04-15 | 株式会社日立製作所 | 描画処理装置及びその描画処理装置を用いた画像表示装置 |
US4935719A (en) * | 1989-03-31 | 1990-06-19 | Sgs-Thomson Microelectronics, Inc. | Comparator circuitry |
IL116210A0 (en) * | 1994-12-02 | 1996-01-31 | Intel Corp | Microprocessor having a compare operation and a method of comparing packed data in a processor |
JPH1153419A (ja) * | 1997-08-07 | 1999-02-26 | Fujitsu Ltd | 比較演算回路生成装置および生成方法 |
DK199801743A (da) * | 1998-12-29 | 2000-06-30 | Moeller Ole | Sum-intervaldetektor |
US6384627B1 (en) * | 2001-02-16 | 2002-05-07 | Xilinx, Inc. | Logic block used as dynamically configurable logic function |
US20060288061A1 (en) * | 2005-06-20 | 2006-12-21 | Altera Corporation | Smaller and faster comparators |
US20080005357A1 (en) | 2006-06-30 | 2008-01-03 | Microsoft Corporation | Synchronizing dataflow computations, particularly in multi-processor setting |
FR2965948A1 (fr) * | 2010-10-07 | 2012-04-13 | Commissariat Energie Atomique | Systeme d'ordonnancement de l'execution de taches cadence par un temps logique vectoriel |
-
2010
- 2010-10-07 FR FR1003964A patent/FR2965946B1/fr active Active
-
2011
- 2011-09-21 WO PCT/FR2011/052176 patent/WO2012045942A1/fr active Application Filing
- 2011-09-21 US US13/824,467 patent/US20130263152A1/en not_active Abandoned
- 2011-09-21 JP JP2013532243A patent/JP2013539144A/ja active Pending
- 2011-09-21 EP EP11771245.5A patent/EP2625597A1/fr not_active Ceased
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US20130263152A1 (en) | 2013-10-03 |
WO2012045942A1 (fr) | 2012-04-12 |
FR2965946A1 (fr) | 2012-04-13 |
JP2013539144A (ja) | 2013-10-17 |
FR2965946B1 (fr) | 2012-12-14 |
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