EP2587484B1 - Integrated circuit with configurable output cell - Google Patents
Integrated circuit with configurable output cell Download PDFInfo
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- EP2587484B1 EP2587484B1 EP20110187140 EP11187140A EP2587484B1 EP 2587484 B1 EP2587484 B1 EP 2587484B1 EP 20110187140 EP20110187140 EP 20110187140 EP 11187140 A EP11187140 A EP 11187140A EP 2587484 B1 EP2587484 B1 EP 2587484B1
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- output
- integrated circuit
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- 238000000034 method Methods 0.000 claims description 4
- 230000003213 activating effect Effects 0.000 claims description 2
- 238000004519 manufacturing process Methods 0.000 claims description 2
- 230000006854 communication Effects 0.000 description 28
- 238000004891 communication Methods 0.000 description 28
- 230000005236 sound signal Effects 0.000 description 6
- 208000016354 hearing loss disease Diseases 0.000 description 3
- 230000003071 parasitic effect Effects 0.000 description 3
- 230000002093 peripheral effect Effects 0.000 description 3
- 230000007175 bidirectional communication Effects 0.000 description 2
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 206010011878 Deafness Diseases 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 230000010370 hearing loss Effects 0.000 description 1
- 231100000888 hearing loss Toxicity 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04R—LOUDSPEAKERS, MICROPHONES, GRAMOPHONE PICK-UPS OR LIKE ACOUSTIC ELECTROMECHANICAL TRANSDUCERS; DEAF-AID SETS; PUBLIC ADDRESS SYSTEMS
- H04R25/00—Deaf-aid sets, i.e. electro-acoustic or electro-mechanical hearing aids; Electric tinnitus maskers providing an auditory perception
- H04R25/50—Customised settings for obtaining desired overall acoustical characteristics
- H04R25/505—Customised settings for obtaining desired overall acoustical characteristics using digital signal processing
Definitions
- the present invention relates to an integrated circuit (IC) with a configurable output cell, in particular to an IC for a hearing device or adapted for a hearing device.
- IC integrated circuit
- Integrated circuits or chips with embedded digital signal processors are widely used in the hearing aid industry to provide a compact and small hearing aid.
- the ICs used in hearing aids are small and the number of Input/Output ports or pads is limited.
- ICs are designed to interface specific components of the hearing aid.
- US 2011/211717 discloses a power management system for a digital processing core of a battery-powered hearing aid.
- the power management system is adapted for providing power to the hearing aid circuit in a particularly efficient manner.
- the power management system comprises a first linear voltage regulator, and a second linear voltage regulator in series with a switched-capacitor 2:1 SC converter, a positive bulk biasing voltage supply, and a negative bulk biasing voltage supply, for controlling the switching speed, threshold voltage, and current leak from the semiconductor elements of the digital processing core when the core is operated at the reduced voltage provided by the power management system.
- an integrated circuit (IC) for a hearing device as in claim 1 wherein the integrated circuit comprises a ground rail, a first power rail adapted to carry a first voltage, and a second power rail adapted to carry a second voltage, the integrated circuit comprising a number of pads for connecting the integrated circuit to other components, the number of pads including at least one output pad including a first output pad.
- the integrated circuit comprises at least one output cell including a first output cell having a ground pin connected to the ground rail, a first power supply pin connected to the first power rail, a second power supply pin connected to the second power rail, a data pin, at least one voltage select pin and an output pin wired to the first output pad.
- the first output cell is adapted to operate according to a first mode wherein the voltage on the first output pin has a first amplitude, and according to a second mode wherein the voltage on the first output pin has a second amplitude larger than the first amplitude depending on a control signal applied to the at least one voltage select pin.
- the first output cell comprises at least three transistors including a first transistor, a second transistor, and a third transistor, each transistor having a first terminal, a second terminal, a third terminal and a fourth terminal.
- the first terminal of the first transistor is wired to the ground pin
- the second terminal of the first transistor is connected to the data pin, optionally via a level shifter
- the third terminal is wired to the output pin
- the fourth terminal is wired to the first terminal.
- the fourth terminal of the second and of the third transducer are wired to a common terminal.
- the method comprises providing at least one output cell having an output pin and at least two drive transistors each having a first terminal connected to a respective first and a second power supply pin of the output cell, a second terminal, a third terminal connected to the output pin and a fourth terminal, wherein the fourth terminal of the two drive transistors are wired such that the voltage difference between the third and fourth terminal of the respective drive transistors is less than the diode threshold voltage between the third and fourth terminal.
- the method may comprise wiring the fourth terminals to the power supply pin adapted to carry the largest supply voltage, e.g. the second power supply pin.
- the voltage amplitude of the first output pad may be easily adjusted by adjusting a register setting during configuration or even during use, thereby increasing the design flexibility for hearing aid constructors without increasing the number of pads on the IC, and at the same time maintaining a low power consumption by avoiding undesired current paths in the IC.
- the at least one output cell e.g. the first output cell, may be configured to form a part of or be embedded in an input/output (IO) cell if bidirectional communication is desired.
- IO input/output
- the integrated circuit optionally comprises a processing core e.g. for digital signal processing of digital audio signal in order to compensate for hearing impairment of a user.
- the processing core is connected to a number of communication cells or peripheral units for communication with other units or components, e.g. an AD converter unit, user interface, memory unit and/or radio unit of a hearing device.
- the IC comprises at least one communication cell, including at least a first communication cell embedding one or more output cells as described herein.
- the IC may comprise a second and/or a third communication cell.
- a communication cell may be adapted to communicate according to one or more standard protocols.
- Exemplary protocols may include but are not limited to Serial Peripheral Interface Bus (SPI), Inter-Integrated Circuit (IIC or I2C) with master and/or slave, Integrated Interchip Sound (IIS, I2S), and protocols for wireless communication, etc.
- a communication cell or unit may comprise one or more output cells, e.g. a first output cell and/or a second output cell, depending on the functionality of the communication cell.
- a communication cell may comprise one or more input cells.
- a communication cell may comprise one or more input/output (IO) cells, i.e. cells that are adapted for bidirectional communication.
- IO input/output
- the integrated circuit comprises a number of pads for connecting the IC or communication cells of the IC to other components such as memory units, radio units, user interfaces, power supplies such as a battery or others.
- the number of pads includes a first pad for connection to ground or other reference voltage, a second pad for connection to a power supply, such as a battery, and a number of communication pads including a first communication pad adapted for operating as an output pad for connecting the IC to other components.
- the first power rail may be adapted to carry a first voltage V 1 , such as V battery
- the second power rail may be adapted to carry a second voltage V 2 .
- the second voltage V 2 may be larger than the first voltage V 1 .
- V 2 2*V battery .
- An output cell e.g. a first output cell and/or a second output cell, may comprise a first transistor, a second transistor and a third transistor, where each transistor has a first terminal, a second terminal, a third terminal, and a fourth terminal.
- the first transistor may be an N-MOS transistor where the first terminal is the source, the second terminal is the gate, the third terminal is the drain and the fourth terminal is the body.
- the first transistor may be configured to pull the voltage on the output pin towards ground or other reference voltage applied to the ground rail. Accordingly, the first transistor may be denoted a ground transistor.
- the second, third and/or a fourth transistor may be P-MOS transistors where the first terminal is the source, the second terminal is the gate, the third terminal is the drain and the fourth terminal is the body.
- the second, third and/or a fourth transistor may be configured to pull or drive the voltage on the output pin towards the voltage applied to the respective power supply pins via power rails available in the IC. Accordingly, the second, third and/or fourth transistors may be denoted drive transistors.
- the IC may comprise a plurality of drive transistors, each connected between the output pin and a respective power supply pin.
- the fourth terminal of at least two drive transistors may be connected to a common terminal with a voltage level equal to or larger than the voltage level on the third terminals of the at least two drive transistors.
- the first terminal of the first transistor may be wired to the ground pin and the third terminal of the first transistor may be wired to the output pin.
- the fourth terminal of the first transistor may be wired to the first terminal.
- the second terminal of the first transistor may be wired to the data pin or connected to the ouput of a first level shifter adapting a data signal on the data pin to correct signal amplitudes.
- the first terminal of the second transistor may be wired to the first power supply pin and the third terminal of the second transistor may be wired to the output pin.
- the first terminal of the third transistor may be wired to the second power supply pin and the third terminal of the third transistor may be wired to the output pin.
- the voltage difference V dif may be less than 0.4 V.
- the voltage difference V dif may be less than 0.4 V, such as less than 0.3 V, less than 0.2 V.
- the voltage difference V dif may be less than or equal to 0 V. In an embodiment, where the fourth terminals are wired to the largest power supply voltage, it is ensured that V dif is less than or equal to 0V irrespective of the mode of operation.
- the fourth terminal of the second transistor and the fourth terminal of the third transistor may be wired to the power supply pin carrying the largest voltage.
- the fourth terminal of the second transistor and the fourth terminal of the third transistor may be wired to a common terminal.
- the first terminal of the third transistor may be the common terminal.
- the second terminals of the second transistor and the third transistor may be connected to the output of a logical circuit of the first output cell for selecting between a first mode (second transistor active) and a second mode (third transistor active) of operation.
- One or more output cells of the integrated circuit may thus be adapted to be able to operate in a first mode wherein the voltage signal on the output pin switches between V GND * and V 1 * , and in a second mode wherein the voltage signal on the output pin switches between V GND * and V 2 * , depending on a control signal applied to the at least one voltage select pin.
- the integrated circuit may comprise a third power rail adapted to carry a third voltage V 3
- the first output cell may comprises a fourth transistor connected between the output pin and a third power supply pin connected to the third power rail.
- the fourth transistor has a first terminal, a second terminal, a third terminal and a fourth terminal.
- the fourth terminal may be wired to the common terminal.
- the first output cell may be adapted to operate according to a third mode wherein the voltage on the first output pin has a third amplitude depending on a control signal applied to the at least one voltage select pin.
- the first terminal of the fourth transistor may be wired to the third power supply pin, and the third terminal of the fourth transistor may be wired to the output pin.
- the second terminal of the fourth transistor may be wired to a logical circuit to enable activation of the fourth transistor in a third mode of operation, wherein the voltage signal on the output pin switches between V GND * and V 3 *, depending on a control signal applied to the at least one voltage select pin.
- One or more output cells of the integrated circuit may comprise a logical circuit having input connected to the at least one voltage select pin and the data pin, and output connected to the second terminals of the drive transistors (second, third and fourth transistor if present) for selecting between the modes by selectively activating the second, third and fourth transistor.
- the integrated circuit may comprise at least one level shifter including a first level shifter between the data pin and the second terminals of the first, second and third transistor for adapting a data signal to correct signal amplitudes.
- the first level shifter may be arranged between the data pin and the logical circuit and/or between the logical circuit and the second terminals of the drive transistors.
- the at least one level shifter may include a second level shifter between the at least one voltage select pin and the logical circuit for adapting a voltage select signal to correct signal amplitudes for the logical circuit.
- the integrated circuit may comprise a core connected to the first output cell, wherein the core is adapted to perform signal processing for a hearing device.
- Fig. 1 shows a hearing device 2.
- the hearing device 2 comprises an audio input interface 4 for receiving audio signal(s) in electronic and/or acoustic form.
- the audio input interface 4 may comprise one or more microphones, e.g. a first microphone and/or a second microphone, and/or a telecoil.
- the audio input interface 4 may comprise an audio connector or audio input boot for coupling external audiosources to the hearing device 2.
- the audio input interface 4 is connected to an AD converter unit 6 which is connected to a signal processing unit or integrated circuit 8.
- the AD converter unit 6 converts or transforms audio signals from the audio input interface 4 and send the digital audio signal(s) to the signal processing unit 8 for processing, e.g. in order to compensate for hearing loss or other hearing impairment.
- the signal processing unit 8 may send control signals to the AD converter unit 6 to configure and control operation of the AD converter unit 6.
- the signal processing unit 8 may be connected to a user interface 10 in order to allow a user, a computer or another hearing device to communicate with the hearing device, e.g. during configuration and/or during use of the hearing aid.
- the user interface 10 may comprise a push button and/or a connector for a data cable in order to couple the hearing device to e.g. a computer during configuration or another hearing device.
- the hearing device 2 may comprise a memory unit 12 connected to the signal processing unit 8 for storing data or hearing aid parameters, and the hearing device 2 may optionally comprise a radio unit 14 connected to the signal processing unit 8 and adapted for receiving and/or transmitting radio signals, e.g.
- the AD converter unit 6 may be embedded in the signal processing unit or integrated circuit 8.
- the hearing device 2 may comprise a receiver or loudspeaker 16 connected to the signal processing unit 8 for emitting audio signals to a user.
- Fig. 2 shows an exemplary signal processing unit or integrated circuit 8 according to the present invention.
- the integrated circuit 8 comprises a processing core 18 e.g. for digital signal processing of digital audio signals from an AD converter 6.
- the processing core 18 is connected to a number of communication cells or peripheral units for communication with other units of the hearing device, e.g. the AD converter unit 6, user interface 10, memory unit 12 and/or radio unit 14.
- the integrated circuit 8 comprises a number of communication cells 20, 28, 30, 32, 34, 36, 38 forming interfaces to the processing core 18.
- a communication cell may be configured to implement different communication protocols depending on the unit to be connected thereto.
- a first and/or second output cell or IO cell may be implemented in each or one or more of the communication cells 20, 28, 30, 32, 34, 36, 38.
- the integrated circuit may comprise a clock management cell 22 optionally comprising one or more output cells or IO cells as described herein.
- Fig. 3 illustrates an exemplary output cell according to the invention, e.g. a first and/or a second output cell which for example may be implemented in one or more of the communication cells of the integrated circuit in Fig. 2 .
- the output cell 106 has a ground pin 108 connected to a ground rail 50 of the integrated circuit, a first power supply pin 110 connected to a first power rail 52 of the integrated circuit adapted to carry a first voltage V 1 , a second power supply pin 112 connected to a second power rail 54 of the integrated circuit adapted to carry a second voltage V 2 , a data pin 114, at least one voltage select pin 116 and an output pin 118 wired to the first output pad 104.
- the output cell 106 further comprises a core power supply pin 120 connected to the core power rail 56.
- the first output pad 104 may be embedded in the output cell 106 as illustrated or be arranged outside the output cell in the integrated circuit.
- the output cell 106 i.e. the first output cell, is adapted to operate according to a first mode wherein the voltage on the output pin 118 has a first amplitude V 1 * , and according to a second mode wherein the voltage on the first output pin has a second amplitude V 2 *, larger than the first amplitude depending on a control signal applied to the at least one voltage select pin 116.
- the output cell 106 comprises a first transistor 122, a second transistor 124 and a third transistor 126 having respective first terminals 128A, 128B, 128C, second terminals 130A, 130B, 130C, third terminals 132A, 132B, 132C, and fourth terminals 134A, 134B, 134C.
- a logical circuit 136 is arranged between the at least one voltage select pin 116 and the second terminals 130B and 130C to selectively activate the second transistor and the third transistor depending on desired mode of operation.
- the output cell comprises a first level shifter 138 coupled between the data pin 114 and the second terminals 130B and 130C to adjust data signal level.
- a second level shifter 140 is coupled between the at least one voltage select pin 116 and the second terminals 130B and 130C to adjust voltage select signal level.
- the level shifters 138, 140 are connected to the second power power supply pin 112 and the core power supply pin 120.
- the at least one voltage select pin 116 may comprise a first voltage select pin and a second voltage select pin in order to select between more than two different operating modes of the output cell.
- Each transistor has an intrinsic parasitic diode between the third terminal and the fourth terminal which is also illustrated in Fig. 3 .
- the coupling of fourth terminals eliminate or reduce parasitic currents between fourth and third terminals of the drive transistors.
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Description
- The present invention relates to an integrated circuit (IC) with a configurable output cell, in particular to an IC for a hearing device or adapted for a hearing device.
- Integrated circuits (ICs) or chips with embedded digital signal processors are widely used in the hearing aid industry to provide a compact and small hearing aid. The ICs used in hearing aids are small and the number of Input/Output ports or pads is limited. Typically, ICs are designed to interface specific components of the hearing aid.
-
US 2011/211717 discloses a power management system for a digital processing core of a battery-powered hearing aid. The power management system is adapted for providing power to the hearing aid circuit in a particularly efficient manner. The power management system comprises a first linear voltage regulator, and a second linear voltage regulator in series with a switched-capacitor 2:1 SC converter, a positive bulk biasing voltage supply, and a negative bulk biasing voltage supply, for controlling the switching speed, threshold voltage, and current leak from the semiconductor elements of the digital processing core when the core is operated at the reduced voltage provided by the power management system. - There is a need for increasing the design flexibility when designing and constructing hearing aids to be able to use different components or be able to use the same component in a number of different hearing device models. Further, there is a need for providing ICs with low power consumption due to the limited power supply capacity of a hearing device.
- Accordingly, an integrated circuit (IC) for a hearing device as in claim 1 is provided, wherein the integrated circuit comprises a ground rail, a first power rail adapted to carry a first voltage, and a second power rail adapted to carry a second voltage, the integrated circuit comprising a number of pads for connecting the integrated circuit to other components, the number of pads including at least one output pad including a first output pad. The integrated circuit comprises at least one output cell including a first output cell having a ground pin connected to the ground rail, a first power supply pin connected to the first power rail, a second power supply pin connected to the second power rail, a data pin, at least one voltage select pin and an output pin wired to the first output pad. The first output cell is adapted to operate according to a first mode wherein the voltage on the first output pin has a first amplitude, and according to a second mode wherein the voltage on the first output pin has a second amplitude larger than the first amplitude depending on a control signal applied to the at least one voltage select pin. The first output cell comprises at least three transistors including a first transistor, a second transistor, and a third transistor, each transistor having a first terminal, a second terminal, a third terminal and a fourth terminal. The first terminal of the first transistor is wired to the ground pin, the second terminal of the first transistor is connected to the data pin, optionally via a level shifter, the third terminal is wired to the output pin, and the fourth terminal is wired to the first terminal. The fourth terminal of the second and of the third transducer are wired to a common terminal.
- Also disclosed is a method for manufacture of an integrated circuit as in
claim 12. The method comprises providing at least one output cell having an output pin and at least two drive transistors each having a first terminal connected to a respective first and a second power supply pin of the output cell, a second terminal, a third terminal connected to the output pin and a fourth terminal, wherein the fourth terminal of the two drive transistors are wired such that the voltage difference between the third and fourth terminal of the respective drive transistors is less than the diode threshold voltage between the third and fourth terminal. The method may comprise wiring the fourth terminals to the power supply pin adapted to carry the largest supply voltage, e.g. the second power supply pin. - It is an advantage of the present invention that the voltage amplitude of the first output pad may be easily adjusted by adjusting a register setting during configuration or even during use, thereby increasing the design flexibility for hearing aid constructors without increasing the number of pads on the IC, and at the same time maintaining a low power consumption by avoiding undesired current paths in the IC.
- The above and other features and advantages of the present invention will become readily apparent to those skilled in the art by the following detailed description of exemplary embodiments thereof with reference to the attached drawings, in which:
- Fig. 1
- schematically illustrates a hearing device,
- Fig. 2
- schematically illustrates an exemplary integrated circuit, and
- Fig. 3
- schematically illustrates an exemplary output cell.
- The figures are schematic and simplified for clarity, and they merely show details which are essential to the understanding of the invention, while other details have been left out. Throughout, the same reference numerals are used for identical or corresponding parts.
- The at least one output cell, e.g. the first output cell, may be configured to form a part of or be embedded in an input/output (IO) cell if bidirectional communication is desired.
- The integrated circuit optionally comprises a processing core e.g. for digital signal processing of digital audio signal in order to compensate for hearing impairment of a user. The processing core is connected to a number of communication cells or peripheral units for communication with other units or components, e.g. an AD converter unit, user interface, memory unit and/or radio unit of a hearing device. Accordingly, the IC comprises at least one communication cell, including at least a first communication cell embedding one or more output cells as described herein. The IC may comprise a second and/or a third communication cell.
- A communication cell may be adapted to communicate according to one or more standard protocols. Exemplary protocols may include but are not limited to Serial Peripheral Interface Bus (SPI), Inter-Integrated Circuit (IIC or I2C) with master and/or slave, Integrated Interchip Sound (IIS, I2S), and protocols for wireless communication, etc.
- A communication cell or unit may comprise one or more output cells, e.g. a first output cell and/or a second output cell, depending on the functionality of the communication cell. A communication cell may comprise one or more input cells. A communication cell may comprise one or more input/output (IO) cells, i.e. cells that are adapted for bidirectional communication.
- The integrated circuit comprises a number of pads for connecting the IC or communication cells of the IC to other components such as memory units, radio units, user interfaces, power supplies such as a battery or others. The number of pads includes a first pad for connection to ground or other reference voltage, a second pad for connection to a power supply, such as a battery, and a number of communication pads including a first communication pad adapted for operating as an output pad for connecting the IC to other components.
- The first power rail may be adapted to carry a first voltage V1, such as Vbattery, and the second power rail may be adapted to carry a second voltage V2. The second voltage V2 may be larger than the first voltage V1. In one or more embodiments, V2 = 2*Vbattery.
- An output cell, e.g. a first output cell and/or a second output cell, may comprise a first transistor, a second transistor and a third transistor, where each transistor has a first terminal, a second terminal, a third terminal, and a fourth terminal.
- The first transistor may be an N-MOS transistor where the first terminal is the source, the second terminal is the gate, the third terminal is the drain and the fourth terminal is the body. The first transistor may be configured to pull the voltage on the output pin towards ground or other reference voltage applied to the ground rail. Accordingly, the first transistor may be denoted a ground transistor.
- The second, third and/or a fourth transistor may be P-MOS transistors where the first terminal is the source, the second terminal is the gate, the third terminal is the drain and the fourth terminal is the body. The second, third and/or a fourth transistor may be configured to pull or drive the voltage on the output pin towards the voltage applied to the respective power supply pins via power rails available in the IC. Accordingly, the second, third and/or fourth transistors may be denoted drive transistors. The IC may comprise a plurality of drive transistors, each connected between the output pin and a respective power supply pin. The fourth terminal of at least two drive transistors may be connected to a common terminal with a voltage level equal to or larger than the voltage level on the third terminals of the at least two drive transistors.
- In one or more output cells, the first terminal of the first transistor may be wired to the ground pin and the third terminal of the first transistor may be wired to the output pin. The fourth terminal of the first transistor may be wired to the first terminal.
- The second terminal of the first transistor may be wired to the data pin or connected to the ouput of a first level shifter adapting a data signal on the data pin to correct signal amplitudes.
- In one or more output cells, the first terminal of the second transistor may be wired to the first power supply pin and the third terminal of the second transistor may be wired to the output pin.
- In one or more output cells, the first terminal of the third transistor may be wired to the second power supply pin and the third terminal of the third transistor may be wired to the output pin.
- In one or more output cells, the fourth terminals of the drive transistors may be wired such that a voltage difference Vdif = Vthird terminal - Vfourth terminal between the third terminals and the fourth terminals of the respective drive transistors is less than the diode threshold voltage Vthres for the parasitic diode between the third and fourth terminal. The voltage difference Vdif may be less than 0.4 V. For one or more drive transistors, the voltage difference Vdif may be less than 0.4 V, such as less than 0.3 V, less than 0.2 V. In one or more embodiments, the voltage difference Vdif may be less than or equal to 0 V. In an embodiment, where the fourth terminals are wired to the largest power supply voltage, it is ensured that Vdif is less than or equal to 0V irrespective of the mode of operation.
- In one or more output cells, e.g. the first output cell, the fourth terminal of the second transistor and the fourth terminal of the third transistor may be wired to the power supply pin carrying the largest voltage. The fourth terminal of the second transistor and the fourth terminal of the third transistor may be wired to a common terminal. The first terminal of the third transistor may be the common terminal. Thereby undesired leakage currents may be avoided when the output cells operate in the mode with the smallest voltage amplitude on the output pin.
- The second terminals of the second transistor and the third transistor may be connected to the output of a logical circuit of the first output cell for selecting between a first mode (second transistor active) and a second mode (third transistor active) of operation.
- One or more output cells of the integrated circuit may thus be adapted to be able to operate in a first mode wherein the voltage signal on the output pin switches between VGND * and V1 *, and in a second mode wherein the voltage signal on the output pin switches between VGND* and V2 *, depending on a control signal applied to the at least one voltage select pin.
- The integrated circuit may comprise a third power rail adapted to carry a third voltage V3, and the first output cell may comprises a fourth transistor connected between the output pin and a third power supply pin connected to the third power rail.
- The fourth transistor has a first terminal, a second terminal, a third terminal and a fourth terminal. The fourth terminal may be wired to the common terminal. The first output cell may be adapted to operate according to a third mode wherein the voltage on the first output pin has a third amplitude depending on a control signal applied to the at least one voltage select pin. The first terminal of the fourth transistor may be wired to the third power supply pin, and the third terminal of the fourth transistor may be wired to the output pin. The second terminal of the fourth transistor may be wired to a logical circuit to enable activation of the fourth transistor in a third mode of operation, wherein the voltage signal on the output pin switches between VGND* and V3*, depending on a control signal applied to the at least one voltage select pin.
- One or more output cells of the integrated circuit may comprise a logical circuit having input connected to the at least one voltage select pin and the data pin, and output connected to the second terminals of the drive transistors (second, third and fourth transistor if present) for selecting between the modes by selectively activating the second, third and fourth transistor.
- The integrated circuit may comprise at least one level shifter including a first level shifter between the data pin and the second terminals of the first, second and third transistor for adapting a data signal to correct signal amplitudes. The first level shifter may be arranged between the data pin and the logical circuit and/or between the logical circuit and the second terminals of the drive transistors.
- The at least one level shifter may include a second level shifter between the at least one voltage select pin and the logical circuit for adapting a voltage select signal to correct signal amplitudes for the logical circuit.
- The integrated circuit may comprise a core connected to the first output cell, wherein the core is adapted to perform signal processing for a hearing device.
-
Fig. 1 shows ahearing device 2. Thehearing device 2 comprises anaudio input interface 4 for receiving audio signal(s) in electronic and/or acoustic form. Theaudio input interface 4 may comprise one or more microphones, e.g. a first microphone and/or a second microphone, and/or a telecoil. Theaudio input interface 4 may comprise an audio connector or audio input boot for coupling external audiosources to thehearing device 2. Theaudio input interface 4 is connected to anAD converter unit 6 which is connected to a signal processing unit orintegrated circuit 8. TheAD converter unit 6 converts or transforms audio signals from theaudio input interface 4 and send the digital audio signal(s) to thesignal processing unit 8 for processing, e.g. in order to compensate for hearing loss or other hearing impairment. Thesignal processing unit 8 may send control signals to theAD converter unit 6 to configure and control operation of theAD converter unit 6. Thesignal processing unit 8 may be connected to auser interface 10 in order to allow a user, a computer or another hearing device to communicate with the hearing device, e.g. during configuration and/or during use of the hearing aid. Theuser interface 10 may comprise a push button and/or a connector for a data cable in order to couple the hearing device to e.g. a computer during configuration or another hearing device. Thehearing device 2 may comprise amemory unit 12 connected to thesignal processing unit 8 for storing data or hearing aid parameters, and thehearing device 2 may optionally comprise aradio unit 14 connected to thesignal processing unit 8 and adapted for receiving and/or transmitting radio signals, e.g. in order to enable thehearing device 2 to communicate wirelessly with another device, such as a hearing device and/or a wireless interface. TheAD converter unit 6 may be embedded in the signal processing unit orintegrated circuit 8. Thehearing device 2 may comprise a receiver orloudspeaker 16 connected to thesignal processing unit 8 for emitting audio signals to a user. -
Fig. 2 shows an exemplary signal processing unit orintegrated circuit 8 according to the present invention. Theintegrated circuit 8 comprises aprocessing core 18 e.g. for digital signal processing of digital audio signals from anAD converter 6. Theprocessing core 18 is connected to a number of communication cells or peripheral units for communication with other units of the hearing device, e.g. theAD converter unit 6,user interface 10,memory unit 12 and/orradio unit 14. - The
integrated circuit 8 comprises a number ofcommunication cells processing core 18. A communication cell may be configured to implement different communication protocols depending on the unit to be connected thereto. A first and/or second output cell or IO cell may be implemented in each or one or more of thecommunication cells clock management cell 22 optionally comprising one or more output cells or IO cells as described herein. -
Fig. 3 illustrates an exemplary output cell according to the invention, e.g. a first and/or a second output cell which for example may be implemented in one or more of the communication cells of the integrated circuit inFig. 2 . Theoutput cell 106 has aground pin 108 connected to aground rail 50 of the integrated circuit, a firstpower supply pin 110 connected to afirst power rail 52 of the integrated circuit adapted to carry a first voltage V1, a secondpower supply pin 112 connected to asecond power rail 54 of the integrated circuit adapted to carry a second voltage V2, adata pin 114, at least one voltageselect pin 116 and anoutput pin 118 wired to thefirst output pad 104. Theoutput cell 106 further comprises a corepower supply pin 120 connected to thecore power rail 56. Thefirst output pad 104 may be embedded in theoutput cell 106 as illustrated or be arranged outside the output cell in the integrated circuit. - The
output cell 106, i.e. the first output cell, is adapted to operate according to a first mode wherein the voltage on theoutput pin 118 has a first amplitude V1 *, and according to a second mode wherein the voltage on the first output pin has a second amplitude V2*, larger than the first amplitude depending on a control signal applied to the at least one voltageselect pin 116. Theoutput cell 106 comprises afirst transistor 122, asecond transistor 124 and athird transistor 126 having respectivefirst terminals second terminals third terminals fourth terminals logical circuit 136 is arranged between the at least one voltageselect pin 116 and thesecond terminals first level shifter 138 coupled between thedata pin 114 and thesecond terminals second level shifter 140 is coupled between the at least one voltageselect pin 116 and thesecond terminals level shifters power supply pin 112 and the corepower supply pin 120. The at least one voltageselect pin 116 may comprise a first voltage select pin and a second voltage select pin in order to select between more than two different operating modes of the output cell. Each transistor has an intrinsic parasitic diode between the third terminal and the fourth terminal which is also illustrated inFig. 3 . The coupling of fourth terminals eliminate or reduce parasitic currents between fourth and third terminals of the drive transistors. -
- 2
- hearing device
- 4
- audio input interface
- 6
- analog-digital (AD) converter unit
- 8
- signal processing unit
- 10
- user interface
- 12
- memory unit
- 14
- radio unit
- 16
- loudspeaker/receiver
- 18
- core
- 20
- communication cell (Master interface)
- 22
- clock management unit
- 24
- audio input/output
- 26
- H-bridge
- 28
- communication cell (Wireless controller)
- 30
- communication cell (IIC Master)
- 32
- communication cell (IIS interface)
- 34
- communication cell (SPI Master)
- 36
- communication cell (Com interface)
- 38
- communication cell (IIC slave)
- 50
- ground rail
- 52
- first power rail
- 54
- second power rail
- 56
- core power rail
- 104
- first output pad
- 106
- output cell
- 108
- ground pin
- 110
- first power supply pin
- 112
- second power supply pin
- 114
- data pin
- 116
- voltage select pin(s)
- 118
- output pin or output node
- 120
- core power supply pin
- 122
- first transistor
- 124
- second transistor
- 126
- third transistor
- 128A, 128B, 128C
- first terminal
- 130A, 130B, 130C
- second terminal
- 132A, 132B, 132C
- third terminal
- 134A, 134B, 134C
- fourth terminal
- 136
- logical circuit
- 138
- first level shifter
- 140
- second level shifter
Claims (12)
- An integrated circuit for a hearing device, wherein the integrated circuit comprises a ground rail (50), a first power rail (52) adapted to carry a first voltage (V1), and a second power rail (54) adapted to carry a second voltage (V2), the integrated circuit comprising a number of pads for connecting the integrated circuit to other components, the number of pads including at least one output pad including a first output pad (104), wherein the integrated circuit comprises at least one output cell including a first output cell (106) having a ground pin (108) connected to the ground rail (50), a first power supply pin (110) connected to the first power rail (52), a second power supply pin (112) connected to the second power rail (54), a data pin (114), at least one voltage select pin (116) and an output pin (118) wired to the first output pad, wherein the first output cell comprises at least three transistors including a first transistor (122), a second transistor (124), and a third transistor (126), each transistor having a first terminal, a second terminal, a third terminal and a fourth terminal, and wherein the first terminal (128A) of the first transistor is wired to the ground pin (108), the second terminal (130A) of the first transistor is connected to the data pin (114), optionally via a level shifter, the third terminal (132A) is wired to the output pin, and the fourth terminal (134A) is wired to the first terminal, wherein the first output cell is adapted to operate according to a first mode wherein the voltage on the output pin (118) has a first amplitude, and according to a second mode wherein the voltage on the output pin (118) has a second amplitude larger than the first amplitude depending on a control signal applied to the at least one voltage select pin, and wherein the fourth terminal of the second transistor and the fourth terminal of the third transistor are wired to a common terminal.
- An integrated circuit according to claim 1, wherein the fourth terminal (134B) of the second transistor and the fourth terminal (134C) of the third transistor is wired to the power supply pin carrying the largest voltage.
- An integrated circuit according to any of claims 1-2, wherein the first terminal (128C) of the third transistor is wired to the second power supply pin and wherein the first terminal (128C) of the third transistor is the common terminal.
- An integrated circuit according to any of claims 1-3, wherein the first terminal (128B) of the second transistor is wired to the first power supply pin.
- An integrated circuit according to any of claims 1-4, wherein the third terminal (132B, 132C) of the second transistor and the third transistor are wired to the output pin (118).
- An integrated circuit according to any of the claims 1-5, wherein the integrated circuit comprises a third power rail adapted to carry a third voltage (V3), and wherein the first output cell comprises a fourth transistor connected between the output pin and a third power supply pin, the third power supply pin being connected to the third power rail.
- An integrated circuit according to claim 6, wherein the fourth transistor has a first terminal, a second terminal, a third terminal and a fourth terminal, wherein the fourth terminal is wired to the common terminal, and wherein the first output cell is adapted to operate according to a third mode wherein the voltage on the first output pin has a third amplitude depending on a control signal applied to the at least one voltage select pin.
- An integrated circuit according to claim 7, wherein the first terminal of the fourth transistor is wired to the third power supply pin and the third terminal of the fourth transistor is wired to the output pin.
- An integrated circuit according to any of the claims 1-8, wherein the first output cell comprises a logical circuit having input connected to the at least one voltage select pin and the data pin, and output connected to the second terminals of the second, third and fourth transistor if present, for selecting between the modes by selectively activating the second, third and fourth transistor, respectively.
- An integrated circuit according to any of the preceding claims, wherein the integrated circuit comprises a core (18) connected to the first output cell, wherein the core is adapted to perform signal processing for a hearing device.
- A hearing device comprising an integrated circuit according to any of the preceding claims.
- A method for manufacture of an integrated circuit, comprising- providing at least one output cell having an output pin and at least two drive transistors each having a first terminal connected to a respective first and a second power supply pin of the output cell, a second terminal, a third terminal connected to the output pin and a fourth terminal, wherein the fourth terminal of the two drive transistors are wired such that the voltage difference between the third and fourth terminal of the respective drive transistors is less than the diode threshold voltage between the third and fourth terminal, and wherein the fourth terminals of the at least two drive transistors are wired to a common terminal.
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DK11187140.6T DK2587484T3 (en) | 2011-10-28 | 2011-10-28 | Integrated circuit with configurable output cell |
EP20110187140 EP2587484B1 (en) | 2011-10-28 | 2011-10-28 | Integrated circuit with configurable output cell |
US13/304,991 US8494173B2 (en) | 2011-10-28 | 2011-11-28 | Integrated circuit with configurable output cell |
JP2012236675A JP5734258B2 (en) | 2011-10-28 | 2012-10-26 | Integrated circuit with configurable output cells |
CN201210548456.2A CN103260122B (en) | 2011-10-28 | 2012-10-29 | Integrated circuit with configurable output cell and manufacturing method and hearing device thereof |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP20110187140 EP2587484B1 (en) | 2011-10-28 | 2011-10-28 | Integrated circuit with configurable output cell |
Publications (2)
Publication Number | Publication Date |
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EP2587484A1 EP2587484A1 (en) | 2013-05-01 |
EP2587484B1 true EP2587484B1 (en) | 2015-03-18 |
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EP20110187140 Active EP2587484B1 (en) | 2011-10-28 | 2011-10-28 | Integrated circuit with configurable output cell |
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EP (1) | EP2587484B1 (en) |
DK (1) | DK2587484T3 (en) |
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CN109428587B (en) * | 2017-08-31 | 2023-10-27 | 恩智浦美国有限公司 | Level shifter standby unit |
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US6147511A (en) * | 1996-05-28 | 2000-11-14 | Altera Corporation | Overvoltage-tolerant interface for integrated circuits |
US6346846B1 (en) * | 1999-12-17 | 2002-02-12 | International Business Machines Corporation | Methods and apparatus for blowing and sensing antifuses |
US6630724B1 (en) * | 2000-08-31 | 2003-10-07 | Micron Technology, Inc. | Gate dielectric antifuse circuits and methods for operating same |
US20080170731A1 (en) * | 2007-01-12 | 2008-07-17 | Siemens Hearing Instruments Inc. | Hearing Aid Momentary Switch Or Joystick As A Multifunction Acoustic Control |
AU2010347004B2 (en) * | 2010-02-26 | 2013-11-28 | Widex A/S | A hearing aid with adaptive bulk biasing power management |
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2011
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EP2587484A1 (en) | 2013-05-01 |
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