EP2572384A1

EP2572384A1 - Optoelectronic semiconductor chip and method for producing same

Info

Publication number: EP2572384A1
Application number: EP11743182A
Authority: EP
Inventors: Werner Bergbauer; Lutz Höppel; Philipp Drechsel; Christopher KÖLPER; Martin Strassburg; Patrick Rode
Original assignee: Osram Opto Semiconductors GmbH
Current assignee: Ams Osram International GmbH
Priority date: 2010-05-18
Filing date: 2011-04-29
Publication date: 2013-03-27
Also published as: CN102893407B; US20130193450A1; KR20130118217A; DE102010020789B4; CN102893407A; DE102010020789A1; WO2011144199A1; US8884311B2

Abstract

The invention relates to an optoelectronic semiconductor chip (10), which has a stack (2) of semiconductor layers and a radiation outlet surface or radiation inlet surface (3). The stack (2) of semiconductor layers comprises an active layer (2a), which is suitable for producing or receiving electromagnetic radiation. A plurality of nanostructures (4) that at least partially have at least one sub-structure (41, 42) is arranged in the stack (2) of semiconductor layers and/or on the radiation outlet surface or radiation inlet surface (3). The invention further relates to a method for producing such an optoelectronic semiconductor chip (10).

Description

description

Optoelectronic semiconductor chip and method for its production

The invention relates to an optoelectronic

Semiconductor chip comprising a semiconductor layer stack and a radiation exit or radiation entrance surface and a method for its production.

This patent application claims the priority of German patent application 10 2010 020 789.6, the disclosure of which is hereby incorporated by reference. The performance of radiation-emitting semiconductor chips, such as LEDs, or radiation-receiving ends

Semiconductor chips, such as sensors or detectors, among others, are influenced by the use of a substrate on which the semiconductor layers of the

Semiconductor chips are grown. In particular, the substrate has compared to the semiconductor layers of

Semiconductor chips mostly significant differences in

Expansion coefficients and / or in the grid parameters. This can cause lattice dislocations and point defects that are non-radiative or non-radiative

Recombination centers lead, whereby the internal and external quantum efficiency of the semiconductor chips can be adversely affected. In addition, leakage current paths can thus arise in the semiconductor chip.

To improve the Lichtaus- or light coupling from or into the semiconductor chip, it is known, the angle of the incident radiation at the interface between Semiconductor chip and environment to keep smaller than the critical angle of total reflection. This will be

For example, the surface of the semiconductor chip with a wet chemical etching process, for example using KOH (potassium hydroxide) treated, whereby special three-dimensional structures can be formed on the surface, but do not lead to a maximum and angle-independent radiation emission due to the selective chemical reaction.

To optimize the radiation emission of the semiconductor chip surface structures are advantageous, which have a special shape and size. With the conventionally

used manufacturing process for the production of

Surface structures, such as KOH surface treatment, are the shape and size of the surface

Surface structures, however, set limits.

It is an object of the present application, a

Provide semiconductor chip having reduced lattice dislocations and / or point defects, which can be achieved in an advantageous manner, an improved efficiency of the semiconductor chip. It is also the task of the present

Application to provide an improved manufacturing method for such a semiconductor chip.

These tasks are among others by a

Semiconductor chip having the features of claim 1 and by a method for producing such a semiconductor chip having the features of claim 12 solved. advantageous

Further developments of the semiconductor chip and the method for its production are the subject of the dependent claims. In one development, the optoelectronic semiconductor chip has a semiconductor layer stack and a

Radiation exit surface or inlet surface on. The semiconductor layer stack has an active layer which is suitable for generating or receiving electromagnetic radiation. On the radiation exit surface or

Radiation entrance surface is a plurality of

Arranged nanostructures, which at least partially have at least one substructure. Alternatively or additionally, a plurality of nanostructures are arranged in the semiconductor layer stack, which at least partially at least one

Substructure have.

In this case, it is not absolutely necessary for each nanostructure of the radiation exit or radiation entrance surface and / or in the semiconductor layer stack to have a substructure. In addition, it is possible for a nanostructure to have a plurality of substructures. The substructures can be targeted or arbitrary in the nanostructures

be arranged. The shape and size of the substructures is preferably dependent on the desired optoelectronic and chemical properties of the semiconductor layer stack.

The substructures in the nanostructures preferably increase the surface area of the nanostructures in comparison to nanostructures without integrated substructures. In addition, the adverse consequences due to

Lattice dislocations and point defects can be reduced as an indirect proportionality

between effects of the lattice dislocations or point defects and the surface exists. For example, dislocations or defects can cancel each other due to the increased surface. Due to the increased Surface, the number of non-radiating or non-receiving recombination centers can be reduced, which advantageously improves the internal and external quantum efficiency of the semiconductor chips. In addition, thus leakage current paths in the semiconductor chip, due to

Lattice dislocations or point defects can be reduced. Overall, the advantage can be

Significantly reduce the dislocation density of the layers in the semiconductor chip.

By using nanostructures with integrated substructures, a growth substrate may be advantageous

Use, the coefficient of expansion of

Expansion coefficient of the semiconductor layers deviates.

In particular, non-crystalline surfaces, such as, for example, amorphous surfaces, can be used. In addition, the detachment of the substrate during the simplifies

Manufacturing process of the semiconductor chip advantageous. An optoelectronic semiconductor chip is in particular a

Semiconductor chip that enables the conversion of electronically generated data or energy into light emission or

vice versa. For example, the optoelectronic

Semiconductor chip a radiation-emitting or

radiation-receiving semiconductor chip.

In one development, the at least one substructure is a recess, for example a depression, a hole, a groove or an opening on a surface of a

Nanostructure or within a nanostructure. Furthermore, the at least one substructure can also be an elevation, for example a web or a convexity. The

Substructure is preferably according to formed electro-optical and chemical properties of the semiconductor layer stack.

In a further development, the nanostructures are arranged in a periodic pattern. Preferably, the

Nanostructures formed during a growth process in this periodic pattern. Is the majority of

Nanostructures on the radiation exit surface or

Radiation entrance surface arranged so has the

Radiation exit surface or radiation entrance surface in this way a regular pattern of nanostructures. This can advantageously be an angle independent

Radiation emission can be achieved, which results in a favorable homogeneous radiation characteristic. In a

Continuing education is the periodic arrangement of

Nanostructures on the radiation exit surface or

Radiation inlet surface arranged specifically so that a radiation shaping is generated. Advantageously, no complex post-processing steps with regard to the shaping of the nanostructures depending on the desired radiation form are necessary.

Is the plurality of nanostructures alternative or

additionally arranged in the semiconductor layer stack, this means that at least one layer of the

Semiconductor layer stack may have the nanostructures. By way of example, the semiconductor layer stack with the active layer can be arranged on a substrate, for example a growth or carrier substrate, wherein the nanostructures can be arranged between the substrate and the active layer so that the active layer in turn can be interposed between the nanostructures and the radiation exit area or surface. inlet surface is arranged. This can be done with Advantage a reduction of defects in the active layer can be achieved.

Alternatively, the active layer may also be in the

Nanostructures be arranged. This may mean, in particular, that the semiconductor layer stack or a part thereof including the active layer may be formed as a plurality of nanostructures. Due to the substructures in the nanostructures, the surfaces of the nanostructures can advantageously be enlarged, so that possible

occurring lattice defects in the nanostructures along the enlarged surfaces and so advantageously a reduction of lattice defects in the active layer

can be achieved within the nanostructures. Furthermore, the active layer can advantageously also be increased by the substructure in a nanostructure with active layer.

Are the nanostructures in the semiconductor layer stack

arranged, for example, on one

Buffer layer grown or merged with a buffer layer. Alternatively, the nanostructures may also be grown or deposited directly on a substrate without having a buffer layer between the substrate and the nanostructures. Furthermore, one or more layers of the nanostructures may also be provided over the nanostructures

Semiconductor layer stack to be grown or fused to the nanostructures. In a development, the nanostructures each have a lateral extent of at most 5 μm. Especially

Preferably, the nanostructures each have a lateral Expansion of at most 2 microns or even more than 1 micron on.

The nanostructures are preferably in minimal

Sized trained, while at the same time

preferably almost exact vertical flanks of

Nanostructures are achieved. For this purpose, the

Nanostructures preferably in forming the

Semiconductor layer stack and / or on the

Radiation exit surface or inlet surface grown.

In a further development, the nanostructures have a

Plurality of substructures, preferably

have different sizes and / or shapes. The nanostructures can each have one _. Have substructure, wherein the size and / or shape of the substructures may differ between the individual nanostructures. Additionally or alternatively, a nanostructure may include a plurality of

Substructures, wherein the substructures of a nanostructure may have a different size and / or shape to each other.

In a development, the semiconductor chip is a

Thin-film chip. As a thin-film chip is considered in the context of the application, a semiconductor chip, during its production, the

Growth substrate on which the semiconductor layer stack has been epitaxially grown, for example, is preferably completely detached. In a further development, the nanostructures are

three-dimensional structures. In other words, the nanostructures are spatially formed. For example, the Nanostructures formed pyramidal or rod-shaped.

In one development, the semiconductor chip is an LED {light-emitting diode) or a sensor. So can the

Semiconductor chip, for example, be an LED or a sensor having nanostructures, which are formed rod-shaped. Alternatively or additionally, the semiconductor chip may also have, for example, pyramidal nanostructures, as explained below.

The semiconductor chip is preferably based on a

Nitride compound semiconductors, phosphide compound semiconductors and / or arsenide compound semiconductors. This means in the present context that the active

Epitaxial layer sequence or at least one layer thereof comprises a nitride, phosphide and / or arsenide III / V compound material. In this case, the bonding material one or more dopants and additional components

that have the characteristic physical

Essentially, the properties of the connection material do not change.

The semiconductor layer stack is preferably based on the AlInGaN material system.

In a further development, the nanostructures are on the

Radiation exit surface or entrance surface arranged in a regular pattern and pyramidal

educated. The nanostructures each have at least one substructure, which is a recess and is arranged in the center of the pyramid. The pyramid thus has no

Pyramid tip on. Instead of the Pyramidenspitze is a Substructure arranged, which is in particular a recess. This can be beneficial to the efficiency of the

Semiconductor chips improve, as occurring

Lattice dislocations and / or point defects can be counteracted due to the increased surface area.

A method for producing an optoelectronic

Semiconductor chips has the following steps:

Forming a semiconductor layer stack comprising an active layer suitable for generating or receiving electromagnetic radiation,

- Forming nanostructures on the

Semiconductor layer stack or in the

Semiconductor layer stack,

- Forming at least one substructure at least

partly in the nanostructures.

In particular, the formation of the nanostructures can

simultaneously with the formation of the at least one

Substructure at least partially in the nanostructures

respectively. Will the nanostructures in the

Semiconductor layer stack formed, the formation of the semiconductor layer stack may at least partially in the nanostructures simultaneously with the formation of the nanostructures and forming the at least one substructure

respectively .

The features mentioned in connection with the optoelectronic semiconductor chip also apply to the method and

vice versa .

The production method according to the invention therefore not only has the production of nanostructures on one Radiation exit surface or -eintrittsflache of

Semiconductor chips to improve the radiation extraction or in the semiconductor layer stack on. In addition, substructures are formed in the nanostructures, which advantageously increase the surface of the nanostructures, so that occurring effects of existing lattice dislocations or point defects can be counteracted.

In a further development, the substructure becomes the

Surface of the nanostructure enlarged, causing

Advantageously occurring lattice defects

(Dislocations) and defects can be effectively counteracted. In a further development, the nanostructures by means of

MOCVD (metal organic vapor phase epitaxy) produced. By means of such a production method, periodically arranged nanostructures can preferably be realized, these being produced by means of this method with minimal

Dimensioning can be formed, and at the same time almost vertical side surfaces of the nanostructures can be achieved. In addition, specially desired

Aspect ratios of the nanostructures can be adjusted and controlled in a targeted manner. Post-processing processes for the exact formation of the desired or specific shape and size of the nanostructures are thus not required.

Preferably, the shape and size of the nanostructures and substructures are adjusted by means of such a method depending on the optoelectronic and chemical properties of the semiconductor layer stack, whereby

advantageously, for example, an optimized and

angle-independent radiation emission or detection of the semiconductor chip can be achieved. As an alternative to a manufacturing process based on MOCVD, the nanostructures can also be processed by MBE

(Molecular Beam Epitaxy) or LPE (Liquid Phase Epitaxy).

In a development, a growth substrate on which the semiconductor layer stack has been grown is at least partially or completely detached.

Further advantages and advantageous developments of

Invention will become apparent from the embodiments described below in connection with FIGS. 1A to 4B.

Show it:

Figures 1A to 1C are schematic cross sections of

Semiconductor chips according to several embodiments,

FIG. 1D shows a schematic representation of a nanostructure according to a further exemplary embodiment,

FIGS. 2A to 2C show a schematic view of a nanostructure according to an exemplary embodiment, wherein the nanostructure can be used for example in one of the semiconductor chips according to FIGS. 1A to 1C,

FIGS. 3A and 3B each show a schematic view of a nanostructure according to a further exemplary embodiment, wherein the nanostructure can be used, for example, in the semiconductor chip according to FIG. 1A, and FIGS. 4A and 4B are views, respectively, of a radiation output or input surface of a semiconductor chip according to a further embodiment. In the figures, the same or the same effect

Each component be provided with the same reference numerals. The illustrated components and their

Size relationships with each other are basically not to be considered as true to scale, but rather individual

Components, such as layers, structures,

Components and areas to be shown exaggerated thick or large dimensions for better presentation and / or for better understanding. FIG. 1A shows an embodiment of a semiconductor chip 10 in cross-section. The semiconductor chip 10 has a substrate 1 on which a plurality of semiconductor layers is arranged. The semiconductor layers form one

Semiconductor layer stack 2 having an active layer 2a for generation or reception

electromagnetic radiation is suitable. Of the

Semiconductor chip 10 further has a radiation exit surface or entrance surface 3 on which nanostructures 4

are arranged.

The semiconductor chip 10 is capable of emitting or receiving radiation. For example, the semiconductor chip 10 is an LED or a sensor. The semiconductor layer stack 2 is based on the

Material system AlInGaN. The substrate 1 of the semiconductor chip 10 is, for example, a growth substrate that is suitable for growing the semiconductor layers of the semiconductor layer stack 2. Furthermore, the substrate 1 may be a carrier substrate. In this case, the growth substrate is in the manufacturing process of

Semiconductor chips 10 have been at least partially or preferably completely detached from the semiconductor layer stack 2. Such a semiconductor chip 10 is also known to the person skilled in the art as a thin-film chip.

The substrate 1 may have a different lattice parameter and / or a different lattice parameter than the semiconductor layers of the semiconductor layer stack 2

Have expansion coefficients. Thereby can

Dislocations and point defects arise that can form non-radiative or non-recapturing recombination centers, which can reduce internal and external quantum efficiency. Furthermore, such defects can lead to a leakage current path in the semiconductor chip.

To these conventionally occurring disadvantages

To counter, a plurality of nanostructures 4 is arranged on the radiation exit surface or radiation entrance surface 3. The nanostructures 4 advantageously increase the surface of the radiation exit surface or

Radiation entrance surface 3. Furthermore, by de

Enlargement of the surface to the negative effects of

Dislocations, dislocations and point defects

This property can advantageously also be independent of the surface on which the nanostructures are applied. In particular, the dislocation density can be significantly reduced, which advantageously increases the internal and external quantum efficiency. In order to increase the surface, substructures are additionally arranged in the nanostructures (not shown), which are explained in more detail in connection with FIGS. 2 to 4.

Advantageously, due to the nanostructures with integrated substructures, the proportion of the radiation emitted, for example, by the active layer 2a and reflected back into the semiconductor layer stack at the interface between the semiconductor layer stack 2 and the surrounding area can be reduced due to the change in the incident angle of the radiation caused thereby, so that the efficiency of the semiconductor chip further improves.

In particular, at the interface of the semiconductor chip 10, a jump of the refractive indices occurs from the material of the semiconductor chip

Semiconductor chips 10 on the one hand to the surrounding material on the other. This leads to a refraction of the

Radiation at the transition from the semiconductor chip 10 in the

Surroundings. Depending on the angle at which a light beam strikes the interface, total reflection may occur. Due to the parallel surface of the

Semiconductor chips 10 hits the reflected light beam at the same angle on the opposite interface, so that there total reflection occurs. The consequence is that the light beam thus does not contribute to the light emission of the

Can contribute semiconductor chips 10. Due to the fact that nanostructures 4 are provided on the radiation exit surface, the angle is changed in which a light beam on the

Surface hits, which advantageously increases the efficiency. The nanostructures 4 are arranged in a periodic pattern on the radiation exit or radiation entrance surface 3. Due to this periodic and uniform arrangement is advantageously an angle independent

Light emission instead, so that the semiconductor chip 10 has a homogeneous emission characteristic.

Alternatively, the periodic arrangement of the

Nanostructures 4 are formed selectively jet-forming properties, without requiring subsequent treatment steps of the radiation exit surface or -eintrittstlache 3 are necessary.

The nanostructures 4 have a lateral extent of at most 5 and more preferably of at most 2 μm. The lateral extent of the nanostructures 4 is in particular parallel to the radiation exit surface or radiation entrance surface 3 of the semiconductor chip 10

extending extent.

A semiconductor chip 10 has nanostructures 4 on the

Radiation exit or inlet surface 3, which have minimal dimensions and in one

arranged regular pattern, whereby dislocations and point defects can be counteracted in the semiconductor chip 10, whereby the efficiency of these semiconductor chips 10 increases advantageously.

The nanostructures 4 are preferably three-dimensional

Structures. For example, the nanostructures are 4

pyramidal or rod-shaped. In addition, at least a part of the nanostructures 4 has at least one Substructure up. In this case, a nanostructure 4 can have a plurality of substructures.

FIG. 1B shows a semiconductor chip 10 according to a further exemplary embodiment, which has a plurality of nanostructures 4 in the semiconductor layer stack 2 in comparison with the previous exemplary embodiment. The active layer 2a is between the nanostructures 4 and the

Radiation exit or -eintrittsflache 3 arranged.

The nanostructures 4 are grown on a buffer layer 5 made of AlInGaN and have a lateral extent of at most 5 μm and particularly preferably of at most 2 μm.

The nanostructures 4 are in the form of columns or rods, for example with a hexagonal cross section, and at least partially have substructures 42, which are formed as depressions, in particular as tubular depressions. The nanostructures 4 point in the process

different sizes and / or shapes. By the

Nanostructures 4 with the substructures 42 can advantageously be reduced lattice defects in the active layer 2a. The semiconductor chip 10 of FIG. 1B may have further features which are described in connection with the embodiment of FIG. 1A. In particular, the

Semiconductor chip 10 according to FIG IB also have nanostructures 4 on the radiation exit or -eintrittsflache 3. Alternatively, the radiation exit surface or - entry surface 3, for example, be roughened. FIG. 1C shows a further exemplary embodiment of a semiconductor chip 10 which, in contrast to the previous exemplary embodiment, has no buffer layer. The

Nanostructures 4 with the substructures 42 are grown or deployed directly on the substrate 1 during the formation of the semiconductor layer stack 2.

Alternatively to the ones shown in FIGS. 1B and 1C

Embodiments, the active layer 2a also

be arranged within the nanostructures 4. FIG. 1D shows an exemplary embodiment of such a nanostructure 4. The semiconductor layer stack 2 in one

Semiconductor chip may have a plurality of such nanostructures 4 with different sizes and / or shapes.

The nanostructure 4 is rod-shaped and has, for example, a hexagonal cross-section. Furthermore, the nanostructure 4 has a substructure 42 in the form of a depression or recess, by means of which the surface of the nanostructure 4 is enlarged. This makes it possible that possible in the nanostructure 4 existing

Lattice defects along the enlarged surface and thus the active layer 2a has a reduced defect density. Furthermore, the active layer 2a in the

Nanostruktur 4 are enlarged.

Further exemplary embodiments of nanostructures 4 are shown in FIGS. 2A to 4B. In particular, nanostructures 4 are shown in FIGS. 2A to 3A, each having a bottom side 43 on the radiation exit or entry surface 3 of the semiconductor chips 10 in accordance with FIGS

Embodiments of Figures 1A to IC can be arranged. FIG. 2A shows a rod-shaped nanostructure 4

represented, which has a substructure 41. The

Substructure 41 is formed as an elongated elevation or elevation, which in the illustration shown in FIG

Standing out. In this case, the elevation 41 leads along the rod-shaped nanostructure 4. In particular, the surface of the nanostructure can be increased by the substructure 41, as a result of which the effects of the dislocations and

Point defects can be counteracted in the semiconductor chip.

The substructure 41 is targeted according to the optoelectronic and chemical properties of the

Semiconductor layer stack 2 is formed. In this case, the substructure 41 does not necessarily have to cover the entire height of the

Nanostruktur 4 extend. Rather, the substructure 41 may be formed only in a partial region of the nanostructure 4. Rod-shaped nanostructures on the radiation exit or -eintrittsflache can be used for example in combination with semiconductor chips designed as sensors. In this case, the radiation entrance surface of such a sensor, as shown in Figure 1, a plurality of such rod-shaped nanostructures 4, which are arranged in a regular pattern.

Alternatively, they can also be implemented as LEDs

Semiconductor chips have such rod-shaped nanostructures.

Such nanostructures can be produced, for example, by means of an MOCVD process. Aftercare of the Radiation exit and -eintrittsflache or the nanostructures are not necessary. In particular, by means of such a MOCVD method

Nanostructures are produced with integrated substructures, which have small dimensions, have almost exact side surfaces and are arranged in a regular pattern, which improves the efficiency of such chips with advantage. Alternatively, the nanostructures can also be produced in a self-organized growth process, such as MBE, whereby, for example, non-regular

Nanostructures are available. The nanostructure 4 shown in FIG

Compared to the nanostructures of Figure 2A no survey as a substructure. The substructure of FIG. 2B is

in particular designed as a recess 42, which projects in the illustration shown in the plane of the drawing. In this case, the nanostructure 4 has a plurality of substructures 42, in particular a plurality of recesses, which may have a different size and / or shape.

In particular, one of the substructures 42 is thinner than the other one. The shape and size of the substructures are formed according to the optoelectronic and chemical properties of the semiconductor layer stack.

Incidentally, the embodiment of Figure 2B may also have features of the embodiment of Figure 2A.

FIG. 2C shows a nanostructure 4 which has a plurality of substructures 41, 42, wherein the

Substructures as a survey 41 and as a recess 42nd can be trained. In particular, between two

Elevations 41 a recess 42 arranged. As a result, the surface of the nanostructure 4 can advantageously be increased, which may have an advantageous effect on the efficiency of the semiconductor chips having such nanostructures.

Incidentally, the embodiment of Figure 2C may include features of the embodiments of Figures 2A and 2b. The nanostructures of FIGS. 2A to 2C may, instead of the cubic shape or a columnar or rod-like shape with a quadrangular cross section, also have a columnar or rod-like shape with a polygonal, in particular hexagonal, cross section in a sectional plane perpendicular to the plane of the drawing, so that the substructures 41 and / or 42 along the

Side surfaces of such nanostructures are formed.

FIGS. 3A and 3B show further examples of

Nanostructures 4 shown, as used for example in semiconductor chips of the embodiment of Figure 1

Can be used.

The nanostructure 4 of Figure 3A has a pyramidal shape, wherein in the embodiment of Figure 3A, the

Pyramid tip is flattened. In particular, the

Nanostruktur 4 formed on the top and bottom hexagonal. Alternatively, the top and / or

Underside also rounded corners or a round

Have cross-section.

In the flattened region of the nanostructure 4 are

Substructures formed as recesses 42. The Substructures 42 may have a different size and / or shape. By virtue of the substructures 42, the surface of the nanostructure 4 advantageously increases. As a result of the production process of the nanostructure 4 by means of an MOCVD process, it is advantageously possible to obtain virtually smooth surfaces

Side surfaces are achieved. Furthermore, such

Nanostructures 4 a lateral extent of at most 5 microns, preferably of at most 2 microns and more preferably of at most 1 micron on. Such nanostructures 4 are on the radiation exit surface or -eintrittsflache of

Semiconductor chips according to the embodiment of Figure 1 arranged in a regular pattern, as shown for example in Figures 4A and 4B.

FIG. 3B shows a plan view of a nanostructure 4 that is similar to the embodiment of FIG. 3A. The nanostructure 4 has a hexagonal pyramidal shape, which is a substructure 42 in the center of the pyramid

having. The substructure 42 is in particular a

Recess. The pyramidal nanostructure 4 accordingly has no pyramid tip. Instead of the pyramid tip, a recess 42 is formed. This advantageously improves the radiation efficiency of the semiconductor chips, which has a regular pattern of nanostructures 4 formed in this way on the radiation entrance surface or exit surface. In particular, such a homogeneous

Abstrahlcharakteristik the semiconductor chips are made possible. In Figure 4A is an oblique view of a

Radiation exit surface or entrance surface of a

Semiconductor chips, as shown for example in Figure 1 shown. On the radiation exit or Radiation entrance surface 3 is arranged a plurality of nanostructures 4, each having a pyramidal shape. In particular, the nanostructures 4 are hexagonal in shape.

The pyramid tip of the nanostructures 4 is respectively

flattened. In the area of the flattened areas of

Nanostructures 4, substructures 42 are formed.

In particular, each nanostructure 4 has a plurality of differently sized substructures 42. The substructures are in this embodiment as

Recesses formed.

The nanostructures 4 of FIGS. 4A are thus formed similarly to the embodiment of FIG. 3A.

As illustrated in the embodiment of FIG. 4A, the nanostructures 4 cover only part of the

Radiation exit or -eintrittsflache 3, so that the remaining part of the radiation exit or -eintrittsflache 3 is free of nanostructures 4.

FIG. 4B is a plan view of a radiation entrance or exit surface 3 of a semiconductor chip, such as FIG

shown for example in Figure 1, shown. On the

Strahlungsaustritts- or -eintrittsflache 3 are formed in a regular pattern, a plurality of nanostructures 4, which are pyramid-shaped as in the embodiment of Figure 4A. In particular, they have a hexagonal shape. In the region of the center of the pyramid, ie in the region of the pyramid tip, in each case a substructure 42 is formed, which in particular has a

Recess is. The nanostructures 4 of FIGS. 4B are thus similar to the embodiment of FIG. 3B. The sizes of the explained in the figures

Semiconductor chips or individual components thereof are not explicitly limited to these. Rather, the invention also has the sizes explained in the description or claims.

The invention is not limited by the description based on the embodiments of these. Rather, the invention has every new feature as well as any combination of

Characteristics on what every particular combination of

Contains features in the claims, even if this feature or combination itself is not explicitly stated in the claims or exemplary embodiments.

Claims

claims

An optoelectronic semiconductor chip (10) comprising a semiconductor layer stack (2) and a

Radiation exit surface or -eintrittsflache (3), wherein

- The semiconductor layer stack (2) has an active layer (2a), which for generating or for receiving

electromagnetic radiation is suitable, and

- In the semiconductor layer stack (2) and / or on the

Radiation exit surface or entry surface (3) a

A plurality of nanostructures (4) is arranged, which at least partially at least one substructure (41, 42).

2. The optoelectronic semiconductor chip according to claim 1, wherein the at least one substructure (41, 42) is a recess (42) or an elevation (41).

3. Optoelectronic semiconductor chip according to one of

preceding claims, wherein the nanostructures (3) are arranged in a periodic pattern.

4. Optoelectronic semiconductor chip according to one of

preceding claims, wherein the nanostructures (3) each have a lateral extent of at most 5 microns

exhibit.

5. Optoelectronic semiconductor chip according to one of

preceding claims, wherein the nanostructures (3) comprise a plurality of substructures (41, 42) having a different size and / or shape.

6. Optoelectronic semiconductor chip according to one of

preceding claims, wherein the at least one Substructure {41, 42) is a recess (42), a recess, a hole, a gutter, an opening or a protrusion (41) on a surface of a nanostructure or within a nanostructure.

7. Optoelectronic semiconductor chip according to one of

preceding claims, wherein the nanostructures (3) are three-dimensional structures.

8. An optoelectronic semiconductor chip according to claim 7, wherein the nanostructures (3) are pyramidal or rod-shaped.

9. Optoelectronic semiconductor chip according to one of

preceding claims, wherein the nanostructures (3) are pyramid-shaped and each having a plurality of different sized substructures {41, 42).

10. Optoelectronic semiconductor chip according to one of

preceding claims, wherein the active layer (2a) between the nanostructures (4) and the

Radiation exit surface or -eintrittsflache (3) or in the nanostructures (4) is arranged.

11. Optoelectronic semiconductor chip according to one of

The preceding claims, wherein the nanostructures (4) are arranged on the radiation exit surface or inlet surface (3) in a regular pattern, are pyramidal in shape and each have at least one substructure (41, 42) which is a recess and arranged in the center of the pyramid is.

12. Method for producing an optoelectronic

Semiconductor chips (10) comprising the following

Process steps:

- Forming a semiconductor layer stack (2) having an active layer (2a), which for the production or the

Receiving electromagnetic radiation is suitable

Forming nanostructures (3) on the

Semiconductor layer stack (2) or in the

Semiconductor layer stack (2), and

- Forming of at least one substructure (41, 42) at least partially in the nanostructures {3).

13. The method according to claim 12, wherein the surface of the nanostructure (3) is enlarged by the substructure (41, 42).

14. The method according to any one of the preceding claims 12 or

13, wherein the nanostructures (3) by means of metalorganic vapor phase epitaxy, molecular beam epitaxy or

Liquid phase epitaxy are produced.

15. The method according to any one of the preceding claims 12 to

14, wherein a growth substrate on which the

Semiconductor layer stack (2) has been grown, at least partially or completely detached.