EP2550706B1 - A phased array antenna signal processing structure, a method and a computer program product - Google Patents

A phased array antenna signal processing structure, a method and a computer program product Download PDF

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Publication number
EP2550706B1
EP2550706B1 EP11712048.5A EP11712048A EP2550706B1 EP 2550706 B1 EP2550706 B1 EP 2550706B1 EP 11712048 A EP11712048 A EP 11712048A EP 2550706 B1 EP2550706 B1 EP 2550706B1
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Prior art keywords
beam data
processor
data
phased array
array antenna
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German (de)
French (fr)
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EP2550706A1 (en
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Frank Edward van Vliet
Raymond Van Dijk
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Nederlandse Organisatie voor Toegepast Natuurwetenschappelijk Onderzoek TNO
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Nederlandse Organisatie voor Toegepast Natuurwetenschappelijk Onderzoek TNO
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q21/00—Antenna arrays or systems
    • H01Q21/0006—Particular feeding systems
    • H01Q21/0025—Modular arrays
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01Q—ANTENNAS, i.e. RADIO AERIALS
    • H01Q3/00—Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system
    • H01Q3/26—Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the relative phase or relative amplitude of energisation between two or more active radiating elements; varying the distribution of energy across a radiating aperture
    • H01Q3/30—Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the relative phase or relative amplitude of energisation between two or more active radiating elements; varying the distribution of energy across a radiating aperture varying the relative phase between the radiating elements of an array
    • H01Q3/34—Arrangements for changing or varying the orientation or the shape of the directional pattern of the waves radiated from an antenna or antenna system varying the relative phase or relative amplitude of energisation between two or more active radiating elements; varying the distribution of energy across a radiating aperture varying the relative phase between the radiating elements of an array by electrical means

Definitions

  • the invention relates to a phased array antenna signal processing structure, comprising a processor that includes a digital beam forming unit for generating partial beam data from digitized samples of a set of phased array antenna elements.
  • Digital beam forming in active electronic antenna arrays is complex. When the beam forming is performed in the digital domain, a central processor is heavily loaded both in terms of processing load and in communication load. Current implementations of analog and digital beam formers are very inflexible and poorly scalable. When the number of (phased array) antenna elements increases, the computational requirements of the used processor increases exceptionally.
  • patent publication WO 2004/030145 discloses a method of producing a digital beamformer signal by a number of antenna modules that are alike, as well as a system implementing the method.
  • phased array antenna signal processing structure according to claim 1 is provided.
  • the processing capacity as well as the communication load of the signal processing structure can be distributed, thereby optimally exploiting the processor capacity.
  • the processors are communicatively connected in a ring structure for cyclically performing the adding function, all processors can in principle be loaded equally.
  • the processing functions that are needed for computing a digital beam can be effectively distributed over the available processors.
  • the processor according to the invention allows a highly scalable ring structure wherein the number of processors increases linearly with number of phased array antenna elements and the communication load remains the same.
  • the structure is thus fully scalable regarding the number of digital beams, the number of phased array antenna elements and the number of processors.
  • a hierarchical beam forming structure can be realized without a hierarchy in the processor structure.
  • the invention relates to a method according to claim 11.
  • a computer program product may comprise a set of computer executable instructions stored on a data carrier, such as a flash memory, a CD or a DVD.
  • the set of computer executable instructions which allow a programmable computer to carry out the method as defined above, may also be available for downloading from a remote server, for example via the Internet.
  • FIG. 1 shows a schematic view of a phased array antenna signal processing structure 1 according to the invention.
  • the structure 1 includes a multiple number of identical processors 2a-h that are communicatively connected in a ring structure.
  • the ring structure is composed of eight processors 2a-h and a central unit that are interconnected via two sets of communication lines 4, viz. a set of communication lines 4a transmitting intermediate beam data and a set of communication lines 4b transmitting final beam data.
  • the set of communication lines 4a,b can be physically distinct lines or logically distinct lines.
  • FIG. 2 shows a schematic view of a processor 2 from the ring structure 1.
  • the processor 2 also called tile, includes a digital beam forming unit 5, also called beam former, for generating partial beam data from digitized samples of a set of phased array antenna elements.
  • the processor 2 includes a first adder 6, also called samples adder, for adding the generated partial beam data.
  • the processor 2 includes a number of terminals for communication with other devices.
  • the processor 2 includes a first set of input terminals 7 for receiving intermediate beam data 44a from a preceding processor in the ring 1, a first set of output terminals 8 for transmitting new intermediate beam data 44a to a subsequent processor in the ring 1, a second set of input terminals 9 for receiving digitized samples 12 of a phased array antenna set, a third set of input terminals 10 for receiving digital beam coefficients 11, a fourth set of input terminals 13 and a second set of output terminals 14 for receiving and transmitting, respectively, final beam data 44b.
  • the first set of input terminals 7 of a particular processor 2c are connected the first set of output terminals 8 of a preceding processor 2b in the ring 1.
  • the first set of output terminals 8 of the particular processor 2c are connected to the set of input terminals 7 of a subsequent processor 2d in the ring 1.
  • the fourth set of input terminals 13 and the second set of output terminals 14 of subsequent processors 2 in the ring structure 1 form the second set of communication lines for the final beam data 44b.
  • Each processor 2 contains the same number of input terminals in the second set of input terminals 9, so that each processor can process the same number of samples 12.
  • the processor 2 includes 32 first input terminals 9, also called sample input channels.
  • the ring structure 1, including in the shown example 8 processors 2 is able to process 256 channels of digital samples.
  • a phased array antenna structure is split into 8 sets of phased array antenna elements, each feeding a corresponding processor 2.
  • the central unit 3 is provided with corresponding sets of input terminals and output terminals for receiving the intermediate beam data 44a and the final beam data 44b.
  • each sample is multiplied with a corresponding coefficient. Then, all multiplied samples are added. Thus, in each processor 2 receiving, in the shown embodiment, 32 samples, 32 multiplied samples are added.
  • a multiple number of digital beams can be computed. Thereto, the same samples 12 are also multiplied with other digital beam coefficients 11 to arrive at a second set of digital beam data.
  • the number of digital beams is in the same order as the total number of samples, in this example, 256 digital beams.
  • the data that is generated in the digital beam forming unit 5 are called partial beam data, since the adding process has not yet been performed over all samples, but only over the samples that are received by a common processor 2. In the following, the process of adding the partial beam data is described.
  • the partial beam data 15 is internally transmitted to the first adder 6 that receives also intermediate beam data 44a from the preceding processor 2 in the ring structure 1, via the first set of input terminals 9.
  • the partial beam data 15 generated by the digital beam forming unit 5 is added to the intermediate beam data 44a to get a new update of the intermediate beam data 44a.
  • Corresponding digital beam data are added, i.e. a summation is performed over partial beam data that relate to the same digital beam.
  • the new update of the intermediate beam data 44a is transmitted to the next processor 2 in the ring structure 1. When this process is repeated, subsequently, by the eight processors 2, all digital beams have been computed.
  • the data of the complete digital beams are called final beam data 44b.
  • final beam data are generated by adding intermediate beam data received at a processor to corresponding partial beam data generated by the processor, wherein the intermediate beam data are based on corresponding partial beam data generated by all other processors in the ring 1.
  • the final beam data 44b is transmitted via the second set of output terminals.
  • Figure 3 shows a schematic view of three subsequent processors 2a-c in the structure 1.
  • the computation of the final beam data 44b is evenly distributed over the processors 2, so that each processor 2 performs a similar task.
  • each processor 2 generates 32 different final digital beams adding up to the total number of 256 digital beams.
  • the first processor 2a computes a block 80 of final digital beams, viz. digital beams 225-256, and seven blocks 81 of 32 intermediate digital beam data each.
  • the second processor 2 b computes a single block 80 of other final digital beams, viz. digital beams 193-224, and seven blocks 81 of 32 intermediate digital beam data each.
  • the block 80 that is added, by a particular processor 2, to the communication line 4b of final data, is not changed by the other processors 2.
  • the central unit 3 obtains all blocks of final data 44b for further processing.
  • the fully beam formed data referred to as final beam data available for further processing can be transmitted to units outside the ring structure.
  • the final beam data can be transmitted to a single processor unit.
  • the communication load is herewith locally increased.
  • the final beam data are transmitted to a dedicated processor node embedded at any location in the ring structure.
  • one or a few beam data sets are allocated to a single processor, so that the communication load is distributed over available processors.
  • the latter method of communicating final beam data has the added advantage that any additional processing required per final beam data set (e.g. range-doppler processing) can be equally divided over processors as well.
  • the processor might include terminals for time controlling signals and/or for reading data such as multiplication coefficients that have been input to the processor.
  • the number of first and second input terminals, and the number of first and second output terminals coincides to optimally benefit from digital I/O terminals in the processor 2.
  • the data passed between processors can contain time stamp data to align partial beam data and intermediate beam data.
  • the digital samples are received at a rate of 96 K samples per second, per ADC, each sample having 8 bits that are transmitted serially.
  • a defect in the performance of a specific processor in the ring structure can be detected. Then, the intermediate data and the final data can be transmitted by a preceding processor in the ring, towards a subsequent processor in the ring, thus circumventing the processor having the defect. Hence, measures have to be taken to properly delay the data or time stamp the data, so that the other processors continue in meaningfully processing the intermediate results.
  • the ring structure can continue processing phased array antenna data, also with a defect processor, albeit with a reduced performance since the functionally eliminated processor and connected antenna element data do not contribute anymore in computing a digital beam.
  • the steps of detecting a defect in the performance of a specific processor, and forwarding the intermediate data and final data transmitted by a preceding processor towards a subsequent processor can not only be performed in combination with a phased array antenna signal processing structure wherein a multiple number of processors are communicatively connected in a ring structure, but also, in combination with a more general phased array antenna signal processing structure wherein a multiple number of processors are communicatively connected in a chain structure.
  • the processor can be implemented in various ways, e.g. as an FPGA, an ASIC, a DSP or a general purpose processor, e.g. using a laptop.
  • FIG. 4 shows a flow chart of an embodiment of the method according to the invention.
  • the method is used for processing phased array antenna digitized samples.
  • the method comprises the steps of generating (100) partial beam data using a processor processing a digitized samples received from a set of phased arrays, receiving (110), at the processor, intermediate beam data from another processor processing digitized samples received from another set of phased array antenna elements, generating (120) new intermediate beam data by adding the partial beam data to the corresponding received intermediate beam data, and transmitting (130) the new intermediate beam data to yet a further processor processing digitized samples received from a further set of phased arrays.
  • the method of processing phased array antenna digitized samples can be performed using dedicated hardware structures, such as FPGA and/or ASIC components. Otherwise, the method can also at least partially be performed using a computer program product comprising instructions for causing a processor of the computer system to perform the above described steps of the method according to the invention. All steps can in principle be performed on a single processor. However it is noted that at least one step can be performed on a separate processor, e.g. the step of transmitting the new intermediate beam data to yet a further processor processing digitized samples received from a further set of phased arrays.
  • processors and another total number of samples can be chosen.
  • another number of input terminals in the second set of input terminals of the processors can be chosen.
  • the processor can include further processing functions such as analog-digital conversion, calibration etc.
  • Calibration can be implemented as an additional multiplication, for the sake of a simple design, or as an additional addition, for the sake of computational efficiency.
  • the digital beam forming unit can process on the real and imaginary part of the samples. Otherwise, also the amplitude and phase components can be processed. Further, by signal decomposition in frequency and phase components, an efficient Hilbert operation can optionally be applied.

Description

  • The invention relates to a phased array antenna signal processing structure, comprising a processor that includes a digital beam forming unit for generating partial beam data from digitized samples of a set of phased array antenna elements.
  • Digital beam forming in active electronic antenna arrays is complex. When the beam forming is performed in the digital domain, a central processor is heavily loaded both in terms of processing load and in communication load. Current implementations of analog and digital beam formers are very inflexible and poorly scalable. When the number of (phased array) antenna elements increases, the computational requirements of the used processor increases exceptionally.
  • It is noted that patent publication WO 2004/030145 discloses a method of producing a digital beamformer signal by a number of antenna modules that are alike, as well as a system implementing the method.
  • It is an object of the invention to provide a more efficient signal processing structure according to the preamble for processing phased array antenna element data. Thereto, according to the invention, a phased array antenna signal processing structure according to claim 1 is provided.
  • By both generating partial beam data and adding intermediate beam data from another processor, the processing capacity as well as the communication load of the signal processing structure can be distributed, thereby optimally exploiting the processor capacity. Especially when the processors are communicatively connected in a ring structure for cyclically performing the adding function, all processors can in principle be loaded equally.
  • The processing functions that are needed for computing a digital beam can be effectively distributed over the available processors. Further, the processor according to the invention allows a highly scalable ring structure wherein the number of processors increases linearly with number of phased array antenna elements and the communication load remains the same. The structure is thus fully scalable regarding the number of digital beams, the number of phased array antenna elements and the number of processors. In addition, since only intermediate results are transmitted, there is a low communication load on array level while the communication between the processors is minimal. Further, a hierarchical beam forming structure can be realized without a hierarchy in the processor structure.
  • Further, the invention relates to a method according to claim 11.
  • In addition, the invention relates to a computer program product according to claim 16. A computer program product may comprise a set of computer executable instructions stored on a data carrier, such as a flash memory, a CD or a DVD. The set of computer executable instructions, which allow a programmable computer to carry out the method as defined above, may also be available for downloading from a remote server, for example via the Internet.
  • Other advantageous embodiments according to the invention are described in the following claims.
  • By way of example only, embodiments of the present invention will now be described with reference to the accompanying figures in which
    • Fig. 1 shows a schematic view of a phased array antenna signal processing structure according to the invention;
    • Fig. 2 shows a schematic view of a compressor in the structure of Fig. 1;
    • Fig. 3 shows a schematic view of three subsequent processors in the structure of Fig. 1; and
    • Fig. 4 shows a flow chart of a method according to the invention.
  • The figures are merely schematic views of a preferred embodiment according to the invention. In the figures, the same reference numbers refer to equal or corresponding parts.
  • Figure 1 shows a schematic view of a phased array antenna signal processing structure 1 according to the invention. The structure 1 includes a multiple number of identical processors 2a-h that are communicatively connected in a ring structure. In the shown embodiment, the ring structure is composed of eight processors 2a-h and a central unit that are interconnected via two sets of communication lines 4, viz. a set of communication lines 4a transmitting intermediate beam data and a set of communication lines 4b transmitting final beam data. The set of communication lines 4a,b can be physically distinct lines or logically distinct lines.
  • Figure 2 shows a schematic view of a processor 2 from the ring structure 1. The processor 2, also called tile, includes a digital beam forming unit 5, also called beam former, for generating partial beam data from digitized samples of a set of phased array antenna elements. Further, the processor 2 includes a first adder 6, also called samples adder, for adding the generated partial beam data. In addition, the processor 2 includes a number of terminals for communication with other devices.
  • More specifically, the processor 2 includes a first set of input terminals 7 for receiving intermediate beam data 44a from a preceding processor in the ring 1, a first set of output terminals 8 for transmitting new intermediate beam data 44a to a subsequent processor in the ring 1, a second set of input terminals 9 for receiving digitized samples 12 of a phased array antenna set, a third set of input terminals 10 for receiving digital beam coefficients 11, a fourth set of input terminals 13 and a second set of output terminals 14 for receiving and transmitting, respectively, final beam data 44b.
  • In order to obtain the ring structure, the first set of input terminals 7 of a particular processor 2c are connected the first set of output terminals 8 of a preceding processor 2b in the ring 1. Similarly, the first set of output terminals 8 of the particular processor 2c are connected to the set of input terminals 7 of a subsequent processor 2d in the ring 1. Analogously, the fourth set of input terminals 13 and the second set of output terminals 14 of subsequent processors 2 in the ring structure 1 form the second set of communication lines for the final beam data 44b.
  • Each processor 2 contains the same number of input terminals in the second set of input terminals 9, so that each processor can process the same number of samples 12. In the shown example, the processor 2 includes 32 first input terminals 9, also called sample input channels. Then, the ring structure 1, including in the shown example 8 processors 2, is able to process 256 channels of digital samples. Thereto, a phased array antenna structure is split into 8 sets of phased array antenna elements, each feeding a corresponding processor 2.
  • Also the central unit 3 is provided with corresponding sets of input terminals and output terminals for receiving the intermediate beam data 44a and the final beam data 44b.
  • During operation of the ring structure 1 according to the invention, each processor 2a-h receives, via the second set of input terminals 9 digitized samples 12 from the corresponding set of phased array antenna elements. Thereto, the samples have been digitized using analog to digital converters ADC's. Each processor 2 processes the samples 12 to generate partial beam data. In this process, digital beam coefficients 11 are received via the third set of input terminals 10. The digital beam forming unit 5 includes a set of multipliers for multiplying the received samples 12 with corresponding digital beam coefficients 11. Further, the digital beam forming unit 5 includes a second adder for adding corresponding multiplied samples to generate partial beam data.
  • In order to obtain a digital beam, each sample is multiplied with a corresponding coefficient. Then, all multiplied samples are added. Thus, in each processor 2 receiving, in the shown embodiment, 32 samples, 32 multiplied samples are added. However, according to an aspect of the invention, a multiple number of digital beams can be computed. Thereto, the same samples 12 are also multiplied with other digital beam coefficients 11 to arrive at a second set of digital beam data. Preferably, the number of digital beams is in the same order as the total number of samples, in this example, 256 digital beams. The data that is generated in the digital beam forming unit 5 are called partial beam data, since the adding process has not yet been performed over all samples, but only over the samples that are received by a common processor 2. In the following, the process of adding the partial beam data is described.
  • The partial beam data 15 is internally transmitted to the first adder 6 that receives also intermediate beam data 44a from the preceding processor 2 in the ring structure 1, via the first set of input terminals 9. Using the first adder, the partial beam data 15 generated by the digital beam forming unit 5 is added to the intermediate beam data 44a to get a new update of the intermediate beam data 44a. Corresponding digital beam data are added, i.e. a summation is performed over partial beam data that relate to the same digital beam. The new update of the intermediate beam data 44a is transmitted to the next processor 2 in the ring structure 1. When this process is repeated, subsequently, by the eight processors 2, all digital beams have been computed. The data of the complete digital beams are called final beam data 44b.
  • According to an aspect of the invention, final beam data are generated by adding intermediate beam data received at a processor to corresponding partial beam data generated by the processor, wherein the intermediate beam data are based on corresponding partial beam data generated by all other processors in the ring 1. The final beam data 44b is transmitted via the second set of output terminals.
  • Figure 3 shows a schematic view of three subsequent processors 2a-c in the structure 1. According to an advantageous embodiment of the invention, the computation of the final beam data 44b is evenly distributed over the processors 2, so that each processor 2 performs a similar task. In the exemplary embodiment, each processor 2 generates 32 different final digital beams adding up to the total number of 256 digital beams. In the shown embodiment, the first processor 2a computes a block 80 of final digital beams, viz. digital beams 225-256, and seven blocks 81 of 32 intermediate digital beam data each. Similarly, the second processor 2 b computes a single block 80 of other final digital beams, viz. digital beams 193-224, and seven blocks 81 of 32 intermediate digital beam data each. The block 80 that is added, by a particular processor 2, to the communication line 4b of final data, is not changed by the other processors 2.
  • The central unit 3 obtains all blocks of final data 44b for further processing. The fully beam formed data referred to as final beam data available for further processing can be transmitted to units outside the ring structure. In a first embodiment, the final beam data can be transmitted to a single processor unit. However, the communication load is herewith locally increased. In a further embodiment, the final beam data are transmitted to a dedicated processor node embedded at any location in the ring structure. In yet a further embodiment, one or a few beam data sets are allocated to a single processor, so that the communication load is distributed over available processors. The latter method of communicating final beam data has the added advantage that any additional processing required per final beam data set (e.g. range-doppler processing) can be equally divided over processors as well.
  • In order to facilitate a proper time management of the data to be processed and transmitted, a number of further input terminals and output terminals can be provided. As an example, the processor might include terminals for time controlling signals and/or for reading data such as multiplication coefficients that have been input to the processor.
  • It is noted that, preferably, the number of first and second input terminals, and the number of first and second output terminals coincides to optimally benefit from digital I/O terminals in the processor 2. In a different embodiment the data passed between processors can contain time stamp data to align partial beam data and intermediate beam data.
  • As an example, the digital samples are received at a rate of 96 K samples per second, per ADC, each sample having 8 bits that are transmitted serially.
  • According to a further aspect of the invention, a defect in the performance of a specific processor in the ring structure can be detected. Then, the intermediate data and the final data can be transmitted by a preceding processor in the ring, towards a subsequent processor in the ring, thus circumventing the processor having the defect. Apparently, measures have to be taken to properly delay the data or time stamp the data, so that the other processors continue in meaningfully processing the intermediate results. Advantageously, by applying a data transfer by-pass, the ring structure can continue processing phased array antenna data, also with a defect processor, albeit with a reduced performance since the functionally eliminated processor and connected antenna element data do not contribute anymore in computing a digital beam.
  • In this respect it is noted that the steps of detecting a defect in the performance of a specific processor, and forwarding the intermediate data and final data transmitted by a preceding processor towards a subsequent processor can not only be performed in combination with a phased array antenna signal processing structure wherein a multiple number of processors are communicatively connected in a ring structure, but also, in combination with a more general phased array antenna signal processing structure wherein a multiple number of processors are communicatively connected in a chain structure.
  • The processor can be implemented in various ways, e.g. as an FPGA, an ASIC, a DSP or a general purpose processor, e.g. using a laptop.
  • Figure 4 shows a flow chart of an embodiment of the method according to the invention. The method is used for processing phased array antenna digitized samples. The method comprises the steps of generating (100) partial beam data using a processor processing a digitized samples received from a set of phased arrays, receiving (110), at the processor, intermediate beam data from another processor processing digitized samples received from another set of phased array antenna elements, generating (120) new intermediate beam data by adding the partial beam data to the corresponding received intermediate beam data, and
    transmitting (130) the new intermediate beam data to yet a further processor processing digitized samples received from a further set of phased arrays.
  • The method of processing phased array antenna digitized samples can be performed using dedicated hardware structures, such as FPGA and/or ASIC components. Otherwise, the method can also at least partially be performed using a computer program product comprising instructions for causing a processor of the computer system to perform the above described steps of the method according to the invention. All steps can in principle be performed on a single processor. However it is noted that at least one step can be performed on a separate processor, e.g. the step of transmitting the new intermediate beam data to yet a further processor processing digitized samples received from a further set of phased arrays.
  • The invention is not restricted to the embodiments described herein. It will be understood that many variants are possible.
  • It is noted that another number of processors and another total number of samples can be chosen. Further, another number of input terminals in the second set of input terminals of the processors can be chosen.
  • In addition, the processor can include further processing functions such as analog-digital conversion, calibration etc. Calibration can be implemented as an additional multiplication, for the sake of a simple design, or as an additional addition, for the sake of computational efficiency.
  • The digital beam forming unit can process on the real and imaginary part of the samples. Otherwise, also the amplitude and phase components can be processed. Further, by signal decomposition in frequency and phase components, an efficient Hilbert operation can optionally be applied.
  • Other such variants will be apparent for the person skilled in the art and are considered to lie within the scope of the invention as determined in the following claims.

Claims (16)

  1. A phased array antenna signal processing structure (1), comprising a processor (2) that includes a digital beam forming unit (5) for generating partial beam data (15) from digitized samples (12) of a set of phased array antenna elements, and wherein the processor further comprises:
    - a first set of input terminals (7) for receiving intermediate beam data (44a) from another processor processing digitized samples received from another set of phased array antenna elements;
    - a first adder (6) for generating new intermediate beam data by adding partial beam data (15) generated by the digital beam forming unit to the corresponding received intermediate beam data (44a);
    - a first set of output terminals (8) for transmitting the new intermediate beam data;
    - a second set of input terminals (9) for receiving said digitized samples (12) of said set of phased array antenna elements;
    - a third set of input terminals (10) for receiving digital beam coefficients (11); and wherein the digital beam forming unit (5) comprises a set of multipliers for multiplying said received digitized samples (12) with corresponding received digital beam coefficients (11); and a second adder for adding corresponding multiplied samples to generate said partial beam data (15).
  2. A structure according to claim 1, wherein the partial beam data and the intermediate beam data include data relating to multiple digital beams.
  3. A structure according to any of the preceding claims, comprising a multiple number of processors communicatively connected in a ring structure.
  4. A structure according to claim 3, wherein the first set of input terminals of a particular processor are connected to the first set of output terminals of a preceding processor in the ring, and wherein the first set of output terminals of the particular processor are connected to the first set of input terminals of a subsequent processor in the ring.
  5. A structure according to claim 3 or 4, wherein each of the processors are arranged for processing digitized samples of a corresponding set of phased array antenna elements.
  6. A structure according to any of claims 3-5, wherein each processor contains the same number of input terminals in the second set of input terminals.
  7. A structure according to any of claims 3-6, further comprising a central unit, included in the ring, for receiving final beam data (44b).
  8. A structure according to any of claims 3-7, wherein the processors further include a fourth set of input terminals and a second set of output terminals for receiving and transmitting, respectively, final beam data (44b).
  9. A structure according to any of claims 3-8, wherein the first adder in each processor is arranged for generating final beam data (44b) by adding received intermediate beam data to corresponding partial beam data generated by the digital beam forming unit wherein the intermediate beam data is based on corresponding partial beam data generated by all other processors in the ring.
  10. A structure according to any of claims 3-9, wherein the processors are identical.
  11. A method for processing digitized samples (12) of a set of phased array antenna elements, comprising the steps of:
    - generating partial beam data (15) using a processor (2) processing digitized samples (12) received from a set of phased array antenna elements;
    - receiving, at the processor (2), intermediate beam data (44a) from another processor processing digitized samples received from another set of phased array antenna elements;
    - generating new intermediate beam data (44a) by adding the partial beam data (15) to the corresponding received intermediate beam data (44a), using a first adder (6); and
    - transmitting the new intermediate beam data (44a) to yet a further processor processing digitized samples received from a further set of phased array antenna elements,
    wherein the step of generating partial beam data (15) includes multiplying said received digitized samples (12) with corresponding digital beam coefficients (11), using a set of multipliers, and adding corresponding multiplied samples, using a second adder, to generate said partial beam data (15).
  12. A method according to claim 11, further comprising the steps of:
    - splitting the digitized samples of the sets of phased array antenna elements into a multiple number of N digitized sample sets;
    - generating partial beam data using N processors communicatively connected in a ring structure, each processor processing a corresponding digitized sample set;
    - receiving, at each processor, intermediate beam data from a preceding processor in the ring;
    - generating, by each processor, new intermediate beam data by adding the intermediate beam data that is received at each processor to corresponding partial beam data generated by said processor; and
    - transmitting all new intermediate beam data to the subsequent processor in the ring.
  13. A method according to claim 12, further comprising generating final beam data by performing the steps of:
    - adding intermediate beam data received at a processor to corresponding partial beam data generated by the processor wherein the intermediate beam data are based on corresponding partial beam data generated by all other processors in the ring; and
    - deciding whether the added intermediate beam data is complete and can be transferred as final beam data instead of intermediate beam data.
  14. A method according to claim 13 , further comprising a step of performing additional processing on the final beam data.
  15. A method according to claim 14, further comprising detecting a defect in the performance of a specific processor in the ring structure, and forwarding the intermediate data and final data transmitted by a preceding processor in the ring, to a subsequent processor in the ring.
  16. A computer program product for processing digitized samples (12) of a set of phased array antenna elements, the computer program product comprising computer readable code causing a processor (2) to perform the steps of:
    - generating partial beam data (15) using a processor (2) processing digitized samples (12) received from a set of phased array antenna elements;
    - receiving, at the processor, intermediate beam data (44a) from another processor processing digitized samples received from another set of phased array antenna elements;
    - generating new intermediate beam data (44a) by adding the partial beam data (15) to the corresponding received intermediate beam data (44a), using a first adder (6); and
    - transmitting the new intermediate beam data (44a) to yet a further processor processing digitized samples received from a further set of phased array antenna element antenna elements,
    wherein the step of generating partial beam data (15) includes multiplying said received digitized samples (12) with corresponding digital beam coefficients (11), using a set of multipliers, and adding corresponding multiplied samples, using a second adder, to generate said partial beam data (15).
EP11712048.5A 2010-03-24 2011-03-23 A phased array antenna signal processing structure, a method and a computer program product Active EP2550706B1 (en)

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