EP2495665A3 - Command transfer controlling apparatus and command transfer controlling method - Google Patents

Command transfer controlling apparatus and command transfer controlling method Download PDF

Info

Publication number
EP2495665A3
EP2495665A3 EP20120004147 EP12004147A EP2495665A3 EP 2495665 A3 EP2495665 A3 EP 2495665A3 EP 20120004147 EP20120004147 EP 20120004147 EP 12004147 A EP12004147 A EP 12004147A EP 2495665 A3 EP2495665 A3 EP 2495665A3
Authority
EP
European Patent Office
Prior art keywords
command
command transfer
transfer controlling
area
storage unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP20120004147
Other languages
German (de)
French (fr)
Other versions
EP2495665A2 (en
EP2495665B1 (en
Inventor
Katsushi Ohtsuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sony Interactive Entertainment Inc
Original Assignee
Sony Computer Entertainment Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sony Computer Entertainment Inc filed Critical Sony Computer Entertainment Inc
Publication of EP2495665A2 publication Critical patent/EP2495665A2/en
Publication of EP2495665A3 publication Critical patent/EP2495665A3/en
Application granted granted Critical
Publication of EP2495665B1 publication Critical patent/EP2495665B1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G06F13/1626—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests
    • G06F13/1631—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement by reordering requests through address comparison
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/1642—Handling requests for interconnection or transfer for access to memory bus based on arbitration with request queuing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/60—Memory management
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/001—Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/125—Frame memory handling using unified memory architecture [UMA]
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/127—Updating a frame memory using a transfer of data from a source area to a destination area

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Software Systems (AREA)
  • Multimedia (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Computer And Data Communications (AREA)
  • Multi Processors (AREA)
  • Communication Control (AREA)

Abstract

Commands transmitted and received among a plurality of processing units are efficiently controlled.
A command receiver 210 receives from an external command transmitting entity a command that has assigned a memory address. An address range of memory is divided into a plurality of areas, and an assignment information storage unit 228 stores an assignment table in which a channel is assigned to each area. A command storage unit 230 contains a queue provided in accordance with each channel wherein the each queue stores received commands temporarily. A distribution destination specifying unit 224 specifies an area that corresponds to a memory address by referring to the assignment table, and an execution unit 222 transfers the received command to a command storage unit that corresponds to said area.
EP12004147.0A 2005-06-14 2006-05-10 Command transfer controlling apparatus and command transfer controlling method Active EP2495665B1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2005174209A JP4443474B2 (en) 2005-06-14 2005-06-14 Command transfer control device and command transfer control method
EP06732619A EP1894105B1 (en) 2005-06-14 2006-05-10 Command transfer controlling apparatus and command transfer controlling method

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
EP06732619A Division EP1894105B1 (en) 2005-06-14 2006-05-10 Command transfer controlling apparatus and command transfer controlling method

Publications (3)

Publication Number Publication Date
EP2495665A2 EP2495665A2 (en) 2012-09-05
EP2495665A3 true EP2495665A3 (en) 2014-03-26
EP2495665B1 EP2495665B1 (en) 2015-08-19

Family

ID=37532113

Family Applications (2)

Application Number Title Priority Date Filing Date
EP06732619A Active EP1894105B1 (en) 2005-06-14 2006-05-10 Command transfer controlling apparatus and command transfer controlling method
EP12004147.0A Active EP2495665B1 (en) 2005-06-14 2006-05-10 Command transfer controlling apparatus and command transfer controlling method

Family Applications Before (1)

Application Number Title Priority Date Filing Date
EP06732619A Active EP1894105B1 (en) 2005-06-14 2006-05-10 Command transfer controlling apparatus and command transfer controlling method

Country Status (6)

Country Link
US (1) US7725623B2 (en)
EP (2) EP1894105B1 (en)
JP (1) JP4443474B2 (en)
KR (1) KR100864998B1 (en)
CN (1) CN101040270B (en)
WO (1) WO2006134746A1 (en)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4996929B2 (en) * 2007-01-17 2012-08-08 株式会社日立製作所 Virtual computer system
US9201790B2 (en) * 2007-10-09 2015-12-01 Seagate Technology Llc System and method of matching data rates
JP5625737B2 (en) * 2010-10-22 2014-11-19 富士通株式会社 Transfer device, transfer method, and transfer program
JP2012221038A (en) * 2011-04-05 2012-11-12 Toshiba Corp Memory system
US9021179B2 (en) * 2011-06-10 2015-04-28 International Business Machines Corporation Store storage class memory information command
CN102904899A (en) * 2012-10-26 2013-01-30 苏州阔地网络科技有限公司 Method and system for dynamically controlling network connection
CN102916870A (en) * 2012-10-26 2013-02-06 苏州阔地网络科技有限公司 Method and system for controlling network connection
CN102932226B (en) * 2012-10-26 2015-07-15 苏州阔地网络科技有限公司 Method for reducing network connection
US10037150B2 (en) * 2016-07-15 2018-07-31 Advanced Micro Devices, Inc. Memory controller with virtual controller mode
EP3270295A1 (en) * 2016-07-15 2018-01-17 Advanced Micro Devices, Inc. Memory controller with virtual controller mode
WO2023022356A1 (en) * 2021-08-17 2023-02-23 삼성전자 주식회사 Electronic device and method for synchronizing timing of processing commands for controlling display panel

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5752010A (en) * 1993-09-10 1998-05-12 At&T Global Information Solutions Company Dual-mode graphics controller with preemptive video access
WO1999034294A1 (en) * 1997-12-24 1999-07-08 Creative Technology Ltd. Optimal multi-channel memory controller system

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5212795A (en) * 1988-10-11 1993-05-18 California Institute Of Technology Programmable DMA controller
WO1994025914A2 (en) 1993-04-30 1994-11-10 Zenith Data Systems Corporation Symmetric multiprocessing system with unified environment and distributed system functions
JP3190852B2 (en) 1997-04-24 2001-07-23 甲府日本電気株式会社 Dispatch method of information processing system
US6205504B1 (en) * 1998-09-30 2001-03-20 International Business Machines Corporation Externally provided control of an I2C bus
JP3558559B2 (en) 1999-08-19 2004-08-25 Ｎｅｃエレクトロニクス株式会社 Information processing equipment
JP4403677B2 (en) * 2001-08-27 2010-01-27 ブラザー工業株式会社 Communication apparatus and communication system
JP2003099384A (en) 2001-09-20 2003-04-04 Nec Corp Load-sharing system, host computer for the load-sharing system, and load-sharing program
US6931478B2 (en) * 2002-02-06 2005-08-16 International Business Machines Corporation Implicit addressing sequential media drive with intervening converter simulating explicit addressing to host applications
JP2004046392A (en) 2002-07-10 2004-02-12 Renesas Technology Corp Usb host control circuit
JP4170742B2 (en) * 2002-11-29 2008-10-22 株式会社エヌ・ティ・ティ・ドコモ Download system, communication terminal, server, download method
US6985970B2 (en) 2003-04-25 2006-01-10 International Business Machines Corporation Data transfer with implicit notification
JP2005010956A (en) * 2003-06-17 2005-01-13 Hitachi Ltd Method for controlling information processor, information processor, information processing system and program

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5752010A (en) * 1993-09-10 1998-05-12 At&T Global Information Solutions Company Dual-mode graphics controller with preemptive video access
WO1999034294A1 (en) * 1997-12-24 1999-07-08 Creative Technology Ltd. Optimal multi-channel memory controller system

Also Published As

Publication number Publication date
JP4443474B2 (en) 2010-03-31
US20080307115A1 (en) 2008-12-11
WO2006134746A1 (en) 2006-12-21
CN101040270A (en) 2007-09-19
EP1894105B1 (en) 2012-06-27
US7725623B2 (en) 2010-05-25
CN101040270B (en) 2012-02-22
KR20070083459A (en) 2007-08-24
EP2495665A2 (en) 2012-09-05
EP1894105A4 (en) 2008-09-17
EP2495665B1 (en) 2015-08-19
EP1894105A1 (en) 2008-03-05
KR100864998B1 (en) 2008-10-23
JP2006350555A (en) 2006-12-28

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