EP2476138B1

EP2476138B1 - A fin-fet non-volatile memory cell and an array

Info

Publication number: EP2476138B1
Application number: EP10815914.6A
Authority: EP
Inventors: Yaw Wen Hu; Prateep Tuntasood
Original assignee: Silicon Storage Technology Inc
Current assignee: Silicon Storage Technology Inc
Priority date: 2009-09-08
Filing date: 2010-08-31
Publication date: 2015-08-12
Anticipated expiration: 2030-08-31
Also published as: KR20120054626A; JP2013504221A; EP2476138A4; TWI422040B; KR101370779B1; TW201131786A; CN102484133A; WO2011031586A1; US8461640B2; EP2476138A1; US20110057247A1; JP5514317B2; CN102484133B

Description

TECHNICAL FIELD

The present invention relates to a Fin-Fet non-volatile memory cell structure, and array.

BACKGROUND OF THE INVENTION

Non-Volatile memory cells using floating gates to control the conduction of current in a planar channel region is well known in the art. See for example U.S. Patent 6,747,310 . as the scale of integration increases, i.e. the geometry of the lithography for semiconductor processing decreases in size, the problem with a planar channel region is that the channel region becomes narrower. This reduces the current flow between the source and drain regions, requiring more sensitive sense amplifiers etc. to detect the state of the memory cell.
Because the problem of shrinking the lithography size thereby reducing the channel width affects all semiconductor devices, a Fin-FET type of structure has been proposed. In a Fin-FET type of structure, a fin shaped member of semiconductor material connects the source to the drain regions. The fin shaped member has a top surface and two side surfaces. Current from the source to the drain regions can then flow along the top surface as well as the two side surfaces. Thus, the width of the channel region is increased, thereby increasing the current flow. However, the width of fhe channel region is increased without sacrificing more semiconductor real estate by "folding' the channel region into two side surfaces, thereby reducing the "footprint" of the channel region. Non-volatile memory cells using such Fin-FETs have been disclosed. Some examples of prior art Fin-FET non-volatile memory structures include U.S. Patent 7,423,310 and 7,410,913 . However, heretofore, these prior art Fin-FET structures have disclosed using floating gate as a stack gate device, or using trapping material, or using SRO (silicon rich oxide) or using nanocrystal silicon to store charges.
US patent 6747310 B2 relates to flash memory and a process of fabrication in which vertically stacked pairs of floating gates and control gates are formed on opposite sides of a source diffusion in a substrate, an erase gate is formed directly above the source diffusion and between the stacked gates, select gates are formed on the sides of the stacked gates opposite the erase gate, programming paths extend from mid-channel regions in the substrate between the select gates and the stacked gates to the edge portions of the floating gates which face the select gates, and erase paths extend from the edge portions of the floating gates which face the erase gates to the source diffusion and to the erase gate. In some example, the source regions are connected electrically to the erase gates, and in others the floating gates project laterally beyond the control gates on one or both sides of the control gates. These memory cells are very small in size and substantially improve programming and erase performance.
US patent application 2007/054448 A1 provides a nonvolatile memory device having multi bit storage and a method of manufacturing the same. The method includes forming a tunneling dielectric layer, a charge storage layer and a charge blocking layer on a fin-active region, forming sacrificial patterns having a groove to open a crossing region of the active region on the charge blocking layer, selectively removing portions of the charge blocking layer, the charge storage layer and the tunneling dielectric layer exposed by the opening groove using the sacrificial layer patterns as an etch mask to expose a top surface and side surfaces of the active region, forming a gate dielectric layer on exposed portion of the active region to cover exposed side surfaces of the of charge storage layer, forming a first gate on the gate dielectric layer to fill the groove, removing the sacrificial layer patterns, forming second gates on side surfaces of the first gate, forming isolated local charge storage patterns, charge blocking patterns and tunneling dielectric patterns by selectively removing exposed portions of the charge blocking layer, the charge storage layer and the tunneling dielectric layer, and forming a source/drain region on the active region.
US patent application 2003/178670 A1 provides a device design and method for forming the same that results in Fin Field Effect Transistors having Non-Volatile Random Access Memory (NVRAM) capability. NVRAM capability arises from the presence of double floating gates arranged on and insulated from a semiconductor fin body, and a control gate arranged on and insulated from the double floating gates. The fabrication of the present device may be accomplished by: providing an SOI wafer and defining a fin on the SOI wafer, the fin may be capped with an insulator layer; providing gate insulator on at least one vertical surface of the FIN; depositing floating gate material over the gate insulator; depositing insulator material on the floating gate material to form the floating gate isolation; depositing control gate material over the isolated floating gate material; removing a portion of the control gate material to expose source and drain regions of the Fin, implanting the Fin to form source/drain regions in the exposed regions of the Fin, and providing insulator material on the Fin. In addition, the NVRAM FinFET allows for horizontal current flow.

SUMMARY OF THE INVENTION

Accordingly, in the present invention a non-volatile memory cell according to claim 1 has a substrate layer with a fin shaped semiconductor member of a first conductivity type on the substrate layer. The fin shaped member has a first region of a second conductivity type and a second region of the second conductivity type, spaced apart from the first region with a channel region extending between the first region and the second region. The fin shaped member has a top surface and two side surfaces between the first region and the second region. A word line is adjacent to the first region and is capacitively coupled to the two side surfaces of a first portion of the channel region. A floating gate is adjacent to the word line and is capacitively coupled to a second portion of the channel region. A coupling gate is capacitively coupled to the floating gate. An crase gate is insulated from the second region and is adjacent to the floating gate and the coupling gate.
The present invention is defined by the independent claim and embodiments thereof are specified by the dependent claims.
The present invention also relates to a memory device with the foregoing memory cell, and an array of memory cells of the foregoing type.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 is a perspective view of a memory array of the present invention.
Figure 2 is a top planar view of the memory array shown in Figure 1.
Figure 3(A-D) are cross sectional views of the memory array shown in Figure 2 taken along the lines A-A, B-B, C-C, and D-D respectively.
Figure 4A(1-16), 4B(1-16), 4C(1-16) and 4D(1-16) are cross sectional views of the memory array shown in Figure 2 taken along the lines A-A, B-B, C-C, and D-D respectively, showing the processing steps (1-16) to make the memory array shown in Figure 1.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

Referring to Figure 1 there is shown a perspective view of an array 10 of Fin-FET non-volatile memory cells 50 of the present invention. Functionally, the memory cells 50 are of the type disclosed in U.S. Patent 6,747.310 . The array 50 comprises a substrate 12. The substrate 12 can be an insulator or it can be a semiconductor substrate 12. A plurality of fin shaped members 20 are positioned spaced apart from one another on the substrate 12. Each of the fin shaped members 20 is made of a single crystalline material, such as silicon. Thus, in the event the substrate 12 is also of semiconductor material then the fin shaped members will be lattice matched to the crystalline structure of the substrate 12. Further, an insulator 14 may separate each of the fin shaped members 20 from the substrate 12. The insulator 14 may be of silicon dioxide. Thus, the fin shaped members 20 are on a silicon dioxide layer 14 on a substrate 12, and is of an SOS type of structure, which is well known in the art. However, that is not necessary and as will be seen, a preferred example of a method for making the array 10 without the insulator 14 will be discussed hereinafter.
Each of the fin shaped members 20 is substantially longitudinally shaped and extends from one end to another end, in a first direction (called column direction) with all of the fin shaped members 20 being parallel to one another and spaced apart from one another in a second direction (row direction) which is perpendicular to the first direction. Each of the fin shaped members 20 has a top surface 22 and two side surfaces (24 and 26), and is lightly doped with a first conductivity (such as P type). Further, each of the fin shaped members 20 has a first region 30 of a second conductivity type (such as N type) at one end, with a second region 32 of the second conductivity type at another end, with a channel region therebetween. A bit line 31 makes electrical contact to the first regions 30 and connects all of the first regions 30 of the same fin shaped member 20 in the same column direction. The second region 32 electrically connects in the row direction all of the second regions 32 of the different fin shaped members 20 in different rows.
Immediately adjacent to the first region 30 and between the first region 30 and the second region 32 is a word line 40. The word line 40 is electrically insulated from the fin shaped member 20 by a layer of buffered polysilicon 60 of about 20 nm with a layer of pad nitride 62 of about 45 nm on the layer of buffered polysilicon 60. The word line 40 is capacitively coupled to the channel region of a fin shaped member 20 by the "side surfaces" by the word line oxide layer 80. A word line 40 extends in a row direction and connects all of the word lines of the fin shaped members 20 in different rows.
Immediately adjacent to the word line 4Q of each fin shaped member 20 is a floating gate 44. The floating gate 44 has two sections: 44a and 44b, separate from one another, with each section positioned adjacent to a side surface (24 and 26) of each fin shaped member 20. Each floating gate 44 is capacitively coupled to the side surface 24 and 26 of the fin shaped member 20.
A coupling gate 46 is capacitively coupled to the floating gate 44 and is "above" the floating gate 44. The coupling gate 46 also extends in the row direction and connects to all the coupling gates 46 of the fin shaped members 20 in the same row.
Finally an erase gate 48 is "above" the second region 32, and is insulated from the second region 32. The erase gate 48 also extends in the row direction and connects to all the erase gates 48 of the fin shaped members 20 in the same row. As discussed hereinabove, the operation of the memory cell 50 is fully disclosed in U.S. Patent 6,747,310 .
Referring to Figure 2 there is shown a top planar view of the memory array 50 shown in Figure 1. A cross-sectional view of the memory array 50 taken along the line A-A is shown in Figure 3A. A cross-sectional view of the memory array 50 taken along the line B-B is shown in Figure 3B. A cross-sectional view of the memory array 50 taken along the line C-C is shown in Figure 3C. A cross-sectional view of the memory array 50 taken along the line D-D is shown in Figure 3D.
Figures 4 show the steps of a manufacturing method for forming the non-volatile memory cell according to the present invention. Referring to Figures 4A-1 there is shown a cross-section views of the memory array 50 taken along the line A-A in the first step of making the array 50 of the present invention. A pad oxide 13 of approximately 17 nm is formed on the substrate 12. Buffered polysilicon 60 of about 20 nm is then deposited on the pad oxide 13. Thereafter, a layer of pad nitride 62 of about 45 nm is deposited on the layer of buffered polysilicon 60.
A masking step is formed with a mask 64. Openings are make in the mask 64 in the row direction of A-A and B-B (see Figures 4A-2 and 4B-2). Through openings in the mask, the pad nitride 62 and polysilicon 60 are etched until the pad oxide 13 is reached. However, the mask is not etched in the area above the second region 32, as shown in Figure 4C-2, nor in the column direction over the active region as shown in Figure 4D-2. The resultant structure is shown in Figures 4(A-D)-2.
The opening in the mask 64 is then used to further etch the pad oxide 13, and into the substrate 12. The mask 64 is then removed. The structure is then subject to an oxidation step causing silicon dioxide (of approximately 20 nm) to form along the side of the trench. Silicon dioxide 70 then fills the trench. The resultant structure is shown in Figures 4(A-D)-3.
A partial silicon dioxide etch is performed to partially remove the silicon dioxide 70 from the trench, leaving approximately 50 nm in the trench. Another silicon dioxide deposition step is performed to form a layer of silicon dioxide around the polysilicon 60 and the silicon nitride 62. The resultant structure is shown in Figures 4(A-D)-4.
Polysilicon 66 is deposited everywhere. The amount of polysilicon deposited is on the order of 80 nm. The resulting structure is shown in Figures 4(A-D)-5.
The polysilicon 66 is subject to a planarization step until the pad nitride 62 is reached. The resultant structure is shown in Figures 4(A-D)-6.
A second masking step is then performed. The mask 68 is opened in the region above the trench in the column direction as shown in Figures 4A-7 and 4B-7. Through the trench, the exposed polysilicon 66 is then etched until the silicon dioxide 70 is reached. This results in polysilicon 66 being formed along the sides of the trench and functions as the floating gate. The resultant structure is shown in Figures 4(A-D)-7.
A layer 72 of ONO (Silicon dioxide/silicon nitride/silicon dioxide), a composite material is deposited everywhere. The ONO layer 72 is on the order of 15 nm. Polysilicon 74 on the order of 100 nm is deposited everywhere. The polysilicon 74 forms the coupling gate 46. A layer 76 of silicon dioxide, on the order of 20 nm is deposited everywhere. A layer 78 of silicon nitride is then deposited on the silicon dioxide 76. The resultant structure is shown in Figures 4(A-D)-8.
Another masking step is performed. The mask however, is positioned over the coupling gates 46 (as shown in Figures 4B-9 and 4D-9), and openings are created everywhere else (as shown in Figures 4A-9 and 4C-9. After the openings are formed, the silicon dioxide layer 76 and the silicon nitride layer 78 are etched, with the polysilicon 74 forming an etch stop.
The mask is removed. The polysilicon 74 is etched. The composite layer 72 of ONO is then etched, until the polysilicon 66 is reached. The resultant structure is shown in Figures 4(A-D)-10.
Another masking step is formed. Openings are created along the line C-C which is "above" the erase gate 48, which is "above" the second region 32. Ion implantation is then performed everywhere, and through the "thinner" portion of the structure, which is not covered by the mask, the ion implantation forms the second region 32. The resultant structure is shown in Figures 4(A-D)-11.
A reverse masking step is performed, i.e. where openings were created in the structure shown in Figures 4(A-D)-11, they are now filled (essentially along the lines C-C, and where a mask existed, it is now removed. The floating gate 66 which is exposed in the trench and the polysilicon 74 are removed from the trench adjacent to the fin shaped members 20. The resultant structure is shown in Figures 4(A-D)-12.
The word line oxide 80, which is silicon dioxide 80 is then deposited everywhere to a thickness between approximately 3.0-6.5 nm. Polysilicon 82 is then deposited to a depth of approximately 150 nm. The resultant structure is shown in Figures 4(A-D)-13.
The polysilicon 82 is then etched back by CMP (Chemical Mechanical Polishing), until the layer of oxide 76 is reached. A masking step is performed. Opening are created in the mask in all areas except along the row direction of A-A, B-B and C-C. The resultant structure is shown in Figures 4(A-D)-14.
Ion implant is performed forming the first regions 30. The resultant structure is shown in Figures 4(A-D)-15.
Inter Level Dielectric is then deposited and planarized. Bit line contacts are then made to the regions 30. The resultant structure is shown in Figures 4(A-D)-16.

Claims

A non-volatile memory cell (50) comprising:
a substrate layer (12);

a fin shaped semiconductor member (20) of a first conductivity type on said substrate layer having a first region (30) of a second conductivity type and a second region (32) of the second conductivity type, spaced apart from the first region with a channel region extending between the first region and the second region; said fin shaped semiconductor member (20) having a top surface (22) and two side surfaces (24 and 26) between the first region and the second region;

a word line (40) adjacent to the first region and capacitively coupled to said two side surfaces of a first portion of the channel region, wherein the word line (40) is electrically insulated from the top surface of the channel by means of a first insulation material (13) which is underneath a buffered polysilicon layer (60) which is underneath a second insulation material (62);

a floating gate (44) immediately adjacent to the word line (40), having two sections (44a and 44b), each of which is adjacent to a side surface (24 or 26) of said fin-shaped semiconductor member (20), and being capacitively coupled to the two side surfaces of a second portion of the channel region;

a coupling gate (46) above the floating gate (44), capacitively coupled to the floating gate (44), wherein the coupling gate (46) and the floating gate (44) are separated by means of an insulation layer (72), wherein the coupling gate extends parallel to the word line (40) and an erase gate (48); and

the erase gate (48) insulated from the second region and adjacent to the floating gate and coupling gate, wherein the erase gate (48) is parallel to the word line (40).
The non-volatile memory cell (50) of claim 1 wherein said coupling gate (46) is between the word line (40) and the erase gate (48), and is insulated therefrom.
The non-volatile memory cell (50) of claim 1 wherein the coupling gate (46) is insulated from the top surface (22) of the fin shaped semiconductor member (20) and is capacitively coupled to the two sections of the floating gate (44) positioned along the two side surfaces (24 or 26) of the fin shaped semiconductor member (20).
A non-volatile memory device comprising the non-volatile memory cell (50) of one of claims 1 to 3, wherein:
said fin shaped semiconductor member (20) further comprised a third region of the second conductivity type located midpoint between the first and second regions, and said top surface and said two side surfaces extend longitudinally between the first region and the second region;

said word line (40) comprises a pair of word lines, adjacent to the first region and the second regions respectively, and between the first region and the third region, and between the second region and the third region, respectively, and capacitively coupled to the two side surfaces of the fin shaped semiconductor member (20);

said floating gate (44) comprises a pair of floating gates, each adjacent to one of said word lines and between one of said word lines and the third region, each of said pair of floating gates has two sections, each of which is adjacent to a side surface of said fin-shaped semiconductor member and capacitively coupled to the two side surfaces (24 and 26) of the fin shaped semiconductor member (20);

said coupling gate (46) comprises a pair of coupling gates each capacitively coupled to a floating gate (44); and

said erase gate is capacitively compled to the top surface of the third region.
The non-volatile memory device of claim 4 wherein each of said pair of coupling gates is capacitively coupled to each of the sections of the floating gate positioned adjacent to the side surface of the fin shaped semiconductor member.
An array (10) of said non-volatile memory cells (50) according to one of claims 1 to 3, comprising:
a plurality of said fin shaped semiconductor members, said fin shaped semiconductor members are spaced from one another and are parallel, wherein said channel region extends between the first region and the second region in a first direction; wherein each word line extends in a second direction perpendicular to the first direction across a plurality of fin shaped semiconductor members;

wherein said coupling gate extends in the second direction across a plurality of fin shaped semiconductor members;

wherein said erase gate extends in the second direction across a plurality of fin shaped members; and

wherein the second region of each of the fin shaped members is connected to the second region of other fin semiconductor shaped members in the second direction.
The array of claim 6 wherein the coupling gate is positioned adjacent to the word line and to the erase gate in each of the fin shaped semiconductor members.
The array of claim 6 wherein each fin shaped member has a plurality of spaced apart first regions, with a bit line connecting to the plurality of first regions.
The array of claim 6 wherein said substrate layer is an insulator.
The array of claim 6 wherein said substrate layer is of the same material as said fin shaped semiconductor members.