Classifications

• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
  • G06F3/14—Digital output to display device ; Cooperation and interconnection of the display device with other functional units
• • G—PHYSICS
  • G06—COMPUTING; CALCULATING OR COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
  • G06F12/02—Addressing or allocation; Relocation
  • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
  • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
  • G06F12/0806—Multiuser, multiprocessor or multiprocessing cache systems
  • G06F12/0815—Cache consistency protocols
  • G06F12/0831—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
  • G06F12/0835—Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means for main memory peripheral accesses (e.g. I/O or DMA)
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
  • G09G5/001—Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
  • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
  • G09G5/363—Graphics controllers
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
  • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
  • G09G5/39—Control of the bit-mapped memory
  • G09G5/393—Arrangements for updating the contents of the bit-mapped memory
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2350/00—Solving problems of bandwidth in display systems
• • G—PHYSICS
  • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
  • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
  • G09G2360/00—Aspects of the architecture of display systems
  • G09G2360/12—Frame memory handling
  • G09G2360/121—Frame memory handling using a cache memory

Definitions

• the present invention relates to processing environments, and more particularly to processing memory requests in multi-processor systems.
• Some graphics processing systems include multiple processing units, e.g., a central processing unit (CPU) that assigns some graphics processing tasks to one or more graphics processing units (GPUs). For example, the CPU can assign rendering tasks to one or more GPUs.
• CPU central processing unit
• GPUs graphics processing units
• the CPU and each of the GPUs each have their own associated memory.
• the CPU can be coupled to a system memory and the GPU can be coupled to a local memory.
• the system memory can include a coherent memory.
• accesses to the GPU local memory are not coherent.
• software may have to be used to ensure coherency, creating a performance overhead.
• Embodiments described herein generally relate to providing a memory that includes a coherent memory in multi-processor systems.
• embodiments of the present invention can relate to providing a coherent memory in a memory coupled to a graphics processing unit (GPU).
• GPU graphics processing unit
• a processing system includes a first processing unit coupled to a first memory and a second processing unit coupled to a second memory.
• the second memory comprises a coherent memory and a private memory that is private to the second processing unit.
• a method of processing a memory request includes determining where a memory word associated with the memory request is located and responsive to the memory word being located in a memory, accessing the memory to process the request.
• the memory includes a coherent memory and a private memory private to the first processing unit.
• FIGS. 1-3 are illustrations of processing systems, according to embodiments of the present invention.
• FIG. 4 is an illustration of a graphics processing unit, according to an embodiment of the present invention.
• FIGS. 5-6 are flowcharts of exemplary methods of processing memory requests, according to embodiments of the present invention.
• FIGS. 7-8 are illustrations of processing systems, according to embodiments of the present invention.
• FIG. 1 shows the conventional processing system 100.
• Processing system 100 includes a central processing unit (CPU) 102, a graphics processing unit (GPU) 104, a system memory 1 18, and a GPU local memory 130.
• CPU 102 includes an execution engine 106, an address processing unit 108, a cache 1 10, and a northbridge (NB) 1 11.
• GPU 104 includes an execution engine 120, a cache 122, an address processing unit 124, and a northbridge 125.
• System memory 1 18 includes a coherent memory 132 and a noncoherent memory 134.
• GPU local memory 130 includes a visible memory 136 and a private memory 138.
• processing system 100 is not limited to the components shown in FIG. 1 and can include more components than those shown in FIG. 1.
• Execution engine 106 executes a variety of commands during the operation of
• CPU 102 Some of these commands require execution engine 106 to issue memory request to access stored information.
• address processing 108 When execution engine 106 issues a memory request for a memory word, address processing 108 initially translates the virtual address corresponding to the memory request to a physical address. Address processing unit 108 also inspects the virtual address and/or the physical address to determine where the requested memory word is located. If the requested memory word is located in coherent memory 132, cache 110 is queried to determine if it can service the memory request. For example, cache 1 10 can be queried to determine whether it is holding the requested memory word, and if so, whether the cache line that is holding the requested memory word is valid. If cache 1 10 cannot service the memory request, i.e., on a cache miss, the memory request must be serviced by coherent memory 132.
• NB 11 1 accesses coherent memory 132 to service the request.
• NB 1 1 1 can act as a multiplexer between CPU 102 and other elements of system 100.
• NB 1 1 1 can be termed a "memory controller.” If address processing unit 108 determines that the requested memory word is located in non-coherent memory 134, NB 1 1 1 accesses non-coherent memory 134 to service the request (without first accessing cache 110).
• the requested memory word may also be located in GPU local memory 130.
• the requested memory word can be located in visible memory 136.
• a request from CPU 102 to visible memory 136 can be a memory mapped I/O (MMIO) request.
• NB 111 communicates the request to NB 125 (e.g., over a peripheral component interconnect express (PCIE) path) .
• PCIE peripheral component interconnect express
• NB 125 is substantially similar to NB 111.
• NB 125 access visible memory 136 to obtain the requested memory word and communicates the memory word back to NB 1 1 1.
• GPU private memory 130 is private to GPU 104 (i.e., inaccessible to CPU 102).
• address processing unit 108 will generate a fault to prevent CPU 102 from accessing private memory 130.
• execution engine 120 of GPU 104 executes a variety of commands during the operation of GPU 104. In response to one or more of these commands, execution engine 120 can generate a memory request.
• the issued memory request includes a virtual requested memory address.
• GPU 104 first queries cache 122 to determine if it is holding the requested memory word (using the virtual memory address). If cache 122 is not holding the memory request or otherwise can not service the memory request, the memory word must be retrieved from memory.
• Address processing unit 124 translates the virtual address to a physical address and determines where the requested memory word is located. For example, if address processing unit 124 determines that the requested memory word is located in visible memory 136 or private memory 138 of GPU local memory 130, NB 125 interacts with GPU local memory 130 to service the request.
• NB 125 sends a request to CPU 102 to obtain the requested memory word. For example, if the requested memory word is located in coherent memory 132, NB 111 can access coherent memory 132 to service the request. In another embodiment, NB 1 11 can access cache 110 to service such a request. If the requested memory word is located in non-coherent memory 132, NB 1 1 1 can access non-coherent memory 134 to service the request.
• GPU local memory 130 All accesses to GPU local memory 130 are non-coherent. If coherency is required, it must then be provided by software, which results in considerable overhead. Furthermore, cache 122, which caches information stored in GPU local memory 130, is a non-coherent cache. In contrast to cache 110 of CPU 102, which incorporates a protocol, such as the MESI protocol, to allow for coherent sharing with other devices, cache 122 of GPU 104 does implement a protocol to allow for sharing among different devices.
• MESI protocol such as the MESI protocol
• a write combining module can be provided in each of CPU 102 and GPU 104. In doing so, multiple write requests can be combined so that the bandwidth for write requests to non-coherent memory can be similar to the bandwidth for write requests to coherent memory. However, similar caching optimizations for read requests are often not available. Thus, read requests to non-coherent memory (e.g., from CPU 102 to visible memory 136) can be at substantially smaller bandwidth than read requests to coherent memory. In some embodiments, read requests to non-coherent memory can be designated "non-performant" and rarely, if ever, used. Indeed, in an embodiment, read requests from CPU 102 to visible memory 136 can be at such a low bandwidth that address processing unit 108 can generate a fault, thus preventing CPU 102 from reading from, visible memory 136.
• a coherent memory is provided in a GPU local memory.
• some requests to the GPU local memory can be hardware coherent, i.e., coherency is ensured by the hardware without requiring software overhead.
• the coherent memory of the CPU e.g., included in system memory
• the coherent memory included in the GPU local memory can be essentially indistinguishable for a programmer writing code for the system.
• This simplified memory model can make programming much simpler because programs that access coherent memory no longer have specify which coherent memory is to be accessed.
• systems described herein may also have performance advantages because software overhead is no longer relied on to ensure coherence and read requests can be conducted at substantially higher bandwidth when they access coherent memory than when they access non-coherent memory.
• FIG. 2 shows a processing system 200, according to an embodiment of the present invention.
• the processing system 200 includes a first processor 202, a second processor 204, a system memory 218, and a memory 234.
• first and second processors 202 and 204 are a CPU and a GPU, respectively.
• CPU 202 includes an execution engine 206, an address processing unit 208, a cache 210, a NB 21 1 , a probe engine 214, and a probe filter 216.
• execution engine 206, address processing unit 208, cache 210, and NB 21 1 are substantially similar to execution engine 106, address processing unit 108, cache 110, and NB 111, respectively, of CPU 102 shown in FIG. 1.
• GPU 204 includes an execution engine 220, a cache 222, a an address processing unit 224, a probe engine 228, a reverse look up table 230, and a probe filter 232.
• execution engine 220, cache 222, address processing unit 224, and NB 225 are substantially similar to execution engine 120, cache 122, address processing unit 124, and NB 125, respectively, of GPU 104 shown in FIG. 1.
• System memory 218 includes a non-coherent memory 240 and a coherent memory
• GPU local memory includes a visible coherent memory 238, a visible non-coherent memory 239, and a private memory 236.
• a visible coherent memory 238, a visible non-coherent memory 239, and a private memory 236 As described above, performance for write requests to non-coherent memory can be improved through the use write combining.
• each of non-coherent memory 240 and visible non-coherent memory 238 can be termed a "write-combining memory” or a "write-combining heap.”
• System memory 218 and memory 234 can be formed out of conventional random access memories (RAM).
• system memory 218 can be formed out of a DDR2 or DDR3 RAM memory and memory 234 can be formed out of a DDR5 RAM memory.
• Address processing units 208 and 225 are processing units that are configured to translate virtual addresses to physical addresses. Furthermore, address processing units can also be configured to determine where physical addresses are located (e.g., among system memory 218 and GPU local memory 234). In an embodiment, address processing unit 208 and/or address processing unit 225 can include a translation lookaside buffer (TLB) that is used to translate virtual addresses into physical addresses.
• TLB translation lookaside buffer
• the operation of CPU 202 with respect to memory requests requesting a memory word located in non-coherent memory 240, visible non-coherent memory 239, and private memory 236 is substantially similar to the operation of CPU 102 with respect to a memory request requesting a memory word located in non-coherent memory 134, visible memory 136, and private memory 138, respectively.
• the operation of GPU 204 with respect to memory requests requesting a memory word located in private memory 236, visible non-coherent memory 239, and non-coherent memory 240 is substantially similar to the operation of GPU 104 with respect to a memory request requesting a memory word located in private memory 138, visible memory 136, and non-coherent memory 134, respectively.
• CPU 202 includes probe engine 214 and probe filter 216.
• Probe engine 214 is used to ensure coherence between cache 210 and coherent memory 242 and cache 222 and visible coherent memory 238. For example, if the requested memory word is located in coherent memory 240 of system memory 218, probe engine 214 generates probes that are sent to GPU 204. The probes are used to determine if cache 222 of GPU 204, is holding the requested memory word in a dirty cache line, i.e., in cache line holding a value that has been modified relative to the value in coherent memory 242. If cache 222 includes such a dirty cache line, GPU 204 will send the cached value back to system memory 218 in response to the probe. Additionally, if the request is a write request, the probe can require all caches to invalidate cache lines that are holding the requested memory word.
• the probe filter 216 is an optional optimization that can prevent some probes from being generated and transmitted when no other components has cached the requested memory word. In many processing systems, transmitting probes to different components in the system can occupy a valuable bandwidth. Furthermore, in many cases, the requested address will not be cached in the cache of another component in the system. To prevent probes from being generated and transmitted when no other component in system 200 has cached a requested memory word, probe filter 216 maintains a list of all addresses of system memory 218 that are cached on other components of system 200. By comparing the requested memory word to this list, probe filter 216 can prevent probes from being generated and transmitted when no other component in the system is caching that memory word.
• GPU 204 When GPU 204 receives probes from CPU 202, the probes are processed by probe engine 228. In response to the probe, GPU 204 can write dirty cache lines back to system memory 218, and, if necessary, invalidate a cache line that is holding the requested memory word.
• cache 222 of GPU 204 is a coherent cache that implements a protocol for coherent sharing with other devices, e.g., the MESI protocol.
• probe engine 214 similarly processes probes received from GPU 204.
• Cache 210 of CPU 202 is a physically tagged cache in which cache lines are tagged with physical addresses.
• cache 222 of GPU 204 is a virtually tagged cache with cache lines tagged with virtual addresses.
• the requested address is translated into a physical address using address processing unit 224 so that probe engine 214 of CPU 202 can compare the requested address with the addresses held in cache 210 in order to process the received probe.
• probe engine 214 of CPU 202 when probe engine 214 of CPU 202 generates a probe, the requested address is a physical address.
• probe engine 228 of GPU 204 cannot immediately query cache 222 because cache 222 for the requested memory word is virtually tagged.
• GPU 204 also includes a reverse lookup table 230.
• Reverse lookup table 230 is used to map the received physical address to a virtual address. After mapping the received physical address to a virtual address, probe engine 228 of GPU 204 can process the probe, as described above.
• CPU 202 and GPU 204 each include a single execution engine coupled to a cache and an address processing unit.
• CPU 202 and/or GPU 204 can be a multi processor system that includes more than one execution engine.
• a cache and an address processing unit can be replicated for each additional execution engine.
• a respective probe engine and probe filter can also be replicated for each additional execution engine.
• an additional cache 222, address processing unit 224, probe engine 228, and probe filter 232 can be provided.
• coherent memory 242 of system memory 218 and visible coherent memory 238 of GPU local memory 234 are both coherent, these two memories can be indistinguishable from the standpoint of a programmer.
• coherent memory 242 of system memory 218 and visible coherent memory 238 of GPU local memory 234 essentially are different parts of the same memory, thereby greatly simplifying the programming model.
• FIG. 3 shows a processing system 300, according to an embodiment of the present invention.
• System 300 is substantially similar to system 200 shown in FIG. 2, except that system memory 218 and GPU local memory 234 are replaced with a memory 302.
• system memory 218 and GPU local memory 234, which may have been implemented on separate dies, can be implemented on the same die in memory 302. In another embodiment, all of system 300 can be included on a single die.
• Memory 302 includes non-coherent memory 301, coherent memory 304, and a private memory 306. As shown in FIG. 3, GPU 204 must accesses NB 21 1 of CPU 202 to access memory 302. In alternate embodiments, NB 225 of GPU 202 may be able to directly access memory 302.
• accesses to private memory 306 are substantially similar to accesses to accesses of private memory 236, described with reference to FIG. 2.
• coherent memory 240 and visible coherent memory 238 of system 200 are implemented in memory 302 as coherent memory 304.
• coherent memory 240 and visible coherent memory 238 can be indistinguishable from the standpoint of a programmer.
• coherent memory 240 and visible coherent memory 238 can be combined into coherent memory 304.
• Accesses from CPU 202 and GPU 204 to coherent memory 304 are substantially similar to accesses from CPU 202 and GPU 204 to coherent memory 242 and visible coherent memory 238.
• non-coherent memory 240 and visible non-coherent memory 239 can be combined to forai non-coherent memory 301. Because memory accesses between CPU 202 and GPU 204 and the different coherent and non-coherent memories remain the same between systems 200 and 300, programs written for the processing system 200 can also be used on processing system 300, thereby obtaining the benefit of having multiple components formed on the same die without having to update the program.
• FIG. 4 shows a GPU 400, according to an embodiment of the present invention.
• GPU 400 includes a probe filter 402, a probe engine 406, an execution engine 410, a range checker 412, a first address processing unit 414, a cache 416, and a second address processing unit 422.
• probe filter 402, probe engine 406, and execution engine 410 are substantially similar to probe filter 232, probe engine 228, and execution engine 220, respectively, described referenced to FIGS. 2 and 3.
• GPU 400 is described with reference to the embodiment in which it is used in place of GPU 204 in systems 200 and 300. However, as would be appreciated those skilled in the relevant art(s), GPU 400 is not limited to that embodiment.
• cache 416 is a hybrid cache that includes a virtually tagged portion 418 and a physically tagged portion 420.
• portion 420 caches memory addresses that may be accessed by a CPU or other component of the system.
• Portion 420 can cache memory addresses located in visible coherent memory 238 and portion 418 can cache memory addresses located in private memory 236 via a NB such as NB 225 (NB 225 is omitted in FIG. 4 for the purposes of simplicity).
• NB 225 is omitted in FIG. 4 for the purposes of simplicity.
• a reverse lookup table is not needed because the only memory addresses that CPU 202 (or any other component in the system) can access, and thus the only memory addresses for which GPU 400 would receive probes are physically tagged.
• range checker 412 inspects the requested address to determine whether it is located in GPU coherent memory 238 or GPU private memory 236. If the requested address is within a range known to be located in GPU coherent memory 238, the requested address is immediately translated to a physical address using first address processing unit 414 and then portion 420 is queried to determine if it can service the request. On the other hand, if range checker 412 determines that the requested address is within a range known to be located in GPU private memory 236, portion 418 is queried to determine if it can service the memory request (without first translating the requested address). If the queried portion of cache 416 cannot service the request, i.e., on a cache miss, the operation of GPU 400 in servicing the memory request is substantially similar to the operation of GPU 204 in servicing a memory request on a cache miss.
• Second address processing unit 422 is used to translate virtual addresses in portion
• address processing unit 414 and address processing unit 422 are separate elements in GPU 400. In an alternate embodiment, address processing unit 414 and address processing unit 422 are the same address processing unit accessed at different points during the operation of GPU 400.
• FIGS. 7 and 8 show processing systems 700 and 800, respectively, according to embodiments of the present invention.
• Processing systems 700 and 800 are substantially similar to processing systems 200 and 300, respectively, except that processing systems 700 and 800 include GPU 400, shown in FIG. 4, instead of GPU 200 (range checker 412 is omitted from FIGS. 7 and 8 for simplicity).
• the use of a hybrid cache can simply operations between the CPU and GPU.
• GPU 400 does not include a reverse lookup table because all addresses that could be cached by cache 210 of CPU 202 are physically tagged in hybrid cache 416.
• FIGS. 2, 3, 7, and 8 conceptually show a connection between a CPU and a
• the different signals transmitted between the CPU and the GPU can be multiplexed over the same set of one or more busses (or traces). In another embodiment, a different bus or trace can be used for each of the different signals.
• FIG. 5 is a flowchart of an exemplary method 500 of processing a memory request, according to an embodiment of the present invention.
• Other structural and operational embodiments will be apparent to persons skilled in the relevant art(s) based on the following discussion.
• the steps shown in FIG. 5 do not necessarily have to occur in the order shown.
• the steps of FIG. 5 are described in detail below.
• step 502 a memory request is issued.
• execution engine For example, in FIG. 2, execution engine
• step 504 it is determined where the requested memory word is located. For example, in FIG. 2, address processing unit 208 or 224 determine where the requested memory word is located.
• step 506 it is determined whether a local cache can service the memory request. For example, the local cache can be queried to determine whether it is holding the request address and for the status of the cache line that is holding the requested memory word. For example, in FIG. 2, if address processing units 208 or 224 determines that the requested memory word is located in coherent memory 242 or visible coherent memory 238, respectively, caches 210 or 222, respectively, can be queried to determine whether they can service memory requests issued by execution engine 206 or execution engine 220, respectively. If the memory request hits on the local cache, method 500 proceeds to step 516. In step 516, the memory request is processed using the local cache.
• step 508 it is determined whether the requested address is located in private memory. If so, method 500 proceeds to step 518.
• step 518 the memory request is processed using the private memory. For example, in FIG. 2, if the requested address is located in private memory 236, NB 225 can access private memory 236 to service the request.
• step 510 it is determined whether the requested address is located in a remote memory. If so, method 500 proceeds to step 520.
• step 520 a request is sent to a remote node for service. For example, in FIG. 2, if the memory word requested by execution engine 220 of GPU 204 is located in system memory 218, NB 225 sends a request to CPU 202 for service. In an alternate embodiment, if the memory word requested by execution engine 206 of CPU 202 is located in GPU coherent memory 238, NB 211 sends a request for service to GPU 204.
• a local memory is used to process the memory request.
• system memory 218 or GPU local memory 234 can be used to process a request from execution engine 202 of CPU 202 or execution engine 220 of GPU 204, respectively.
• FIG. 6 is a flowchart of an exemplary method 600 of processing a memory request, according to an embodiment of the present invention.
• Other structural and operational embodiments will be apparent to persons skilled in the relevant art(s) based on the following discussion.
• the steps shown in FIG. 6 do not necessarily have to occur in the order shown.
• the steps of FIG. 6 are described in detail below.
• step 602 a remote request for service is received. For example, in FIGS. 2 and
• NBs 21 1 and 225 can receive requests for service.
• step 604 the memory request is processed using a local memory.
• NBs 21 1 and 225 can access system memory 218 or GPU local memory 234 to access a request memory word.
• some of the memory accesses described in methods 500 and 600 may require probes to be generated. For example, when a coherent memory is accessed, probes may need to be generated.
• a probe filter can be used to determine whether to transmit the probes to other devices in the system.
• the probe filter can be consulted before the probes are generated so that even on coherent memory accesses, probes may not need to be generated.
• Embodiments of the present invention may be used in any computing device where register resources are to be managed among a plurality of concurrently executing processes.
• embodiments may include computers, game platforms, entertainment platforms, personal digital assistants, and video platforms.
• Embodiments of the present invention may be encoded in many programming languages including hardware description languages (HDL), assembly language, and C language.
• HDL hardware description languages
• Verilog can be used to synthesize, simulate, and manufacture a device that implements the aspects of one or more embodiments of the present invention.
• Verilog can be used to model, design, verify, and/or implement the elements of systems 200, 300, 700, 800 and/or GPU 400, described with reference to FIGS. 2, 3, 7, 8, and 4, respectively.

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