EP2471088A1

EP2471088A1 - Method for producing a semiconductor wafer

Info

Publication number: EP2471088A1
Application number: EP10743044A
Authority: EP
Inventors: Jürgen Schwandner
Original assignee: Siltronic AG
Current assignee: Siltronic AG
Priority date: 2009-08-26
Filing date: 2010-08-11
Publication date: 2012-07-04
Also published as: US8343873B2; SG178470A1; KR20120048670A; WO2011023297A1; DE102009038941B4; KR101316364B1; CN102484042B; MY153463A; US20120149198A1; JP5458176B2; DE102009038941A1; JP2013502733A; CN102484042A

Abstract

The invention relates to a method for producing a semiconductor wafer, comprising in the following order: (a) removing material from both sides of the semiconductor wafer separated from a monocrystal; (b) chamfering the edge of the semiconductor wafer; (c) grinding the front and the back of the semiconductor wafer, wherein one side of the semiconductor wafer is held by means of a wafer holder, while the other side is worked with a grinding tool; (d) polishing at least one side of the semiconductor wafer with a polishing cloth that contains firmly bound abrasives; (e) treating both sides of the semiconductor wafer with an etching medium, wherein the material removal amounts to no more than 1 μm per side of the semiconductor wafer; (f) polishing a front of the semiconductor wafer using a polishing cloth containing firmly bound abrasives and at the same time polishing a back of the semiconductor wafer with a polishing cloth containing no abrasives, wherein however a polishing agent containing an abrasive is placed between the polishing cloth and the back of the semiconductor wafer; (g) polishing the edge of the semiconductor wafer; (h) polishing the back of the semiconductor wafer with a polishing cloth that contains firmly bound abrasives and at the same time polishing the front of the semiconductor wafer with a polishing cloth that contains no firmly bound abrasives, wherein a polishing agent containing an abrasive is placed between the polishing cloth and the front of the semiconductor wafer.

Description

Method for producing a semiconductor wafer

The invention relates to a method for producing a semiconductor wafer.

According to the prior art, semiconductor wafers are in a plurality of successive process steps

which are generally subdivided into the following groups: a) Production of a single crystal of semiconductor material

(Crystal pulling);

b) separating the semiconductor single crystal into individual wafers ("wafering", "sawing");

c) mechanical processing of the semiconductor wafers;

d) chemical processing of the semiconductor wafers;

e) chemo-mechanical processing of the semiconductor wafers;

f) thermal treatment of the semiconductor wafers and / or epitaxial coating of the semiconductor wafers.

In addition, there are a variety of secondary steps such as cleaning, measuring and packaging. The production of a semiconductor single crystal is usually carried out by pulling a single crystal from a melt (CZ or "Czochralski" method) or by recrystallization of a rod made of polycrystalline semiconductor material (FZ or "floating zone" method).

As a separation process, wire saws ("multi-wire slicing", MWS) and inner hole saws are known.

When wire sawing a plurality of semiconductor wafers is separated in one operation of a piece of crystal. The mechanical processing serves to remove seeding, remove the surface layers that are damaged by the rougher sawing processes or are contaminated by the saw wire, and above all, the global leveling of the semiconductor wafers. Here are surface loops (single-sided, double-sided) and lapping known, as well as mechanical

Edge processing steps.

In the case of one-side grinding, the semiconductor wafer is held on the back on a base ("chuck") and on the front by a cup grinding disk with rotation of the base and

Grinding wheel and slow radial feed leveled. Processes and devices for surface grinding of a semiconductor wafer are known, for example, from US Pat. No. 3,905,162 and US Pat. No. 5,400,548 or from EP-0955126. In this case, a semiconductor wafer is held with its one surface on a disk holder, while its opposite surface is processed with a grinding wheel by rotating disk holder and grinding wheel and pressed against each other. In this case, the semiconductor wafer is mounted on the disc holder so that its center substantially coincides with the center of rotation of the disc holder.

In addition, the grinding wheel is positioned so that the center of rotation of the semiconductor wafer passes into a working region or the edge region of the grinding wheel formed by teeth. This can, the entire surface of the

Semiconductor wafer be ground without any movement in the grinding plane. In simultaneous double-sided grinding (DDG), the wafer is floating freely between two mounted on opposite collinear spindles

Grinding wheels simultaneously machined on both sides and thereby largely free of constraining forces axially between a front and back acting water (hydrostatic principle) or air cushion (aerostatic principle) out and radially loose from a surrounding thin guide ring or individual

Radial spokes prevented from swimming away.

During lapping, the semiconductor wafers are moved under a certain pressure while supplying a slurry containing abrasive materials between an upper and a lower working disk, which are usually made of steel and are usually provided with channels for better distribution of the lapping agent, whereby semiconductor material is removed.

DE 103 44 602 A1 and DE 10 2006 032 455 A1 disclose methods for simultaneous simultaneous grinding of both sides of a plurality of semiconductor wafers with a movement sequence similar to that of lapping, but characterized in that abrasive is used which is fixed in working layers ("films").

"Cloths"), which is on the work disks

are applied. Such a method is called

"Fine grinding with lapping kinematics" or "Planetary Päd Grinding" (PPG).

Working shifts used at the PPG were based on the two

Working disks are glued, for example, described in US 6,007,407 A and US 6,599,177 B2. During processing, the semiconductor wafers are in thin guide cages, so-called.

Carrier discs, inserted, the corresponding openings for

Have recording of the semiconductor wafers. The LauferScheiben have an external toothing, which engages in a rolling device of the inner and outer ring gear and are moved by means of this, in the formed between the upper and lower working disk, working gap.

The edge of the semiconductor wafer, including any mechanical markings such as a

Orientation notch ("notch") is usually also processed (edge rounding, "edge-notch-grinding"). To do this

conventional grinding steps with profiled grinding wheels or belt grinding method with continuous or periodic tool feed used.

These edge rounding methods are necessary because the edge is particularly susceptible to breakage in the unprocessed state and the semiconductor wafer can already be damaged by slight pressure and / or temperature stresses in the edge region.

In a later processing step, the ground and treated with an etching medium edge of the disc is usually polished. In this case, the edge of a centrally rotating semiconductor wafer is pressed with a certain force (contact pressure) against a centrally rotating polishing drum. From US 5,989,105 such a method for edge polishing is known in which the polishing drum from a

Aluminum alloy is composed and with a polishing cloth

is charged. The semiconductor wafer is usually fixed on a flat disk holder, a so-called chuck. The edge of the semiconductor wafer protrudes beyond the chuck so that it is freely accessible to the polishing drum.

The group of chemical processing steps includes

usually wet-chemical cleaning and / or etching steps.

The group of chemo-mechanical processing steps includes polishing steps with which the surface is smoothed by partial chemical reaction and partial mechanical removal of material (abrasion) and residual damage to the surface is removed. While the single-sided polishing processes generally lead to poorer plane parallelism, double-sided polishing processes produce semiconductor wafers with improved flatness.

After the grinding, cleaning and etching steps according to the prior art, a smoothing of the surface of the

Semiconductor wafers through removal polishing. When polishing in one side During processing, semiconductor wafers ("single-side polishing", SSP) are held back on a carrier plate with putty, by vacuum or by adhesion

Double-side polishing (DSP), semiconductor wafers are loosely inserted into a thin toothed disc and polished simultaneously "free floating" between an upper and a lower, with a polishing cloth occupied polishing plate front and back.

Furthermore, the front sides of the semiconductor wafers are often polished without haze, for example with a soft polishing cloth with the aid of an alkaline polishing sol. In the literature, this step is often called CMP polishing ("chemo-mechanical polishing"). CMP processes are

for example disclosed in US 2002-0077039 and in US 2008-0305722.

Also known in the art are the so-called "Fixed Abrasive Polishing" (FAP) technologies, in which the

A polishing step using such a FAP polishing cloth is hereinafter referred to as FAP step for short / 55491 A1 describes a two-stage polishing process, with a first FAP polishing step and a subsequent second CMP polishing step In CMP, the polishing cloth does not contain a bonded abrasive Abrasive is here as in a DSP step in the form of a suspension between the silicon wafer and the Such a two-stage polishing method is used in particular to eliminate scratches that the FAP step has left on the polished surface of the substrate. [0003] German patent application DE 102 007 035 266 A1 describes a method for polishing a substrate made of silicon material comprising two polishing steps of the FAP type, which characterized in that in a polishing step a

Poliermittelsuspension, the unbound abrasive than

Solid is brought between the substrate and the polishing cloth, while in the second polishing step in place of the polishing agent suspension occurs a polishing agent solution which is free of solids.

Often, semiconductor wafers are made with an epitaxial

Layer provided, ie with a monocrystalline grown layer with the same crystal orientation on which later semiconductor devices are applied. such

epitaxially coated or epitaxially coated semiconductor wafers have certain advantages over semiconductor wafers made of homogeneous material, for example the prevention of a

Charge reversal in bipolar CMOS circuits followed by device short-circuit ("latch-up" problem), lower

Defect densities (eg reduced number of COPs

("Crystal-originated particles") and the absence of a significant oxygen content, whereby a short circuit risk can be excluded by oxygen precipitates in device-relevant areas.

It is crucial how the mechanical and chemo-mechanical or purely chemical process steps described above are arranged in a process sequence for producing a semiconductor wafer.

It is known that the polishing steps such as SSP, DSP and CMP, the etching treatments and the Epitaxieschritt to a

Deterioration of the flatness of the semiconductor wafer

especially in the edge area lead.

Therefore, efforts have been made in the prior art to minimize material removal during polishing, in order to minimize the deterioration of the flatness to a minimum. In US 5942445 A, it is proposed to separate a semiconductor wafer from the crystal (sawing), to round the edge of the semiconductor wafer, then to perform a grinding step, which may include double-side grinding and single-side grinding of the front and back sides of the semiconductor wafer, the semiconductor wafer to an alkaline wet etching and finally polish the semiconductor wafer by means of DSP. The double side grinding can also be replaced by a lapping step. After wet etching, plasma etching can also be performed. Finally, the grinding steps and that

Wet etching can be replaced by a plasma etching.

The DSP polished semiconductor wafers obtainable by this process have unsatisfactory edge geometry due to the use of wet chemical treatments as well as plasma assisted chemical etching (PACE). At best, semiconductor wafers are acceptable

Flatness values available, if always an edge exclusion of at least 2 mm is used, cf. ITRS Roadmap.

In particular, the nanotopology is adversely affected by etching. In order to improve the nanotopology after the etching step, an increased material removal is necessary with DSP, which in turn negatively affects the geometry in the edge region

affected.

In order to provide semiconductor wafers for future generations of technology that meet the high demands on the edge region of the semiconductor wafer, ie

For example, to make the outermost edge area of the disc accessible to modern lithographic methods (immersion lithography), other approaches are needed.

From the problem described resulted in the

Task of the present invention, a novel process sequence for the production of semiconductor wafers

especially with a diameter of 450mm. The object of the invention is achieved by a method for producing a semiconductor wafer, comprising in the

specified order:

(A) two-sided material removing machining of the separated from a single crystal semiconductor wafer;

(b) rounding the edge of the semiconductor wafer;

(c) grinding front and back sides of the semiconductor wafer, each holding one side of the semiconductor wafer by means of a wafer holder while the other side is being processed with a grinding tool;

(d) polishing at least one side of the wafer with a polishing cloth that includes bonded abrasives;

(E) treatment of both sides of the semiconductor wafer with a corrosive medium at a material removal of not more than 1 micron per side of the semiconductor wafer;

(f) polishing a front side of the semiconductor wafer using a fixed abrasive abrasive cloth and simultaneously polishing a back side of the semiconductor wafer with a polishing cloth that does not contain an abrasive, but wherein an abrasive containing abrasive is placed between the polishing cloth and the back side of the wafer;

(g) polishing the edge of the wafer;

(h) polishing the back side of the wafer with a polishing cloth that includes bonded abrasive and simultaneous polishing of the front face of the wafer with a polishing cloth that does not contain a firmly bonded abrasive, wherein an abrasive containing polishing agent is placed between the polishing cloth and the face of the wafer. First, a semiconductor wafer is separated from a single crystal of semiconductor material grown by means of CZ or FZ. The separation of the semiconductor wafer is preferably carried out with a wire saw. The separation of the semiconductor wafer by means of wire saw is carried out as e.g. from US 4655191, EP 522 542 Al, DE 39 42 671 Al or EP 433 956 Al known.

The grown single crystal of semiconductor material is preferably a single crystal of silicon. In the Semiconductor wafer is preferably a monocrystalline silicon wafer.

The following are the essential steps of the

inventive method and its preferred embodiments explained in detail.

Step (a) - Two-sided material removing machining of the semiconductor wafer separated from a single crystal

In step (a) of the method according to the invention, both sides of the semiconductor wafer are processed to erode material.

This can be done by means of simultaneous double-side loops (DDG) or by means of PPG (Planetary Päd Grinding). A lapping step is less preferred in the process according to the invention.

State-of-the-art DDG machines like them

For example, in JP2000-280155A and JP2002-307303A described have two opposing grinding wheels whose axes of rotation are arranged collinear. During the grinding process, one between the grinding wheels

positioned disc-shaped workpiece on both sides simultaneously through the two rotating about its axis

Grinding wheels machined while passing through an annular

Holding and rotating device held in position while being rotated about its own axis. During the grinding process, the two grinding wheels are in axial

Delivered direction until the desired final thickness of the workpiece is reached.

The holding and rotating device can, for example

Include friction wheels that engage the edge of the workpiece. But it can also be a device that the workpiece

surrounds annular, and in a possibly on the circumference of the

Workpiece's existing groove, groove or notch (engl.

"Notch")

commonly referred to as "notch finger." To the entire To machine the surface of the workpiece, the workpiece is guided relative to the grinding wheels so that the abrasive

Abrasive segments of the grinding wheels describe a circular path which runs continuously over the workpiece center.

The workpiece is usually not firmly fixed, but is by two to both sides of the workpiece

mounted devices for hydrostatic storage,

Such devices are described in JP2002-280155 A. According to the prior art, those facing the workpiece are referred to as "hydropads"

Surfaces of the two hydropads designed flat and aligned parallel to each other. Each hydropad includes several

Hydrostatic bearing, between which grooves for discharging the medium used for the hydrostatic bearing (hereinafter referred to as "hydro-bearing medium") and the grinding coolant are arranged.

In the hydropads one or more measuring sensors are integrated, which during the grinding process, a measurement of the distance between the surface of the hydropads and the

Allow workpiece surface. This distance measurement is usually carried out with the help of dynamic pressure nozzles as a pneumatic dynamic pressure measurement. The dynamic pressure nozzles are designed as simple bores in the edges of the hydrostatic bearings which form the guide surfaces. In order to be able to measure the distance between the hydropads and the workpiece as close as possible to the location of the grinding process, the

Back pressure nozzles are usually mounted close to the edge of the hydropads adjacent to the grinding wheels.

PPG is a process for simultaneous double-sided grinding of a plurality of semiconductor wafers, each wafers being freely movable in a recess of one of a plurality of wafers rotated by a winder, and thereby on a cycloid

Trajectory is moved, the semiconductor wafers machined material between two rotating working discs with each work disk comprising a working layer containing bonded abrasive.

The use of a PPG method in step (a) of

method according to the invention is very particularly preferred.

Preferably, the PPG to be processed

Semiconductor wafer already has a rounded edge, but is subjected to such an edge rounding after performing the PPG step again. It has been found that such a two-part edge rounding step offers advantages, particularly as the PPG process of round-edged wafers appears to result in wafers of better geometry and nanotopography.

As a bonded in the working layers abrasive hard material with a Mohs hardness> 6 is preferred. Suitable abrasives are preferably diamond, silicon carbide (SiC),

Ceria (CeO ₂ ), corundum (alumina, Al ₂ O ₃ ), zirconia (ZrO ₂ ), boron nitride (BN, cubic boron nitride, CBN), further

Silicon dioxide (SiO ₂ ), boron carbide (B ₁ C) to much softer substances such as barium carbonate (BaCO ₃ ), calcium carbonate (CaCO ₃ ) or magnesium carbonate (MgCO ₃ ). However, particularly preferred are diamond, silicon carbide (SiC) and alumina (Al ₂ O ₃ , corundum).

The mean grain size of the abrasive should be less than 9 microns. The preferred size of the abrasive grains bonded in the working layers is in the case of diamond as

Abrasive on average 0.1 to 9 microns and more preferably 0.1 to 6 microns. The diamonds are preferably singly or as conglomerates ("clusters") in the bonding matrix of

Working shift involved. In the case of a conglomerate bond, the preferred grain diameters are the primary particle size of the cluster constituents.

Working layers with a ceramic bond are preferably used; a synthetic resin bond is particularly preferred; in the Case of working layers with conglomerates also a hybrid bonded system (ceramic bond within the

Conglomerates and resin bonding between conglomerates and working layer matrix).

The hardness of the working layer is preferably at least 80 Shore A. Particularly preferably, the working layer is constructed in multiple layers, wherein the top and bottom have different hardness, so that point elasticity and long-term compliance of the working layer can be adjusted independently of the process requirements.

Before the first use of a working layer, the abrasive materials incorporated in the working layer are preferably exposed by removing the uppermost layer in order to make them usable for the grinding process. This initial sharpening is carried out, for example, with the aid of grindstones or knives, which are preferably specially modified

Rotor discs are mounted and are guided by means of the rolling device on the two working wheels. The

Initial sharpening is also called "dressing" in English.

designated .

Preferably, the dressing is done with grindstones containing abrasive grain having a similar grain size to the abrasive in the working layers

"Sharpening stones" can for example be inserted annularly and in an externally toothed driving ring, so that they by means of the rolling devices of the grinding machine on

suitable way between the upper and lower working layer can be performed along. The sharpening stones preferably coat the entire surface of the working layers during the dressing, and even more preferably even run

temporarily or constantly something beyond its edge.

The abrasive grain is preferably bonded in the sharpening stone in such a way that the wear of the sharpening stones still permits an economical sharpening operation, but always during the sharpening process at least one layer of loose sharpening grain grain in the sharpening stone Work zone is located between sharpening stone and working surface, so that the sharpening mainly by free

(unbound) grain takes place. It has been shown that the sharpening process produces a disturbed near-surface layer in the working layer whose depth has approximately the extent of the sharpening grain. One

Sharpening stone with too coarse grain therefore imposes a structure on the working layer, which is characterized by the grain of the sharpening stone and not by the properties of the working layer. This is unfavorable for the desired uniform possible self-sharpening of the working layer in the following

Grinding operation. Too fine sharpening stone provides too little material removal and leads to an uneconomical

Sharpening. Finally, it has been found that sharpening is predominantly less directed by free sharpening grain as a result of the rolling motion of the sharpening grain during the sharpening movement

Forces on the working layer than sharpening with predominantly strong sharpening grains and a rougher but especially isotropic sharpened working layer results.

For sharpening or dressing the working layer, it is preferred to use a grain which is softer than that in the

Working layer used abrasive grains. Particularly preferred is the sharpening grains of corundum (Al ₂ O ₃ ).

By dull wear of the working layer

sanding fabric residues are preferably removed and constantly exposed new, easy-to-cut abrasive materials. This is a continuous operation until complete wear of the

Working shifts possible. This operating condition without

Interim re-sharpening intervention is called

"Self-sharpening work" of working shifts is designated and is particularly preferred

Surface of the working layers exposed grains in the

Surface of the semiconductor wafers and by the

Relative movement of working layer and semiconductor wafers Successful material removal is technically referred to as "multi-grain grinding with a geometrically indeterminate cutting edge".

Furthermore, it is preferred that the material removal by

predominantly surface engagement of the working layer is effected. By "surface engagement" is meant that the portion of the surface of the working layer which actually averages during grinding in contact with the

Semiconductor wafer is located, is significantly larger than the

Contact surface of the abrasive coating of a cup grinding disc during processing by means of a conventional

Cup grinding loop process, such as DDG or SSG. The carriers are preferably made of a completely metal-free material, such as a ceramic

Material, manufactured. But there are also rotor discs with a core of steel or stainless steel, for example, which are coated with a non-metallic coating,

prefers. Such a coating is preferably made of thermoplastic or thermosetting plastics, ceramics or organic-inorganic hybrid polymers, diamond

("Diamond-like carbon", DLC), but also from a hard chrome plating or nickel-phosphor coating.

In the case of carriers made of metal or with a metal core, the walls of the recesses for receiving the

Semiconductor wafers preferably lined with a ceramic material. As a result, there is no direct contact between the semiconductor wafer and the metal of the rotor disc.

Preferably, the recesses for receiving the

Semiconductor slices mounted in the rotor discs so eccentric with respect to the center of the respective rotor disc that the center of the rotor disc is outside the surface of the semiconductor wafers. A rotor disk preferably has three to eight recesses for semiconductor wafers. During one The grinding process is preferably five to nine

Runners simultaneously in the grinding machine.

The pressure with which the working layers are pressed against the semiconductor wafers during processing, and the

Path speed of the semiconductor wafers over the

Working shifts are during the main load step

preferably chosen so that the total removal rate, d. H. the sum of the removal rates on both sides of the semiconductor wafers is 2 to 60 μm / min. Under main load step is the

Understand processing phase, within which the largest proportion of the total removal of the entire grinding treatment is effected, wherein the processing phase is again a period to understand, during which all process parameters remain constant. As a rule, the main load step is the

Processing phase with the highest pressure or the proportionately longest duration or both. In the case of a working layer with abrasive grains of diamond having an average size of 3 to 15 μm, a removal rate between 2.5 and 25 μm / min is particularly preferred.

For the pressure that the working disks during the

Main load step on the semiconductor wafers, a range of 0.007 to 0.5 bar is preferred and a range of 0.012 to 0.3 bar particularly preferred. For this indication, the pressure on the total area of the for editing in the

Device located semiconductor wafers and not on the effective contact surface between the working layer and semiconductor wafers.

Furthermore, an opposite rotation of the working wheels with respect to the average rotational speed of the carriers during the main load step of processing is preferred.

In addition, it is particularly preferred that the pressures, speeds and thus web speeds for the various

Processing phases assume different values. Finally, it is also particularly preferred that in certain low-pressure processing phases ("Ausfeuer" or "spark out" phases) the Rotate working disks in the same direction. Such an outbreak phase is especially at the very end of the whole

Grinding treatment makes sense and therefore preferred. Preferably, during the processing, the temperature prevailing in the working gap formed between the working layers is kept constant. For this purpose, the carrier discs may have openings through which cooling lubricant can be exchanged between lower and upper working disk, so that upper and lower working layers always have the same temperature. This counteracts an undesired deformation of the working gap formed between the working layers by deformation of the working layers or working disks due to thermal expansion under alternating load. In addition, the cooling of those involved in the working layers

Abrasive improves and more uniform, and thus extends their effective life.

The cooling lubricant used preferably consists of a water-based mixture with viscosity-modifying

Additives such as glycols, short or longer chain polyethylene glycols, alcohols, sols or gels, and the like

Substances that are known as coolants or lubricants. A particularly preferred coolant but is also pure water without any addition.

The work gap on the implementation in the top

Working disk supplied amounts of cooling lubricant are preferably in the range between 0.2 and 50 l / min and more preferably between 0.5 and 20 l / min.

The preferred initial thickness before processing with step a) of the method according to the invention is 500 to 1000 μm. For silicon wafers having a diameter of 300 mm, an initial thickness of 775 to 950 μm is particularly preferred. The final thickness of the semiconductor wafers after machining

Step a) of the process according to the invention is preferably 500 to 950 μm and more preferably 775 to 870 μm. The total removal, d. H. the sum of the individual abrasions from both sides of the semiconductor wafer is preferably 7.5 to 120 μm and more preferably 15 to 90 μm.

Preferably, the shape of the working gap formed between the working layers is determined during grinding and the shape of the working surface of at least one working disk mechanically or thermally changed depending on the measured geometry of the working gap so that the working gap has a predetermined shape.

Preferably, the semiconductor wafers leave during the

Machining temporarily with a part of their area the working gap bounded by the working layers, wherein the maximum of the overflow in the radial direction is more than 0% and at most 20% of the diameter of the semiconductor wafer, wherein the

Overflow is defined as the relative to the working wheels measured in the radial direction length to the one

Semiconductor disk at a certain time during grinding beyond the inner or outer edge of the working gap is also.

Step (b) - rounding the edge of the semiconductor wafer:

In step (b), the semiconductor wafer is provided with a rounded edge.

For this purpose, the semiconductor wafer is fixed on a rotating table and delivered with its edge against the also rotating working surface of a machining tool. The processing tools used can be used as slices

be formed, which are attached to a spindle and Have peripheral surfaces that serve as work surfaces for processing the edge of the semiconductor wafer. The

Material-removing grain can be firmly anchored in the working surfaces of the processing tools. Usually that shows

Used grain on a coarse grain. The mean grain size is preferably greater than or equal to 10 μm.

These grinding processing tools are suitable for

Semiconductor wafer to be provided with a rounded edges. Usually, however, after edge rounding, a certain minimum roughness remains on the edge surface.

In a later processing step, the ground and treated with an etching medium edge of the disc is therefore in

Polished step (g).

In the case where PPG is used in step (a) of the method, it is preferable to use two edge grinding steps

with the first edge rounding done prior to the PPG step.

Step (c) grinding front and back of the

Semiconductor wafer In step c) of the process, both sides of the

Semiconductor wafer ground.

The grinding of front and back is preferably carried out sequentially.

These are held on a disc holder

Semiconductor wafer and an opposite grinding wheel rotated independently, wherein the grinding wheel is arranged laterally offset relative to the semiconductor wafer and thereby positioned so that an axial center of the

Semiconductor wafer enters a working area of the grinding wheel, wherein the grinding wheel with a Feed rate is moved in the direction of the semiconductor wafer, whereby the grinding wheel and semiconductor wafer are delivered to each other while semiconductor wafer and

Rotate the grinding wheel around parallel axes so that a

Surface of the semiconductor wafer is ground, wherein after reaching a certain material removal, the grinding wheel is guided back with a return speed.

It is preferred that the grinding wheel and semiconductor wafer be delivered by a distance of 0.03-0.5 μm during one revolution of the semiconductor wafer. Very particularly preferred is the choice of a delivery during a revolution of

Wafer of 0.03-0.1 μm. Preferably, a grinding wheel with a grain size greater than or equal to # 2000 is used, most preferably # 2000 - # 8000.

The grain size is usually indicated in # (mesh size) according to Japanese Industrial Standard JIS R 6001: 1998.

From the mesh numbers, a mean particle size can be calculated: When grinding wheels are used with fine grain, is often spoken of fine grinding. Such

Finishing wheels have e.g. a grit of # 1000 up to # 4000, e.g. that of Disco Corporation commercially

available.

When converting into particle sizes, it follows that

For example, # 1200 has an average particle size of 9.5 μm, # 5000 a mean particle size of 2.5 μm, and # 8000 a mean particle size of 1.2 μm. The mean particle sizes during fine grinding are thus approximately greater than or equal to 1 μm and less than or equal to 10 μm.

Particularly preferred is a sequence of two in series

switched grinding steps, wherein the first step with

Grinding wheels of a grain size of less than or equal to # 2000 are performed in order to achieve the highest possible removal rates and short process times (rough grinding) and the second, subsequent step with grinding wheels of a grain size greater than # 2000 and less than or equal to # 8000 takes place to be particularly smooth sanded wafers with a minimum damage of approx. 1 μm (fine sanding).

As total removal of the fine grinding step, 25 μm are preferred, with a symmetrical removal of approximately 12.5 μm per side.

The rotational speed of the grinding wheel is preferably 1000-5000 min ^-1 . The rotational speed of the semiconductor wafer is preferably 50-300 min ^-1 , very particularly preferably 200-300 min ^-1 .

The feed speed is preferably 10-20 μm / min. Step (d) - FAP polish at least one side of the

Semiconductor wafer

In step (d), at least one side of the semiconductor wafer is polished with a polishing cloth containing abrasives.

Preferably, in step (d), only the front side of the

Semiconductor disc polished.

Preferably, in step (d), only the back of the

Semiconductor disc polished. Preferably, in step (d), both the front and rear sides of the semiconductor wafer are polished.

During the polishing step is preferably a

Polishing agent solution, which is free of solids, placed between the side of the semiconductor wafer to be polished and the polishing cloth.

The polish solution is in the simplest case water, preferably deionized water (DIW) with the purity customary for use in the semiconductor industry.

The polish solution can also be compounds such as

Sodium carbonate (Na ₂ CO ₃ ), potassium carbonate (K ₂ CO ₃ ), sodium hydroxide (NaOH), potassium hydroxide (KOH), ammonium hydroxide

(NH ₄ OH), tetramethylammonium hydroxide (TMAH) or any mixtures thereof. Very particularly preferred is the use of potassium carbonate. In this case, the pH of the polishing agent solution is preferably in a range of 10 to 12 and the proportion of said compounds in the

Polishing agent solution is preferably 0.01 to 10 wt .-%, particularly preferably from 0.01 to 0.2 wt .-%.

The polish solution may also contain one or more further additives, for example surface-active additives such as wetting agents and surfactants, as protective colloids

acting stabilizers, preservatives, biocides,

Alcohols and complexing agents. A polishing cloth is used which contains an abrasive substance bound in the polishing cloth (FAP or FA cloth or FA pad).

Suitable abrasives include, for example, particles of oxides of the elements cerium, aluminum, silicon, zirconium and Particles of hard materials such as silicon carbide, boron nitride and diamond.

Particularly suitable polishing dishes have a surface topography embossed by replicated microstructures. These

For example, "posts" are in the form of pillars having a cylindrical or polygonal cross-section, or in the shape of pyramids or truncated pyramids Further descriptions of such polishing cloths are included, for example, in WO 92/13680 A1 and US 2005/227590 A1.

Even more preferred is the use of a polishing cloth with cerium oxide abrasives firmly bonded therein, such as e.g. in US 6602117 Bl.

The grain sizes of the FAP polishing cloths used (size of the bonded abrasive / particles) are preferably greater than or equal to 0.1 p and less than or equal to 1.0 micron.

Particularly preferred is a particle size of 0.1-0.6 μm.

Very particular preference is given to a particle size of 0.1-0.25 μm.

The FA-polishing is preferably carried out with ablations of greater than or equal to 1 micron per side, in this regard, the range of 1 - 3 microns is particularly preferred and quite

particularly preferably in a range of 1.5 to 2 microns is worked.

The discs processed by FA polishing are

preferably previously by means of grinding wheels a grain size of # 2000- # 8000 has been processed on both sides (fine grinding).

Step (e) - etching or cleaning the semiconductor wafer In step (e) of the method according to the invention, both sides of the semiconductor wafer are treated with a corrosive medium at a material removal of not more than 1 μm per side of the semiconductor wafer.

The minimum material removal per side of the semiconductor wafer is preferably 1 monolayer, i. about 0.1 nm. Preferably, a wet-chemical treatment of

Semiconductor disk with an acidic medium.

Suitable acidic media are aqueous solutions of hydrofluoric acid, nitric acid or acetic acid.

It is very particularly preferred for the semiconductor wafer to comprise a gaseous medium containing hydrogen fluoride and at least one surface of the semiconductor wafer

oxidizing oxidizing agent to treat.

In this case, it is particularly advantageous if the

gaseous medium, the surfaces of the semiconductor wafer with a relative velocity in the range of 40 mm / s to 300 m / s flows. The gaseous medium thus contains hydrogen fluoride and

at least one oxidizing agent. The oxidant must be able to remove the semiconductor material, e.g. Silicon, to oxidize. During the oxidation of a silicon surface arises

for example, a silica, preferably silica.

This in turn becomes chemical by hydrogen fluoride

attacked, wherein as reaction products hexafluorosilicic acid (H ₂ SiF ₆ ), silicon tetrafluoride (SiF ₄ ) and water are formed, which are removed by the flow of the gaseous medium. The gaseous medium may additionally contain further constituents, for example inert carrier gases such as nitrogen or Argon, for influencing the flow conditions and removal rates.

Preferably, at least one oxidizing agent selected from the group of nitrogen dioxide, ozone and chlorine is used. When using pure chlorine, the addition of

Water vapor required to access the silicon surface

oxidize. When using a mixture of nitrogen dioxide and chlorine as well as ozone and chlorine, the addition of chlorine serves to do this in the reaction of hydrogen fluoride with silica

released water for further Öxidation the

Silicon surface to use, and thus to prevent condensation of the liberated in the reaction water even at low flow rates and temperatures.

Particularly preferred is the use of ozone because of its high oxidation potential, the problem-free reaction products and the simple provision by in the

Semiconductor industry widespread ozone generators. To produce the gaseous medium, the constituents can be mixed in the desired ratio. Typically, the ratio of hydrogen fluoride to oxidant is selected in the range 1: 1 to 4: 1. The gaseous medium can

either by direct supply of the individual components in the process chamber or a mixer connected upstream

be fed or by the gaseous

Oxidizing agent by a liquid aqueous solution of

Hydrogen fluoride of suitable concentration directs. This can, for example, in a so-called. Wash bottle or a

comparable device happen. As the gaseous oxidant passes through the aqueous solution, it is enriched with water and hydrogen fluoride to form the required gaseous medium. At the same process parameters and constant ratio of hydrogen fluoride to oxidant show an increase in temperature and an increase in the concentrations of one

reaction-accelerating effect. The etching in the gas phase serves to reduce the roughness of the semiconductor wafer, whereby the required polishing removal can be reduced, as well as for removing

Impurities and reduction of surface defects of the crystal structure.

The described cleaning and etching processes take place

preferably as a single-disc treatment.

The SSEC 3400 ML from Solid State Equipment Corp. is particularly suitable for a wafer with a diameter of 450 mm that is particularly preferred in the context of the method according to the invention. / USA, which is designed for substrates up to a size of 500mm x 500mm.

Step (g) - polishing the edge of the wafer

In step (g) polishing of the edge of the

Semiconductor wafer.

Commercially available edge polishing machines are suitable for carrying out step (g) of the method according to the invention. From US 5,989,105 such a device for edge polishing is known in which the polishing drum from a

Aluminum alloy is composed and with a polishing cloth

is charged. The semiconductor wafer is usually on a flat

Disk holder, a so-called chuck, fixed. The edge of the semiconductor wafer protrudes beyond the chuck so that it is freely accessible to the polishing drum. A tilted by a certain angle to the chuck, centric

rotating and applied to the polishing cloth polishing drum and the chuck with the semiconductor wafer are each other

delivered and with a certain contact pressure below continuous supply of the polishing agent to each other

pressed.

In edge polishing, the chuck is rotated centrally with the semiconductor wafer held thereon.

Preferably, one turn of the chuck takes 20-300, more preferably 50-150 seconds (orbital period). A polishing drum coated with the polishing drum, which is preferably at a rotational speed of 300-1500 min ^"1 , more preferably 500-1000 min ^{" 1} , centrically rotated, and the Chuck are delivered to each other, the polishing drum under a

Angle of attack is made obliquely against the semiconductor wafer and the semiconductor wafer is fixed on the chuck so that it protrudes slightly beyond this and is thus accessible to the polishing drum.

The angle of attack is preferably 30-50 °.

Semiconductor wafer and polishing drum with a certain contact pressure with continuous feeding a

Polishing agent, preferably with a polishing agent flow of 0.1-1 liter / min, more preferably 0.15-0.40 liters / min, pressed together, wherein the contact pressure can be adjusted by weights attached to rollers, and preferably 1-5 kg, particularly preferably 2-4 kg.

Preferably after 2-20, particularly preferably after 2-8 revolutions of the semiconductor wafer or of the

Semiconductor disk holding Chuck polishing drum and

Semiconductor disc away from each other.

In these conventional edge polishing methods, the local

Geometry in the edge region of the semiconductor wafer usually negatively affected. This is related to the fact that with the relatively "soft edge polishing cloths" used here

(Usually, relatively soft and with silica sol applied polishing cloths used) not only the edge itself, but also an outer part on the front and / or back of the semiconductor wafer is polished, which can be explained by a "dipping" of the hard edge in the treated with polishing slurry polishing cloth. This leads to the fact that not only in the area of the actual edge is removed, but also in the adjacent area on the front and / or back. Therefore, the edge polishing of the semiconductor wafer in the method according to the invention is preferably carried out by fixing the

Semiconductor disk on a centrically rotating chuck,

Delivery of the semiconductor wafer and a tilted against the chuck, centrically rotating, with a polishing cloth

containing firmly bonded abrasive (FAP polishing cloth)

applied polishing drum and pressing together of

Semiconductor wafer and polishing drum with continuous supply of a polishing agent solution containing no solids.

By means of this it is possible to target the wafer edge

affect without affecting the adjacent region of the front and / or back of the semiconductor wafer and thus, for example, the desired geometry and

Adjust surface properties only on the wafer edge.

The FAP cloth used is much harder and far less compressible than the standard polishing cloths and also offers the advantage of removal without alkaline-charged silica sol. B. only by using an alkaline solution - to produce what also Poliermittelverschleppung on the wafer front and thus the additional negative

Influence of the wafer surface - in the form of z. B. increased defect rates such. B. LLS (localized light scatterers) due to etching - avoids.

In addition, a short soft polishing step with gently removing silica sol can follow on the same FAP polishing cloth, to realize a reduction of the edge roughness and -defektraten.

The two polishing steps can then be matched to each other, so that a targeted positive influence on the wafer edge geometry and surface without negative

Influencing the Waferpartialsites on the wafer front and make wafer back. Basically, therefore, the semiconductor wafer is preferably by means of a polishing drum, on the surface of a hard and less compressible polishing cloth is adhered, which includes firmly bonded abrasive, under feeding a

polished alkaline solution.

Preferably, then in a second step on the same polishing cloth a smoothing step with the supply of a silica sol, such as. B. Glanzox 3900 * with about 1 wt% SiO ₂ . * Glanzox 3900 is the product name for a polishing agent suspension offered as a concentrate by Fujimi Incorporated, Japan. The base solution of this concentrate has a pH of 10.5 and contains about 9% by weight colloidal SiO ₂ with a

average particle size of 30 to 40 nm.

It has been found that by such edge polishing with a FAP cloth observed in the prior art

Deterioration of the local geometry in the periphery of the

Semiconductor wafer is completely avoided.

Another advantage is that

Polishing agent carryover in the erosive step of the

Edge polishing and thus the occurrence of surface defects due to uncontrolled etching on the

Wafer surface can be avoided.

The polishing agent solution used in the edge polishing is in the simplest case water, preferably deionized water (DIW) with the usual purity for use in the semiconductor industry.

The polish solution can also be compounds such as

Sodium carbonate (Na ₂ COs), potassium carbonate (K ₂ CO ₃ ), sodium hydroxide (NaOH), potassium hydroxide (KOH), ammonium hydroxide

(NH ₄ OH), tetramethylammonium hydroxide (TMAH) or any mixtures thereof. Very particularly preferred is the use of potassium carbonate.

The pH of the polishing agent solution is preferably in a range of 10 to 12, and the proportion of said compounds in the polishing agent solution is preferably 0.01 to 10 wt%, particularly preferably 0.01 to 0.2 wt%. ,

acting stabilizers, preservatives, biocides,

Alcohols and complexing agents.

The preferred second step of edge polishing uses a polishing agent containing abrasive.

The proportion of the abrasive in the polishing agent suspension is preferably 0.25 to 20 wt .-%, particularly preferably 0.25 to 1 wt .-%. The size distribution of the abrasive particles is preferably monomodal.

The mean particle size is 5 to 300 nm, more preferably 5 to 50 nm. The abrasive material consists of a substrate material

mechanically ablative material, preferably one or more of the oxides of the elements aluminum, cerium or silicon. Particularly preferred is a polishing agent suspension containing colloidally disperse silica.

In the optional second step of the edge polish are in the

Unlike the first step, preferably no additives such as sodium carbonate (Na ₂ CO ₃ ), potassium carbonate (K ₂ CO ₃ ), sodium hydroxide (NaOH), potassium hydroxide (KOH), ammonium hydroxide (NH ₄ OH), tetramethylammonium hydroxide (TMAH) added.

However, the polishing agent suspension can contain one or more further additives, for example surface-active additives such as wetting agents and surfactants, acting as protective colloids

Stabilizers, preservatives, biocides, alcohols and complexing agents. Preferably, in step (g) of the method according to the invention, a polishing cloth is used which contains an abrasive substance bound in the polishing cloth (FAP cloth or FA pad).

Suitable abrasives include, for example, particles of oxides of the elements cerium, aluminum, silicon, zirconium and

Particles of hard materials such as silicon carbide, boron nitride and diamond.

Particularly suitable polishing cloths have a surface topography embossed by replicated microstructures. These

For example, "posts" are in the form of pillars having a cylindrical or polygonal cross section, or the shape of pyramids or truncated pyramids. Further descriptions of such polishing cloths are contained, for example, in WO 92/13680 A1 and US 2005/227590 A1.

Particularly preferred is the use of bound in the polishing cloth cerium oxide particles, see. also US6602117B1.

The mean particle size of the FAP polishing cloth is

preferably 0.1-1.0 μm, more preferably 0.1-0.25 μm. Particularly suitable for carrying out the method is a polishing cloth having a multilayer structure, comprising a layer

containing abrasive, a layer of rigid plastic and a resilient, non-woven layer, the layers being bonded together by means of pressure-sensitive adhesive layers.

The layer of rigid plastic preferably comprises polycarbonate. The polishing cloth may contain an additional layer of polyurethane foam.

One of the layers of the polishing cloth is yielding. The compliant layer is preferably a non-woven layer.

The compliant layer preferably comprises polyester fibers.

Particularly suitable is a layer of polyester fibers impregnated with polyurethane ("non-woven").

Due to the yielding position, the height of the fabric can adapt and follow continuous transitions. The resilient layer preferably corresponds to the bottom layer of the polishing cloth. Above this there is preferably one Foam layer, for example made of polyurethane, which is attached by means of an adhesive layer on the flexible layer. Above the PU foam is a layer of a harder, rigid material, preferably of a hard plastic, including itself

For example, polycarbonate is suitable. Above this stiff layer is the layer with the micro-replicas, ie the actual fixed abrasive layer.

The pliable situation can also be between the

Foam layer and the rigid layer or located directly below the fixed-abrasive layer.

The attachment of the different layers to each other is preferably carried out by means of pressure-sensitive adhesive layers (PSA).

The inventor has recognized that a polishing cloth without the PU foam layer always present in the prior art of FAP polishing cloths leads to good results. In this case, the polishing cloth comprises a layer of micro-replicas, a compliant layer and a layer of a rigid plastic such as polycarbonate, wherein the

compliant layer may be either the middle or the bottom layer of the polishing cloth.

The grain sizes of the FAP polishing cloths used are

preferably greater than or equal to 0.1 μm and less than or equal to 0.1 μm, particularly preferably 0.1-0.25 μm. Steps (£) and (h) - Double-sided polishing using FAP and CMP

Further, in step (f), polishing of a front side of the semiconductor wafer using a polishing cloth having firmly bonded abrasives and simultaneous polishing of one takes place

Back side of the semiconductor wafer with a polishing cloth that no Abrasive contains, however, in which an abrasive containing polishing agent between polishing cloth and back of the

Semiconductor wafer is brought. In step (g), edge polishing is performed as before

described.

Subsequently, in step (h) polishing of the back side of the semiconductor wafer is carried out with a polishing cloth which includes firmly bonded abrasive and simultaneous polishing of the front side of the semiconductor wafer with a polishing cloth which does not contain firmly bonded abrasive, wherein an abrasive containing polishing agent between polishing cloth and front of

Semiconductor wafer is brought.

Thus, in steps (f) and (h), the invention provides a combined simultaneous double-side polishing process by simultaneously applying a FAP polish and a CMP polish

Front / back and then take place on the back / front. On the conventional DSP step and the

subsequent separate CMP step is omitted.

Steps (f) and (h) can be carried out on existing equipment for double side polishing of semiconductor wafers, e.g. on a commercial double-side polishing machine of the AC2000 type by Peter Wolters, Rendsburg (Germany).

This polishing machine is equipped with a pin toothing of the outer and inner ring for driving the carriers. The system can be designed for one or more carriers. Because of the higher throughput, a system for a plurality of carriers is preferred, as described for example in DE-100 07 390 Al and in which the carriers move on a planetary orbit around the plant center. to

Plant include a lower and an upper polishing plate, which are horizontally freely rotatable and covered with polishing cloth. During polishing, the wafers are located in the recesses of the carriers and between the two

Polishing plates which rotate and apply a certain polishing pressure to them while a polishing agent is continuously supplied. It also the rotor discs in

Movement offset, preferably about rotating pin rings, which engage in teeth on the circumference of the rotor discs.

A typical carrier disc has recesses for receiving three half-discs. At the circumference of the recesses are deposits that the break-sensitive edges of

To protect semiconductor wafers, in particular against release of metals from the carrier body. The rotor disk body can be made of metal, ceramic, plastic, fiber-reinforced plastic or metal, for example

However, preference is given to steels, particularly preferably stainless chromium steel The recesses are preferably suitable for accommodating an odd number of semiconductor wafers with a diameter of .mu.m.sup.2 at least 200 mm, preferably 300 mm, very particularly preferably 450 mm and thicknesses of 500 to 1000 microns designed The polish used in polishing with a

Polishing cloth, which contains no firmly bonded abrasive, includes Abrasive. It is about a

Polishing agent suspension. The size distribution of the abrasive particles is preferably monomodal.

mechanically ablative material, preferably one or more of the oxides of the elements aluminum, cerium or silicon. The proportion of the abrasive in the polishing agent suspension is preferably 0.25 to 20 wt .-%, particularly preferably 0.25 to 1 wt .-%.

Particularly preferred is the use of colloidally disperse silica as polishing agent suspension.

For example, the aqueous polishing agents Levasil® 200 from Bayer AG and Glanzox 3900® from the company are used. Fujimi.

Preferably, the polishing agent contains additives such as

Sodium carbonate (Na ₂ CO ₃ ), potassium carbonate (K ₂ CO ₃ ), sodium hydroxide (NaOH), potassium hydroxide (KOH), ammonium hydroxide (NH ₄ OH), tetramethylammonium hydroxide (TMAH).

Stabilizers, preservatives, biocides, alcohols and complexing agents.

In the method according to the invention according to steps (f) and (h), a polishing cloth is also used which has a polishing cloth

bonded abrasive (FAP or FA cloth or FA Päd).

Suitable abrasives include, for example, particles of oxides of the elements cerium, aluminum, silicon, zirconium and particles of hard materials such as silicon carbide, boron nitride and diamond. Particularly suitable polishing cloths have a surface topography embossed by replicated microstructures. These

For example, "posts" are in the form of pillars having a cylindrical or polygonal cross-section, or the shape of pyramids or truncated pyramids.

Further descriptions of such polishing cloths are contained, for example, in WO 92/13680 A1 and US 2005/227590 A1.

Even more preferred is the use of a polishing cloth with cerium oxide abrasives firmly bonded therein, such as e.g. in US 6602117 Bl. The grain sizes of the FAP polishing cloths used (fixed abrasive / particle size) are preferably greater than or equal to 0.1 μm and less than or equal to 1.0 μm.

Particularly preferred is a particle size of 0.1-0.6 μm.

Very particular preference is given to a particle size of 0.1-0.25 μm.

A polishing plate is equipped with such a FAP cloth.

The second polishing plate is loaded with a conventional CMP polishing cloth.

The CMP polishing cloths used are

Polishing cloths with a porous matrix.

Preferably, the polishing cloth is made of a thermoplastic or thermosetting polymer. The material is a variety of materials into consideration, for example, polyurethanes, polycarbonate, polyamide, polyacrylate, polyester, etc. Preferably, the polishing cloth includes solid, microporous polyurethane. The use of polishing cloths is also preferred

foamed sheets or felt or fiber substrates impregnated with polymers.

Coated / impregnated polishing cloths can do this too

be designed that there is another in the substrate

Pore distribution and size as in the coating.

The polishing cloths can be largely flat or perforated.

To control the porosity of the polishing cloth, fillers may be incorporated into the polishing cloth.

Commercially available polishing cloths are e.g. the SPM 3100 from Rodel Inc. or the DCP series cloths and the IC1000 ™, Polytex ™ or SUBA ™ cloths from Rohm & Hass.

As previously mentioned, when polishing according to steps (f) and (h) of the process according to the invention can be carried out on a double-side polishing machine, as is the case, for example, with type AC 2000 from Peter Wolters / Rendsburg Technique obligatory one-sided

Veiling Polishing (CMP) is omitted because both the

Geometry determining as well as the surface quality determining polish completely on a machine type

be performed.

In the prior art, however, were the Abtrags- and

Veiling polishing (DSP and CMP) carried out separately and on different polishing machines. By CMP was in the prior art only the front of the

Semiconductor disc polished.

To achieve optimum wafer geometry, especially edge geometry (edge roll-off elimination), simultaneous double side polishing with planetary kinematics and

Combined use of Fixed Abrasive and CMP polishing cloths Advantages because the Fixed Abrasive polishing process allows it, due to the hard and optionally with an overflow

Shaped cloth to achieve the necessary polishing removal to dispense with a silica sol-containing component and also allows targeted influence on the edge region of the

To take semiconductor wafer. In addition, the simultaneous double-sided polish already integrates the CMP polish by using one of the

Polishing plate is equipped with a CMP polishing cloth on which the CMP step takes place. The Doppelseitenpolitur invention finds in two

Teilpolierschritten (f) and (h) instead, between which the

Semiconductor wafer according to step (g) is edge polished.

Preferably, a two-stage edge polishing is carried out, in which a first edge polish between the two partial steps of the double-sided polish (f) and (h) and the second

Edge polishing after completion of the complete

Double-side polishing, that is, after step (h) is performed, which allows the edge polish finer tune by this division in two steps and thus to influence the edge geometry of the semiconductor wafer as little as possible.

Both steps of edge polishing preferably take place by means of polishing cloths with abrasives firmly bonded therein. The second edge polishing is preferably carried out with the supply of an abrasive-containing polishing agent suspension, such as the optional soft polishing step described under (g). The proportion of abrasives in the polishing agent suspension is preferably 0.25 to 20 wt .-%.

The abrasives in the polishing agent suspension are

preferably selected from one or more of the group consisting of oxides of the elements aluminum, cerium or silicon.

Preferably, the polishing agent suspension is colloidally disperse silica. Preferably, the pH of the polishing agent suspension is 9 to 11.5.

Preferably, the pH of the polishing agent suspension is adjusted by addition of additives selected from the group consisting of sodium carbonate (Na ₂ CO ₃ ), potassium carbonate (K ₂ CO ₃ ), sodium hydroxide (NaOH), potassium hydroxide (KOH), ammonium hydroxide (NH ₄ OH ), Tetramethylammonium hydroxide (TMAH) or any mixtures of these compounds. In order to achieve a specifically desired defined back roughness of the polished wafer back, it may be advantageous to make additional one-sided FAP polishes of the back: This is preferably done in three steps each below

Using a polishing cloth, the one in the polishing cloth

Contains bonded abrasive and which is pressed with a polishing pressure on the back of the semiconductor wafer, wherein in the first step, a polishing agent which is free of solids, in the second and third steps, however, a polishing agent, containing abrasive material, is placed between the polishing cloth and the back side of the semiconductor wafer, wherein a polishing pressure in the first and second step of 8-15 psi is reduced to 0.5-5 psi in the third step.

The semiconductor wafer points to the flat surfaces of their

Back preferably has an average surface roughness R _a in a wide range of 0.3 to 4.5 nm, based on spatial wavelengths of less than or equal to 250 microns.

To determine the surface roughness is suitable

For example, a Chapman Surface Profiler MP 2000 with a 250 μm filter (spatial wavelengths greater than 250 μm = Waviness Data, see Chapman Technical Note-TG-1, Rev-01-09).

Is a high back roughness in o. G. Range desired, preferably FAP wipes are used with grain sizes of 0.5-1.0 microns. If low back roughness is desired, it is preferred to use FAP wipes with grain sizes of 0.1-0.25 μm.

The polishing agent solution in the first step of polishing the back of the silicon wafer of the method according to the invention is in the simplest case water, preferably deionized water (DIW) with that for use in the

Semiconductor industry usual purity.

The polish solution can also be compounds such as

Sodium carbonate (Na ₂ CO ₃ ), potassium carbonate (K ₂ CO ₃ ), sodium hydroxide (NaOH), potassium hydroxide (KOH), ammonium hydroxide (NH ₄ OH),

Tetramethylammonium hydroxide (TMAH) or any mixtures thereof. Very particularly preferred is the use of potassium carbonate. At the second step the polish of the back of the

Semiconductor wafer is a polishing agent containing abrasive used. The abrasive material consists of a substrate material

mechanically ablative material, preferably one or more of the oxides of the elements aluminum, cerium or silicon.

Particularly preferred is a polishing agent suspension containing colloidally disperse silica.

At the third step the polish of the back of the

Semiconductor wafer is also a polishing agent containing abrasives as used in the second step. Polishing pressure is reduced from 8-15 psi to 0.5-5 psi versus the first and second steps.

For carrying out these polishes, conventional polishing machines, e.g. the polishing machine "nHance 6EG" from Strasbaugh Inc.

The polishing machine from Strasbaugh Inc. has a polishing pad with a polishing cloth and a polishing head that processes a semiconductor wafer fully automatically. The polishing head is gimballed and includes a fixed base plate coated with a backing päd and a movable guide ring. Drilled holes in the base plate allow air cushions to be constructed in two concentric pressure zones, one inner and one outer, on which the The movable guide ring may be pressurized by means of a pneumatic bellows so as to bias and hold the polishing cloth in contact with the semiconductor wafer In the following, particularly preferred embodiments AF of the method according to the invention are shown. The abbreviations used PPG, DDG, FAP and CMP were previously explained. A

Separating a disk from single crystal - edge rounding - PPG

- edge rounding - double-sided fine sanding> double-sided FAP - gas phase etching - FAP on the back side and CMP on the backside> edge polishing - FAP back side and CMP front side - edge polishing

B

Separating a disk from single crystal - edge rounding - PPG

- edge rounding - double - sided fine sanding> FAP the

Back side - gas phase etching - FAP back and at the same time CMP back> Edge polishing - FAP back and

simultaneously CMP front side - edge polishing

Separating a disk from single crystal - edge rounding - PPG

- edge rounding - double - sided fine sanding> FAP the

Front side - gas phase etching - FAP the back and

at the same time CMP on the back> Edge polishing - FAP backside and CMP front side - Edge polishing

D

Disconnecting a disk from the single crystal DDG edge banding

- double - sided fine sanding> double - sided FAP gas phase etching - FAP on the back side and CMP on the back side>

Edge polishing - FAP backside and CMP front side at the same time

- Edge polishing

e

Disconnecting a disk from the single crystal DDG edge banding

- double-sided fine grinding> FAP the back - gas phase etching - FAP the back and at the same time CMP the Back> Edge Polishing - FAP Backside and CMP Front Side - Edge Polishing

F

Separating a single-crystal disk - DDG - edge rounding - double-sided fine sanding> FAP front side - gas phase etching - FAP on the backside and CMP on the backside> Edge polishing - FAP backside and CMP front side - Edge polishing

After the final step of edge polishing is preferably followed by a final cleaning.

In addition, the semiconductor wafer of a thermal

Treatment or provided with an epitaxial layer.

Claims

Claims:

1. Method for producing a semiconductor wafer,

comprising in the order given:

(b) rounding the edge of the semiconductor wafer;

(c) grinding front and back of the

Semiconductor disk, wherein each one side of the

Semiconductor wafer by means of a disc holder

is held while the other side is machined with a grinding tool;

(d) polishing at least one side of the semiconductor wafer with a polishing cloth, the firmly bonded abrasive

includes;

(E) treatment of both sides of the semiconductor wafer with a corrosive medium at a material removal of not more than lum per side of the semiconductor wafer;

(f) polishing a front side of the semiconductor wafer using a tufted abrasive cloth and simultaneously polishing a back side of the wafer

A wafer having a polishing cloth which does not contain abrasives, but which contains an abrasive

Polish between polishing cloth and back of the

Semiconductor wafer is brought;

(g) polishing the edge of the wafer;

(h) polishing the back surface of the wafer with a polishing cloth containing firmly bonded abrasive and simultaneous polishing of the front of the wafer

Semiconductor wafer with a polishing cloth, which contains no firmly bonded abrasive, wherein an abrasive

containing polishing agent between polishing cloth and

Front side of the semiconductor wafer is brought.

2. The method of claim 1, wherein in step (a) is a simultaneous double side grinding (DDG).

3. The method of claim 1 wherein step (a) is PPG.

4. The method of claim 3, wherein the semiconductor wafer is already provided prior to performing the PPG step according to step (a) with a rounded edge and the edge of the semiconductor wafer after performing the PPG step again in step (b) is rounded.

5. The method according to any one of claims 1 to 4, wherein the

Grinding of front and back in step (c) is carried out sequentially.

6. The method according to any one of claims 1 to 5, wherein the

Front and back grinding according to step (c) is performed with a grinding tool having a grain size of # 2000 - # 8000.

7. The method according to any one of claims 1 to 6, wherein in

Step (d) polishing the front side of the semiconductor wafer.

8. The method according to any one of claims 1 to 6, wherein in

Step (d) polishing the back side of the semiconductor wafer.

9. The method according to any one of claims 1 to 6, wherein in

Step (d) are polished front and back of the semiconductor wafer.

10. The method according to any one of claims 1 to 9, wherein in step (d) a polishing agent solution free of

Solids is placed between the side of the semiconductor wafer to be polished and the polishing cloth.

11. The method according to any one of claims 1 to 10, wherein the polishing cloth used in step (d) abrasive particles selected from the group consisting of silicon carbide, Boron nitride, diamond and oxides of the elements cerium, aluminum, silicon, zirconium.

12. The method of claim 11, wherein the grain sizes of the abrasive particles are greater than or equal to 0.1 microns and less than or equal to 1.0 microns.

13. The method according to any one of claims 1 to 12, wherein in step (f) the material removal per side of

Semiconductor wafer is at least 0.1 nm and at most 1 micron.

14. The method of claim 13, wherein in step (f) the semiconductor wafer with a gaseous medium containing hydrogen fluoride and at least one of the surface of the

Semiconductor disk oxidizing oxidizer is treated.

15. The method according to any one of claims 1 to 14, wherein in step (g) the edge of a centrically rotating

A semiconductor wafer is pressed with a certain force against a centrically rotating polishing drum, wherein the polishing drum with a polishing cloth, containing firmly bonded Abrasive, is applied and continuously a polishing agent solution containing no solids is supplied.

16. The method of claim 15, wherein the polishing cloth containing abrasives used in step (g) corresponds to a polishing cloth according to claims 11 or 12.

17. The method according to any one of claims 1 to 16, wherein the one used in step (f) and (h) polishing cloth containing abrasive corresponds to a polishing cloth according to claims 11 or 12.

18. The method of claim 17, wherein the other

Polishing cloth each contains no abrasive and has a porous matrix.

The method of any one of claims 1 to 18, wherein the abrasive containing abrasive used in steps (f) and (h) comprises particles selected from the group consisting of one or more of the oxides of the elements aluminum, cerium or silicon.

20. The method according to any one of claims 1 to 18, wherein the polishing agent is colloidally disperse silica.

21. The method according to any one of claims 1 to 20, wherein a two-stage edge polishing takes place, wherein a first edge polishing in step (g) and the second edge polishing takes place after step (h).

22. The method of claim 21, wherein the second

Edge polishing under supply of abrasive containing polishing agent suspension, which corresponds to the polishing agent of claims 19 or 20.

23. The method according to any one of claims 1 to 22, wherein an additional polishing of the back takes place after step (h), wherein the back in three steps each using a polishing cloth, the one in the

Polishing cloth bound abrasive and which is pressed with a polishing pressure on the back of the semiconductor wafer is polished, wherein in the first step, a polishing agent which is free of solids, in the second and third step, a polishing agent containing abrasive substances between polishing cloth and Back of the wafer is brought, wherein a polishing pressure in the first and second step of 8-15 psi in the third step is reduced to 0.5-5 psi.