EP2359462B1 - Variable speed device of the matrix converter type - Google Patents

Description

The present invention relates to a method for controlling a variable speed drive of the matrix converter type as well as to the corresponding speed controller implementing the method.

A matrix converter type speed variator comprises nine bidirectional switches arranged within a switching matrix comprising three switching cells. This switching matrix is connected on one side to three input phases u, v, w connected to an AC voltage source and on the other side to three output phases a, b, c connected to the load. The switches are individually controlled to connect an output phase to any one of the input phases.

Generally, the control commands of the switches of a matrix converter can be generated by different methods such as Space Vector Modulation (MVE), vector modulation or intersective modulation.

The document JP 2006 129620 A discloses a method of controlling a variable speed drive of the matrix type according to the preamble of claim 1.

The document IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, vol. 38, No. 3, June 1991 titled "A novel control method for forced commutated cycloconverters using instantaneous values of input line-to-line voltages" and written by Akio ISHIGURO, Takeshi FURUHASHI and Shigeru OKUMA describes a method of controlling a cycloconverter. This method consists in expressing the reference output voltages as a function of the input voltages and the cyclic switching ratios of the switches. The document proposes in particular to block permanently on a switching period a switch of a switching cell in order to increase up to its maximum modulation depth. We then get the input = 0.86XV output instead of the input = 0.75XV output.

• des pertes par commutation lorsque courant et tension de sortie sont en phase,
• des tensions de mode commun,

The introduction of a zero phase makes it possible to apply the blocking of one of the cells of the converter over a switching period. This makes it possible to increase the electrical performance at the output of the converter (higher average output voltage) and to limit the number of active states (or number of switches) to eight over a period of division of the two unblocked cells. This reduced number of active states over a switching period makes it possible to reduce by one third the number of switching operations and thus to reduce both the switching losses and the common mode voltages. However, the blocking of a cell during the cutting period does not make it possible to reach the optimum in terms of reduction:

• switching losses when current and output voltage are in phase,
• common mode voltages,

In fact, the blocked cell does not make it possible to systematically impose on a switching period the total sum that is the lowest in absolute value of the input voltages to the other two cells that switch.

The object of the invention is to propose a method of controlling a speed variator of the matrix converter type, this control method making it possible to achieve the optimum in terms of reducing switching losses and common mode voltages.

• trois phases d'entrée connectées à une source de tension alternative et trois phases de sortie connectées à une charge électrique,
• neuf interrupteurs électroniques bidirectionnels en courant et en tension répartis dans trois cellules de commutation et destinés à être commandés individuellement pour connecter une phase de sortie à l'une quelconque des phases d'entrée, la commutation des interrupteurs du convertisseur obéissant à une matrice de rapports cycliques permettant d'obtenir une tension de sortie à destination de la charge,
• ladite matrice de rapports cycliques comportant une phase nulle,
• caractérisé en ce que le procédé comporte :
• une étape de suppression de la phase nulle dans la matrice de rapports cycliques,
• une étape de positionnement d'une nouvelle phase nulle dans la matrice de rapports cycliques afin de réduire au maximum les pertes par commutation et les tensions de mode commun.

This object is achieved by a control method implemented in a speed variator of the matrix converter type comprising:

• three input phases connected to an AC voltage source and three output phases connected to an electrical load,
• nine bidirectional current and voltage electronic switches distributed in three switching cells and intended to be individually controlled to connect an output phase to any one of the input phases, switching the switches of the converter obeying a matrix of reports cyclic to obtain an output voltage to the load,
• said cyclic ratio matrix comprising a zero phase,
• characterized in that the method comprises:
• a step of suppressing the null phase in the cyclic ratio matrix,
• a step of positioning a new zero phase in the duty cycle matrix to minimize switching losses and common mode voltages.

According to one particularity, the step of positioning the new null phase consists of determining the input voltage vector (V _input ) and determining the location of the new null phase as a function of the position of this vector with respect to the different single input voltages.

According to another particularity, the control commands of the bidirectional electronic switches are determined by intersective type modulation.

According to another particularity, the intersective type modulation is implemented by applying the cyclic ratios of the cyclic ratio matrix in the form of modulators on two distinct carriers.

According to another particularity, the two carriers are of triangular shape, of frequency equal to the switching frequency, one of the carriers being the inverse of the other carrier.

According to another particularity, the modulants of a row of the cyclic ratio matrix always apply to the same carrier.

According to another feature, the line of the cyclic ratio matrix having the largest duty cycle is applied to neither of the two carriers and the two non-excluded lines are each compared to one of the carriers.

• trois phases d'entrée connectées à une source de tension alternative et trois phases de sortie connectées à une charge électrique,
• neuf interrupteurs électroniques bidirectionnels en courant et en tension répartis dans trois cellules de commutation et destinés à être commandés individuellement pour connecter une phase de sortie à l'une quelconque des phases d'entrée, la commutation des interrupteurs du convertisseur obéissant à une matrice de rapports cycliques permettant d'obtenir une tension de sortie à destination de la charge,
• ladite matrice de rapports cycliques comportant une phase nulle,
• caractérisé en ce que le variateur comporte :
• des moyens pour supprimer la phase nulle dans la matrice de rapports cycliques,
• des moyens pour positionner une nouvelle phase nulle dans la matrice de rapports cycliques afin de réduire au maximum les pertes par commutation et les tensions de mode commun.

The invention also relates to a variable speed drive type matrix comprising:

• three input phases connected to an AC voltage source and three output phases connected to an electrical load,
• nine bidirectional current and voltage electronic switches distributed in three switching cells and intended to be individually controlled to connect an output phase to any one of the input phases, switching the switches of the converter obeying a matrix of reports cyclic to obtain an output voltage to the load,
• said cyclic ratio matrix comprising a zero phase,
• characterized in that the variator comprises:
• means for suppressing the null phase in the cyclic ratio matrix,
• means for positioning a new null phase in the duty cycle matrix to minimize switching losses and common mode voltages.

According to a particularity, the variator comprises means for determining the input voltage vector and for determining the location of the new zero phase as a function of the position of this vector with respect to the different single input voltages.

According to another particularity, the control commands of the bidirectional electronic switches are determined by intersective type modulation.

According to another particularity, the intersective type modulation is implemented by applying the cyclic ratios of the cyclic ratio matrix in the form of modulators on two distinct carriers.

According to another particularity of the variable speed drive, the two carriers are of triangular shape, of frequency equal to the switching frequency, one of the carriers being the inverse of the other carrier.

• la figure 1 représente schématiquement le principe de réalisation d'un variateur de vitesse de type convertisseur matriciel,
• la figure 2 représente schématiquement le principe de fonctionnement du procédé de commande de l'invention,
• la figure 3 illustre le principe de fonctionnement du sélecteur d'entrée utilisé dans le convertisseur virtuel de l'invention,
• la figure 4 illustre le principe de fonctionnement du sélecteur de sortie utilisé dans le convertisseur virtuel de l'invention,
• les figures 5A et 5B montrent les différences entre les potentiels des phases d'entrées utilisés pour justifier de modifier l'emplacement de la phase nulle,
• la figure 6 représente les différents secteurs de positionnement du vecteur tension d'entrée permettant d'indiquer l'emplacement de la nouvelle phase nulle,
• la figure 7 représente les deux porteuses x et y triangulaires inversées utilisées pour définir la modulation de largeur d'impulsions,
• la figure 8 illustre le principe de choix de la première ou de la seconde porteuse,
• la figure 9 représente un exemple de modulation intersective effectuée à l'aide des deux porteuses choisies pour l'invention.

Other features and advantages will appear in the detailed description which follows with reference to an embodiment given by way of example and represented by the appended drawings in which:

• the figure 1 schematically represents the embodiment of a speed converter of the matrix converter type,
• the figure 2 schematically represents the operating principle of the control method of the invention,
• the figure 3 illustrates the operating principle of the input selector used in the virtual converter of the invention,
• the figure 4 illustrates the operating principle of the output selector used in the virtual converter of the invention,
• the Figures 5A and 5B show the differences between the input phase potentials used to justify changing the location of the null phase,
• the figure 6 represents the different sectors of positioning of the input voltage vector making it possible to indicate the location of the new null phase,
• the figure 7 represents the two inverse triangular x and y carriers used to define the pulse width modulation,
• the figure 8 illustrates the principle of choosing the first or the second carrier,
• the figure 9 represents an example of intersective modulation carried out using the two carriers chosen for the invention.

With reference to the figure 1 a matrix converter-type speed variator comprises nine bidirectional current and voltage switches of the double IGBTs + antiparallel diode series or RB-IGBT (for Reverse Blocking IGBT which has two IGBT switches) arranged in the form of a matrix switching circuit comprising three switching cells A, B, C of three switches each. The drive further comprises three input phases u, v, w connected to an AC voltage source and three output phases a, b, c connected to an electrical load (not shown) to be controlled.

Each of the nine bidirectional switches is individually controlled to connect an output phase a, b, c to any of the input phases u, v, w. The bidirectional switches are controlled from a 3X3 control matrix comprising the cyclic ratios of the switches of the switching matrix. Each switching cell A, B, C controls the voltage on an output phase a, b or c from the cyclic ratios of three switches connected to the three input phases u, v, w. Only one switch per switching cell A, B, C can be controlled in the closed state. On the figure 1 , the points designated fau, fav, faw, fbu, fbv, fbw, fcu, fcv, fcw each represent a bidirectional switch.

By convention, the switches of each switching cell are numbered from 1 to 3. Thus, to identify the active state of the switching matrix, the number of the closed switch in each cell is indicated. For example, the active state 131 means that the top switch (fau-1) of the cell A is closed, that the bottom switch (fbw-3) of the cell B is closed and that the top switch (fcu-1) of cell C is closed.

The 3X3 control matrix is as follows: $$\mathrm{M}=\left\{\begin{array}{ccc}{\mathrm{at}}_{\mathrm{u}}& {\mathrm{b}}_{\mathrm{u}}& {\mathrm{vs}}_{\mathrm{u}}\\ {\mathrm{at}}_{\mathrm{v}}& {\mathrm{b}}_{\mathrm{v}}& {\mathrm{vs}}_{\mathrm{v}}\\ {\mathrm{at}}_{\mathrm{w}}& {\mathrm{b}}_{\mathrm{w}}& {\mathrm{vs}}_{\mathrm{w}}\end{array}\right\}$$

• au, a_v, a_w sont les rapports cycliques respectifs des interrupteurs fau, fav, faw,
• b_u, b_v, b_w sont les rapports cycliques respectifs des interrupteurs fbu, fbv, fbw,
• c_u, c_v, c_w sont les rapports cycliques respectifs des interrupteurs fcu, fcv, fcw.

In which :

• at, a, _v , a _w are the respective duty cycles of the switches fau, fav, faw,
• b _u , b _v , b _w are the respective duty cycles of the switches fbu, fbv, fbw,
• c _u , c _v , c _w are the respective duty cycles of the switches fcu, fcv, fcw.

It is known from the document of the prior art IEEE TRANSACTIONS ON INDUSTRIAL ELECTRONICS, vol. 38, No. 3, June 1991 titled "A novel control method for forced commutated cycloconverters using instantaneous values of input line-to-line voltages" and written by Akio ISHIGURO, Takeshi FURUHASHI and Shigeru OKUMA to block one of the three switching cells A, B, C to increase the modulation depth to 0.86. For this, one of the cyclic ratios of the blocked switching cell is set to one. This is for example the cyclical report to the first switch fau of the switching cell A. This gives the following control matrix: $$\mathrm{M}=\left\{\begin{array}{ccc}1& {\mathrm{b}}_{\mathrm{u}}& {\mathrm{vs}}_{\mathrm{u}}\\ 0& {\mathrm{b}}_{\mathrm{v}}& {\mathrm{vs}}_{\mathrm{v}}\\ 0& {\mathrm{b}}_{\mathrm{w}}& {\mathrm{vs}}_{\mathrm{w}}\end{array}\right\}$$

However, it is known that the reference output voltages depend on the input voltages and the cyclic ratios. In a three-phase network, it is sufficient to control two of the three compound voltages (i.e. the voltages between two phases) to determine the system. We then obtain the following relations: $$\{\begin{array}{l}{{\mathrm{u}}^{*}}_{\mathrm{ab}}={\mathrm{b}}_{\mathrm{uv}}\cdot {\mathrm{u}}_{\mathrm{uv}}+{\mathrm{b}}_{\mathrm{vw}}\cdot {\mathrm{u}}_{\mathrm{vw}}+{\mathrm{b}}_{\mathrm{uw}}\cdot {\mathrm{u}}_{\mathrm{uw}}+{\mathrm{b}}_{\mathrm{u}}\cdot {\mathrm{u}}_{\mathrm{uu}}\\ {{\mathrm{u}}^{*}}_{\mathrm{ac}}={\mathrm{vs}}_{\mathrm{uv}}\cdot {\mathrm{u}}_{\mathrm{uv}}+{\mathrm{vs}}_{\mathrm{vw}}\cdot {\mathrm{u}}_{\mathrm{vw}}+{\mathrm{vs}}_{\mathrm{uw}}\cdot {\mathrm{u}}_{\mathrm{uu}}+{\mathrm{vs}}_{\mathrm{u}}\cdot {\mathrm{u}}_{\mathrm{uu}}\end{array}$$

• u*_ab désigne la tension de référence de sortie entre les phases de sortie a et b,
• u*_ac désigne la tension de sortie de référence entre les phases de sortie a et c,
• b_uv représente le rapport cyclique de la combinaison d'interrupteurs fau+fbv ou fbu+fav, selon le signe des tensions d'entrée et de sortie,
• b_vw représente le rapport cyclique de la combinaison d'interrupteurs fav+fbw ou faw+fbv, selon le signe des tensions d'entrée et de sortie,
• b_uw représente le rapport cyclique de la combinaison d'interrupteurs fau+fbw ou faw+fbu, selon le signe des tensions d'entrée et de sortie,
• b_u représente le rapport cyclique de l'interrupteur fbu,
• c_uv représente le rapport cyclique de la combinaison d'interrupteurs fau+fcv ou fav+fcu, selon le signe des tensions d'entrée et de sortie,
• c_vw représente le rapport cyclique de la combinaison d'interrupteurs fav+fcw ou faw+fcv, selon le signe des tensions d'entrée et de sortie,
• c_uw représente le rapport cyclique de la combinaison d'interrupteurs fau+fcw ou faw+fcu, selon le signe des tensions d'entrée et de sortie,
• c_u représente le rapport cyclique de l'interrupteur fcu.

In which :

• u * _ab designates the output reference voltage between the output phases a and b,
• u * _ac denotes the reference output voltage between the output phases a and c,
• b _uv represents the duty cycle of the combination of fau + fbv or fbu + fav switches, according to the sign of the input and output voltages,
• b _vw represents the duty cycle of the combination of switches fav + fbw or faw + fbv, according to the sign of the input and output voltages,
• b _uw represents the duty cycle of the combination of switches fau + fbw or faw + fbu, according to the sign of the input and output voltages,
• b _u represents the duty cycle of the switch fbu,
• c _uv represents the duty cycle of the combination of switches fau + fcv or fav + fcu, according to the sign of the input and output voltages,
• c _vw represents the duty cycle of the combination of switches fav + fcw or faw + fcv, according to the sign of the input and output voltages,
• c _uw represents the duty cycle of the combination of switches fau + fcw or faw + fcu, according to the sign of the input and output voltages,
• c _u represents the duty cycle of the fcu switch.

Since u _uv + u _vw + u _wu = 0, we obtain: $$\{\begin{array}{l}{{\mathrm{u}}^{*}}_{\mathrm{ab}}={\mathrm{b}}_{\mathrm{uv}}\cdot {\mathrm{u}}_{\mathrm{uv}}+{\mathrm{b}}_{\mathrm{vw}}\cdot \left({\mathrm{u}}_{\mathrm{seen}}+{\mathrm{u}}_{\mathrm{uw}}\right)+{\mathrm{b}}_{\mathrm{uw}}\cdot {\mathrm{u}}_{\mathrm{uw}}+{\mathrm{b}}_{\mathrm{u}}\cdot {\mathrm{u}}_{\mathrm{uu}}\\ {{\mathrm{u}}^{*}}_{\mathrm{ac}}={\mathrm{vs}}_{\mathrm{uv}}\cdot {\mathrm{u}}_{\mathrm{uv}}+{\mathrm{vs}}_{\mathrm{vw}}\cdot \left({\mathrm{u}}_{\mathrm{seen}}+{\mathrm{u}}_{\mathrm{uw}}\right)+{\mathrm{vs}}_{\mathrm{uw}}\cdot {\mathrm{u}}_{\mathrm{uw}}+{\mathrm{vs}}_{\mathrm{u}}\cdot {\mathrm{u}}_{\mathrm{uu}}\end{array}$$

Which then gives: $$\{\begin{array}{l}{{\mathrm{u}}^{*}}_{\mathrm{ab}}=\left({\mathrm{b}}_{\mathrm{uv}}-{\mathrm{b}}_{\mathrm{vw}}\right)\cdot {\mathrm{u}}_{\mathrm{uv}}+\left({\mathrm{b}}_{\mathrm{uw}}+{\mathrm{b}}_{\mathrm{vw}}\right)\cdot {\mathrm{u}}_{\mathrm{uw}}+{\mathrm{b}}_{\mathrm{u}}\cdot {\mathrm{u}}_{\mathrm{uu}}\\ {{\mathrm{u}}^{*}}_{\mathrm{ac}}=\left({\mathrm{vs}}_{\mathrm{uv}}-{\mathrm{vs}}_{\mathrm{vw}}\right)\cdot {\mathrm{u}}_{\mathrm{uv}}+\left({\mathrm{vs}}_{\mathrm{uw}}+{\mathrm{vs}}_{\mathrm{vw}}\right)\cdot {\mathrm{u}}_{\mathrm{uw}}+{\mathrm{vs}}_{\mathrm{u}}\cdot {\mathrm{u}}_{\mathrm{uu}}\end{array}$$

Gold $$\{\begin{array}{l}{\mathrm{b}}_{\mathrm{v}}=\left({\mathrm{b}}_{\mathrm{uv}}-{\mathrm{b}}_{\mathrm{vw}}\right)\\ {\mathrm{b}}_{\mathrm{w}}=\left({\mathrm{b}}_{\mathrm{uw}}+{\mathrm{b}}_{\mathrm{vw}}\right)\\ {\mathrm{vs}}_{\mathrm{v}}=\left({\mathrm{vs}}_{\mathrm{uv}}-{\mathrm{vs}}_{\mathrm{vw}}\right)\\ {\mathrm{vs}}_{\mathrm{w}}=\left({\mathrm{vs}}_{\mathrm{uw}}+{\mathrm{vs}}_{\mathrm{vw}}\right)\end{array}$$

We then obtain the following final relations: $$\{\begin{array}{c}{{\mathrm{u}}^{*}}_{\mathrm{ab}}={\mathrm{b}}_{\mathrm{v}}\cdot {\mathrm{u}}_{\mathrm{uv}}+{\mathrm{b}}_{\mathrm{w}}\cdot {\mathrm{u}}_{\mathrm{uw}}+{\mathrm{b}}_{\mathrm{u}}+{\mathrm{u}}_{\mathrm{uu}}\\ {{\mathrm{u}}^{*}}_{\mathrm{ac}}={\mathrm{vs}}_{\mathrm{v}}\cdot {\mathrm{u}}_{\mathrm{uv}}+{\mathrm{vs}}_{\mathrm{w}}\cdot {\mathrm{u}}_{\mathrm{uw}}+{\mathrm{vs}}_{\mathrm{u}}+{\mathrm{u}}_{\mathrm{uu}}\end{array}$$

And we then deduce the following cyclic ratio matrix: $$\mathrm{M}=\left\{\begin{array}{ccc}{\mathrm{at}}_{\mathrm{u}}=\mathrm{1}& {\mathrm{b}}_{\mathrm{u}}=\mathrm{1}-{\mathrm{b}}_{\mathrm{v}}-{\mathrm{b}}_{\mathrm{w}}\hfill & {\mathrm{vs}}_{\mathrm{u}}=\mathrm{1}-{\mathrm{vs}}_{\mathrm{v}}-{\mathrm{vs}}_{\mathrm{w}}\hfill \\ {\mathrm{at}}_{\mathrm{v}}=\mathrm{0}& {\mathrm{b}}_{\mathrm{v}}=\frac{\left({\mathrm{u}}_{\mathrm{uv}}-{\mathrm{u}}_{\mathrm{vw}}\right)\cdot {{\mathrm{u}}^{*}}_{\mathrm{<figure-callout\; id="2"\; label="ab\; u"\; filenames="imgf0002.png"\; state="\{\{state\}\}">ab\; </figure-callout>}}}{{{\mathrm{u}}^{}}_{}}\hfill & {\mathrm{vs}}_{\mathrm{v}}=\frac{\left({\mathrm{u}}_{\mathrm{uv}}-{\mathrm{u}}_{\mathrm{vw}}\right)\cdot {{\mathrm{u}}^{*}}_{\mathrm{<figure-callout\; id="2"\; label="ac\; u"\; filenames="imgf0002.png"\; state="\{\{state\}\}">ac\; </figure-callout>}}}{{{\mathrm{u}}^{}}_{}}\hfill \\ {\mathrm{at}}_{\mathrm{w}}=\mathrm{0}& {\mathrm{b}}_{\mathrm{w}}=\frac{\left({\mathrm{u}}_{\mathrm{uw}}+{\mathrm{u}}_{\mathrm{vw}}\right)\cdot {{\mathrm{u}}^{*}}_{\mathrm{<figure-callout\; id="2"\; label="ab\; u"\; filenames="imgf0002.png"\; state="\{\{state\}\}">ab\; </figure-callout>}}}{{{\mathrm{u}}^{}}_{}}\hfill & {\mathrm{vs}}_{\mathrm{w}}=\frac{\left({\mathrm{u}}_{\mathrm{uw}}+{\mathrm{u}}_{\mathrm{vw}}\right)\cdot {{\mathrm{u}}^{*}}_{\mathrm{<figure-callout\; id="2"\; label="ac\; u"\; filenames="imgf0002.png"\; state="\{\{state\}\}">ac\; </figure-callout>}}}{{{\mathrm{u}}^{}}_{}}\hfill \end{array}\right\}$$

With conditions: $$\{\begin{array}{c}{\mathrm{b}}_{\mathrm{u}}+{\mathrm{b}}_{\mathrm{v}}+{\mathrm{b}}_{\mathrm{w}}=\mathrm{1}\\ {\mathrm{vs}}_{\mathrm{u}}+{\mathrm{vs}}_{\mathrm{v}}+{\mathrm{vs}}_{\mathrm{w}}=\mathrm{1}\end{array}\mathrm{and}\{\begin{array}{c}0\le {\mathrm{b}}_{\mathrm{u}}\le 1\\ 0\le {\mathrm{b}}_{\mathrm{v}}\le 1\\ 0\le {\mathrm{b}}_{\mathrm{w}}\le 1\\ 0\le {\mathrm{vs}}_{\mathrm{u}}\le 1\\ 0\le {\mathrm{vs}}_{\mathrm{v}}\le 1\\ 0\le {\mathrm{vs}}_{\mathrm{w}}\le 1\end{array}$$

Starting from matrix M above, it is understood that these conditions are satisfied if: $$\{\begin{array}{c}{\mathrm{u}}_{\mathrm{uv}}-{\mathrm{u}}_{\mathrm{vw}}>\mathrm{0}\\ {\mathrm{u}}_{\mathrm{uw}}+{\mathrm{u}}_{\mathrm{vw}}>\mathrm{0}\end{array}$$

Since u _uv + u _vw + u _wu = 0, we obtain the following two conditions: $$\{\begin{array}{c}\mathrm{2}\cdot {\mathrm{u}}_{\mathrm{uv}}-{\mathrm{u}}_{\mathrm{uw}}>\mathrm{0}\\ \mathrm{2}\cdot {\mathrm{u}}_{\mathrm{uw}}-{\mathrm{u}}_{\mathrm{uv}}>\mathrm{0}\end{array}$$

These two conditions are fulfilled when u _uv and u _uw are the two largest voltages composed in absolute value. However, as network voltages evolve, this is not always the case. Therefore, the matrix M of cyclic ratios expressed above can not be used continuously to control the switches.

With reference to the figure 2 , the control method of the invention consists in continuously reducing to the particular case of the matrix M. For this, the control method of the invention uses a virtual control matrix Mv to which the control method allows to bring back continuously to determine the actual matrix of cyclic ratios. The virtual matrix Mv is of the same dimension as the matrix M and takes up the relations determined for the matrix M. The control method of the invention uses an input selector (Sel IN) and an output selector (Sel OUT) allowing to reduce itself permanently to the particular case of the matrix Mv. The selector input (Sel IN) and output selector (Sel OUT) perform the permutations on the input and output voltages before each duty cycle calculation, the calculation of the duty cycle being performed at each switching period. Once the cyclic ratios have been calculated, we return to the initial base by swapping the rows and columns of the virtual matrix Mv of calculated cyclic ratios. The method employed therefore amounts to controlling a virtual converter 20 ( figure 2 ) and to perform a permutation of the matrix cyclic reports calculated to obtain the control orders of the actual converter. With reference to the figure 2 the virtual converter 20 comprises virtual control switches designated f'a'u ', f'a'v', f'a'w ', f'b'u', f'b'v ', f'b 'w', f'c'u ', f'c'v', f'c'w 'distributed in three switching cells A', B ', C', each corresponding to a real control switch designated above above and intended to associate the inputs u ', v', w 'of the virtual converter to the outputs a', b ', c' of the virtual converter.

The simple voltages of the input phases u, v, w are assigned to virtual single voltages of the inputs u ', v', w 'of the virtual converter thanks to the input selector (Sel IN) and the simple voltages of the phases of output a, b, c are assigned to virtual voltages virtual outputs of the outputs a ', b', c 'of the virtual converter through the selector output (Sel OUT). In this way, it is always possible to reduce to the particular case defined above.

The assignment of the simple voltages of the input phases u, v, w to the simple voltages of the inputs u ', v', w 'of the virtual converter first consists of calculating the input voltage vector v _input from the following relation: $${\mathrm{v}}_{\mathrm{Entrance}}=\sqrt{\frac{\mathrm{2}}{\mathrm{3}}}\left({\mathrm{u}}_{\mathrm{uv}}+\mathrm{at}\cdot {\mathrm{at}}_{\mathrm{vw}}+{\mathrm{at}}^{\mathrm{2}}+{\mathrm{u}}_{\mathrm{wu}}\right)\mathrm{with\; a}={\mathrm{e}}^{\mathrm{j}\frac{\mathrm{2}\mathrm{<figure-callout\; id="3"\; label="\pi "\; filenames="imgf0002.png,imgf0004.png"\; state="\{\{state\}\}">\pi </figure-callout>}}{\mathrm{3}}}$$

With reference to the figure 3 , the assignment of the single voltages of the input phases u, v, w is then performed as a function of the sector (1, 2, 3, 4, 5, 6 on the figure 3 where is the input voltage vector v _input calculated. The simple voltage v _a , v _vn , v _wn common to the two largest voltages composed of the sector where the vector input voltage is located is connected to the virtual simple voltage of the input u '. The other two voltages of the input phases are arbitrarily assigned to the last two single voltages of the inputs v ', w' of the virtual converter. From the diagram of the figure 3 , we then obtain the following allocation table according to the sectors:

The signs (+) and (-) correspond to the sign of the vector voltage v _input with respect to the single input voltages v _a , v _vn , v _wn represented on the diagram of the figure 3 .

With regard to the output selector (Sel OUT), the assignment of the simple voltages of the output phases a, b, c to the simple voltages of the outputs a ', b', c 'of the virtual converter first requires calculate the reference output voltage vector from the following relation: $${\mathrm{v}}_{\mathrm{exit}}=\sqrt{\frac{\mathrm{2}}{\mathrm{3}}}\left({\mathrm{v}}_{\mathrm{year}}+\mathrm{at}\cdot {\mathrm{v}}_{\mathrm{bn\text{'}}}+{\mathrm{at}}^{\mathrm{2}}+{\mathrm{v}}_{\mathrm{cn\text{'}}}\right)\mathrm{with\; a}={\mathrm{e}}^{\mathrm{j}\frac{\mathrm{2}\mathrm{<figure-callout\; id="3"\; label="\pi "\; filenames="imgf0002.png,imgf0004.png"\; state="\{\{state\}\}">\pi </figure-callout>}}{\mathrm{3}}}$$

v _{an '} , v _bn' , v _{cn '} are represented on the figure 1 and correspond to the reference output voltages. They therefore come from the control and their value is the image of the output voltage since they represent the desired voltages for the next sampling instant. According to the position of the reference output voltage vector v _output relative to each of the sectors defined on the figure 4 we then obtain the following table in which we know which of the simple voltages of the output phases a, b, c is the largest Vsup, the smallest Vinf and the intermediate voltage Vmid in absolute value:

• être de même signe que la tension simple de la phase d'entrée reliée à la tension simple virtuelle de l'entrée u',
• être la tension la plus élevée ou la plus faible des trois tensions de sortie dans le secteur considéré mais pas la valeur intermédiaire en valeur absolue parmi ces trois tensions de sortie.

For the output selector (Sel OUT), the simple voltage of the output phase to be applied to the simple voltage of output a 'of the virtual converter must:

• be of the same sign as the simple voltage of the input phase connected to the virtual simple voltage of the input u ',
• be the highest or lowest voltage of the three output voltages in the sector considered but not the intermediate value in absolute value among these three output voltages.

• ne pourra pas être le potentiel intermédiaire dans le secteur du vecteur tension de sortie
• sera celle dont le potentiel Vsup ou Vinf dans le secteur considéré est de même signe que la tension simple de la phase d'entrée u, v ou w qui est reliée à la tension simple virtuelle de l'entrée u'.

Accordingly, from the table above, the simple voltage of the output phase a, b, or c to be applied to the simple voltage of the input a 'of the virtual converter 20:

• can not be the intermediate potential in the sector of the vector output voltage
• will be the one whose potential Vsup or Vinf in the considered sector is of the same sign as the simple voltage of the input phase u, v or w which is connected to the virtual simple voltage of the input u '.

The following table summarizes the different rules for assigning input phase voltages and output phase voltages: Sector u ' at' b ' vs' u '(+) Sup (u, v, w) Sup (a, b, c) Mid (a, b, c) Min (a, b, c) u '(-) Min (u, v, w) Min (a, b, c) Sup (a, b, c) Mid (a, b, c)

Taking into account the relationships defined for the matrix M calculated above, the virtual matrix Mv applied in the virtual converter is thus the following: $$\mathrm{mv}=\left\{\begin{array}{ccc}{\mathrm{at}}_{\mathrm{u\text{'}}}=\mathrm{1}& {\mathrm{b\; \text{'}}}_{\mathrm{u\text{'}}}=\mathrm{1}-{\mathrm{b\; \text{'}}}_{\mathrm{V\text{'}}}-{\mathrm{b\; \text{'}}}_{\mathrm{W\text{'}}}\hfill & {\mathrm{vs}}_{\mathrm{u\text{'}}}=\mathrm{1}-{\mathrm{vs}}_{\mathrm{V\text{'}}}-{\mathrm{vs}}_{\mathrm{W\text{'}}}\hfill \\ {\mathrm{at}}_{\mathrm{V\text{'}}}=\mathrm{0}& {\mathrm{b\; \text{'}}}_{\mathrm{V\text{'}}}=\frac{\left({\mathrm{u}}_{\mathrm{u\text{'}v\text{'}}}-{\mathrm{u}}_{\mathrm{v\text{'}w\text{'}}}\right)\cdot {\mathrm{u}}_{\mathrm{s}\mathrm{1}}}{{{\mathrm{<figure-callout\; id="2"\; label="u"\; filenames="imgf0002.png"\; state="\{\{state\}\}">u</figure-callout>}}^{\mathrm{2}}}_{\mathrm{u\text{'}v\text{'}}}+{{\mathrm{<figure-callout\; id="2"\; label="u"\; filenames="imgf0002.png"\; state="\{\{state\}\}">u</figure-callout>}}^{\mathrm{2}}}_{\mathrm{v\text{'}w\text{'}}}+{{\mathrm{<figure-callout\; id="2"\; label="u"\; filenames="imgf0002.png"\; state="\{\{state\}\}">u</figure-callout>}}^{\mathrm{2}}}_{\mathrm{u\text{'}w\text{'}}}}\hfill & {\mathrm{vs}}_{\mathrm{V\text{'}}}=\frac{\left({\mathrm{u}}_{\mathrm{u\text{'}v\text{'}}}-{\mathrm{u}}_{\mathrm{v\text{'}w\text{'}}}\right)\cdot {\mathrm{u}}_{\mathrm{s}\mathrm{2}}}{{{\mathrm{<figure-callout\; id="2"\; label="u"\; filenames="imgf0002.png"\; state="\{\{state\}\}">u</figure-callout>}}^{\mathrm{2}}}_{\mathrm{u\text{'}v\text{'}}}+{{\mathrm{<figure-callout\; id="2"\; label="u"\; filenames="imgf0002.png"\; state="\{\{state\}\}">u</figure-callout>}}^{\mathrm{2}}}_{\mathrm{v\text{'}w\text{'}}}+{{\mathrm{<figure-callout\; id="2"\; label="u"\; filenames="imgf0002.png"\; state="\{\{state\}\}">u</figure-callout>}}^{\mathrm{2}}}_{\mathrm{u\text{'}w\text{'}}}}\hfill \\ {\mathrm{at}}_{\mathrm{W\text{'}}}=\mathrm{0}& {\mathrm{b\; \text{'}}}_{\mathrm{W\text{'}}}=\frac{\left({\mathrm{u}}_{\mathrm{u\text{'}w\text{'}}}+{\mathrm{u}}_{\mathrm{v\text{'}w\text{'}}}\right)\cdot {\mathrm{u}}_{\mathrm{s}\mathrm{1}}}{{{\mathrm{<figure-callout\; id="2"\; label="u"\; filenames="imgf0002.png"\; state="\{\{state\}\}">u</figure-callout>}}^{\mathrm{2}}}_{\mathrm{u\text{'}v\text{'}}}+{{\mathrm{<figure-callout\; id="2"\; label="u"\; filenames="imgf0002.png"\; state="\{\{state\}\}">u</figure-callout>}}^{\mathrm{2}}}_{\mathrm{v\text{'}w\text{'}}}+{{\mathrm{<figure-callout\; id="2"\; label="u"\; filenames="imgf0002.png"\; state="\{\{state\}\}">u</figure-callout>}}^{\mathrm{2}}}_{\mathrm{u\text{'}w\text{'}}}}\hfill & {\mathrm{vs}}_{\mathrm{W\text{'}}}=\frac{\left({\mathrm{u}}_{\mathrm{u\text{'}w\text{'}}}+{\mathrm{u}}_{\mathrm{v\text{'}w\text{'}}}\right)\cdot {\mathrm{u}}_{\mathrm{s}\mathrm{2}}}{{{\mathrm{<figure-callout\; id="2"\; label="u"\; filenames="imgf0002.png"\; state="\{\{state\}\}">u</figure-callout>}}^{\mathrm{2}}}_{\mathrm{u\text{'}v\text{'}}}+{{\mathrm{<figure-callout\; id="2"\; label="u"\; filenames="imgf0002.png"\; state="\{\{state\}\}">u</figure-callout>}}^{\mathrm{2}}}_{\mathrm{v\text{'}w\text{'}}}+{{\mathrm{<figure-callout\; id="2"\; label="u"\; filenames="imgf0002.png"\; state="\{\{state\}\}">u</figure-callout>}}^{\mathrm{2}}}_{\mathrm{u\text{'}w\text{'}}}}\hfill \end{array}\right\}$$

• u_s1 = V_sup - V_mid = u_a'b'
• u_s2 = V_sup V_inf = u_a'c'

If the virtual simple voltage of the input u 'is positive, we have:

• u _s1 = V _sup - V _mid = u _{a'b '}
• u _s2 = V _sup V _inf = u _{a'c '}

• u_s1 = V_sup - V_inf = u_a'c'
• u_s2 = V_mid - V_inf = u_a'b'

If the virtual simple voltage of the input u 'is negative, we have:

• u _s1 = V _sup - V _inf = u _{a'c '}
• u _s2 = V _mid - V _inf = u _{a'b '}

• La matrice virtuelle obtenue après calcul des rapports cycliques à partir des relations définies précédemment est par exemple la suivante : $$\mathrm{Mv}=\left\{\begin{array}{ccc}1& 0.135& 0.215\\ 0& 0.65& 0.59\\ 0& 0.215& 0.195\end{array}\right\}$$
  
  
  On remarque notamment que la somme des rapports cycliques pour chaque colonne est égale à 1. De plus la première cellule de commutation est bloquée car le rapport cyclique de l'interrupteur f'a'u' est égal à 1.
• Ensuite, selon l'affectation des tensions des phases de sortie a, b, c aux tensions des sorties a', b', c' du convertisseur virtuel 20, le procédé consiste à effectuer les permutations des colonnes de la matrice Mv précédente. On obtient alors par exemple la matrice M1 suivante : $$\mathrm{M}\mathrm{1}=\left\{\begin{array}{ccc}\mathrm{0.135}& \mathrm{1}& \mathrm{0.215}\\ \mathrm{0.65}& \mathrm{0}& \mathrm{0.59}\\ \mathrm{0.215}& \mathrm{0}& \mathrm{0.195}\end{array}\right\}$$
  
  
  Dans cette matrice M1 les deux premières colonnes ont été permutées par rapport à la matrice virtuelle Mv initiale car :
  • la tension simple de la phase de sortie a est reliée à la tension virtuelle de la sortie b',
  • la tension simple de la phase de sortie b est reliée à la tension virtuelle de la sortie a',
  • la tension simple de la phase de sortie c est reliée à la tension virtuelle de la sortie c'.
• Selon l'affectation des tensions des phases d'entrée u, v, w aux tensions virtuelles des entrées u', v', w' du convertisseur virtuel, le procédé consiste ensuite à permuter les lignes de la matrice M1 précédente pour obtenir la matrice M2 suivante : $$\mathrm{M}2=\left\{\begin{array}{ccc}\mathrm{0.65}& 0& \mathrm{0.59}\\ \mathrm{0.135}& \mathrm{1}& \mathrm{0.215}\\ \mathrm{0.215}& \mathrm{0}& \mathrm{0.195}\end{array}\right\}$$
  
  
  Cette matrice M2 est obtenue en permutant les deux premières lignes de la matrice M1 car:
  • la tension simple de la phase d'entrée u est reliée à la tension virtuelle de l'entrée v',
  • la tension simple de la phase d'entrée v est reliée à la tension virtuelle de l'entrée u',
  • la tension simple de la phase d'entrée w est reliée à la tension virtuelle de l'entrée w'.

After calculating the cyclic ratios in the virtual matrix Mv defined above, the control method of the invention consists in performing if necessary the permutations of the rows and columns of the virtual matrix Mv to obtain the real matrix, taking into account the assigning the voltages of the input phases u, v, w and the output phases a, b, c of the actual converter respectively to the voltages of the inputs u ', v', w 'and outputs a', b ', c' of the virtual converter. Here is an example to illustrate the different steps to move from the virtual matrix to the real matrix. The cyclic ratios presented in the matrix Mv are of course only examples and should not be interpreted in a limiting way.

• The virtual matrix obtained after calculation of the cyclic ratios from the relationships defined above is for example the following: $$\mathrm{mv}=\left\{\begin{array}{ccc}1& 0135& 0215\\ 0& 0.65& 0.59\\ 0& 0215& 0195\end{array}\right\}$$
  
  
  Note in particular that the sum of the cyclic ratios for each column is equal to 1. In addition, the first switching cell is blocked because the duty cycle of the switch f'a'u 'is equal to 1.
• Next, according to the assignment of the voltages of the output phases a, b, c to the voltages of the outputs a ', b', c 'of the virtual converter 20, the method consists in performing the permutations of the columns of the preceding matrix Mv. For example, the following matrix M1 is obtained: $$\mathrm{M}\mathrm{1}=\left\{\begin{array}{ccc}\mathrm{0135}& \mathrm{1}& \mathrm{0215}\\ \mathrm{0.65}& \mathrm{0}& \mathrm{0.59}\\ \mathrm{0215}& \mathrm{0}& \mathrm{0195}\end{array}\right\}$$
  
  
  In this matrix M1, the first two columns have been permuted with respect to the initial virtual matrix Mv because:
  • the simple voltage of the output phase a is connected to the virtual voltage of the output b ',
  • the simple voltage of the output phase b is connected to the virtual voltage of the output a ',
  • the simple voltage of the output phase c is connected to the virtual voltage of the output c '.
• According to the assignment of the voltages of the input phases u, v, w to the virtual voltages of the inputs u ', v', w 'of the virtual converter, the method then consists in permuting the lines of the matrix M1 above to obtain the matrix Next M2: $$\mathrm{M}2=\left\{\begin{array}{ccc}\mathrm{0.65}& 0& \mathrm{0.59}\\ \mathrm{0135}& \mathrm{1}& \mathrm{0215}\\ \mathrm{0215}& \mathrm{0}& \mathrm{0195}\end{array}\right\}$$
  
  
  This matrix M2 is obtained by permuting the first two rows of the matrix M1 because:
  • the simple voltage of the input phase u is connected to the virtual voltage of the input v ',
  • the simple voltage of the input phase v is connected to the virtual voltage of the input u ',
  • the simple voltage of the input phase w is connected to the virtual voltage of the input w '.

The two steps of permutation can of course be performed in the reverse order.

The matrix M2 thus obtained is the real matrix of cyclic ratios to be applied to the nine switches of the commutation matrix of the real converter. The two permutations carried out in particular displaced the position of the null phase, the latter being identified by the line of the matrix M2 which has no zero value. The null phase is therefore on the input phase v because the second line of the matrix M2 is non-zero.

Blocking a switching cell of the converter over a switching period by introducing a zero phase makes it possible to reduce by one third the number of switching operations and thus to reduce both the switching losses and the common mode voltages. However, the blocking of a cell during the switching period does not make it possible to reach the optimum in terms of reduction of switching losses and common mode voltages since the blocked cell does not make it possible to systematically impose the total sum the lowest absolute value of the input voltages to the other two cells that switch. Optimum performance is therefore achieved when the total voltage cut in absolute value over the cutting period by the three cells is the lowest possible.

For this, the control method of the invention also consists in modifying the position of the zero phase in the cyclic ratio matrix obtained. This particularity of the control method of the invention should not be understood as applying only to the cyclic ratio matrix obtained by means of the method previously described using the virtual matrix Mv. It should be understood that this new feature of the method of the invention which consists in moving the null phase can be applied to a cyclic ratio matrix comprising a zero phase, whatever the method by which this matrix has been obtained.

• les trois interrupteurs du haut fau, fbu, fcu sont commandés à l'état fermé (111),
• les trois interrupteurs du milieu fav, fbv, fcv sont commandés à l'état fermé (222),
• les trois interrupteurs du bas faw, fbw, fcw sont commandés à l'état fermé (333).

In a matrix converter, three types of null phase are possible:

• the three switches of the top fau, fbu, fcu are controlled in the closed state (111),
• the three switches of the medium fav, fbv, fcv are controlled in the closed state (222),
• the three bottom switches faw, fbw, fcw are controlled in the closed state (333).

• supprimer dans la matrice de rapports cycliques la phase nulle et,
• choisir et placer dans la matrice de rapports cycliques une nouvelle phase nulle parmi les trois possibles définies ci-dessus afin de résoudre le problème précité.

As far as necessary, the control method of the invention for reducing switching losses and common mode currents comprises:

• delete in the cyclic ratio matrix the null phase and,
• select and place in the cyclic ratio matrix a new zero phase among the three possible ones defined above in order to solve the aforementioned problem.

First of all, it is nevertheless necessary to justify that a change of position of the null phase actually makes it possible to reduce the total voltage switched in absolute value. For this, for each zero phase defined above, it is possible to start from a standard sequence of four active states without a null phase, to integrate a passage through the zero phase considered and to see which sequence makes it possible to switch the lowest voltage. The transition from one active state to another must not cause the switching of two switches at the same time, that is to say do not cause the modification of two digits at the same time.

• 322
• 323
• 313
• 311

For example, from a sequence with the following four active states:

• 322
• 323
• 313
• 311

The three possible null phases are positioned within these four active states so as to obtain the following table: Sequence A Sequence B Sequence C 322 222 322 323 322 323 333 323 313 313 313 311 311 311 111

• le passage de l'état actif 322 à 323 revient à passer de la tension de la phase d'entrée v à la tension de la phase d'entrée w, donc à commuter ΔVmin,
• le passage de l'état actif 323 à 333 revient à passer de la tension de la phase d'entrée v à la tension de la phase d'entrée w, donc à commuter ΔVmin,
• le passage de l'état actif 333 à 313 revient à passer de la tension de la phase d'entrée w à la tension de la phase d'entrée u, donc à commuter ΔVmax,
• le passage de l'état actif 313 à 311 revient à passer de la tension de la phase d'entrée w à la tension de la phase d'entrée u, donc à commuter ΔVmax,

From the Figure 5A indicating the deviations (ΔVmax, ΔVmin, ΔVmid) between the simple voltages v _a , v _vn , v _wn of the input phases u, v, w, we note that for the sequence A:

• the transition from the active state 322 to 323 amounts to switching from the voltage of the input phase v to the voltage of the input phase w, thus to switching ΔVmin,
• the transition from the active state 323 to 333 amounts to going from the voltage of the input phase v to the voltage of the input phase w, thus to switching ΔVmin,
• the transition from the active state 333 to 313 amounts to going from the voltage of the input phase w to the voltage of the input phase u, thus to switching ΔVmax,
• the transition from the active state 313 to 311 amounts to going from the voltage of the input phase w to the voltage of the input phase u, thus to switching ΔVmax,

For the sequence A, the total switched voltage is Utot = 2 ΔVmax + 2 ΔVmin.

• Séquence B Utot=2 Δvmax+Δvmin
• Séquence C Utot=3 ΔVmax

By doing the same reasoning for the B and C sequences defined in the table above, we obtain:

• Sequence B Utot = 2 Δvmax + Δvmin
• Sequence C Utot = 3 ΔVmax

• Séquence A Utot=2 ΔVmax+2 ΔVmid
• Séquence B Utot=2 ΔVmax+ΔVmid
• Séquence C Utot=3 ΔVmax

Similarly, from the Figure 5B by modifying the sign of the switched voltage, we obtain:

• Sequence A Utot = 2 ΔVmax + 2 ΔVmid
• Sequence B Utot = 2 ΔVmax + ΔVmid
• Sequence C Utot = 3 ΔVmax

Therefore, if initially the null phase was on the three switches of the bottom, the replacement of this zero phase on the switches of the medium would reduce the total voltage switched and thus reduce the switching losses and common mode voltages.

To correctly position the null phase in the control matrix, it is necessary to determine the vector input voltage v _input and position it with respect to the different simple voltages v _a , v _vn , v _wn of the input phases u, v, w as represented on the figure 6 . As a reminder, we have: $${\mathrm{v}}_{\mathrm{Entrance}}=\sqrt{\frac{\mathrm{2}}{\mathrm{3}}}\left({\mathrm{u}}_{\mathrm{uv}}+\mathrm{at}\cdot {\mathrm{at}}_{\mathrm{vw}}+{\mathrm{at}}^{\mathrm{2}}\cdot {\mathrm{u}}_{\mathrm{wu}}\right)\mathrm{with\; a}={\mathrm{e}}^{\mathrm{j}\frac{\mathrm{2}\mathrm{<figure-callout\; id="3"\; label="\pi "\; filenames="imgf0002.png,imgf0004.png"\; state="\{\{state\}\}">\pi </figure-callout>}}{\mathrm{3}}}$$

On the figure 6 the sector (111, 222, 333) in which the input voltage v _input vector is located corresponds to the optimal location for the null phase (for example 333 on the figure 6 ). Starting from the previous example which made it possible to obtain the matrix M2 defined above, the method therefore consists, if necessary, in eliminating the null phase and replacing the null phase in order to minimize the switching losses and the mode voltages. common.

The matrix M2 obtained was as follows: $$\mathrm{M}2=\left\{\begin{array}{ccc}\mathrm{0.65}& 0& \mathrm{0.59}\\ 0135& 1& \mathrm{0215}\\ \mathrm{0215}& 0& \mathrm{0195}\end{array}\right\}$$

$$\mathrm{M}3=\left\{\begin{array}{ccc}\mathrm{0.65}& 0& \mathrm{0.59}\\ \mathrm{0}& \mathrm{0.865}& \mathrm{0.08}\\ \mathrm{0.215}& 0& \mathrm{0.195}\end{array}\right\}$$

The null phase is represented by the second line of the matrix M2. Considering, for example, that the input voltage vector determined by the formula above is in the sector for which the null phase should be on the third line of the matrix M2 ( figure 6 ), it is necessary to modify the placement of the null phase. For this purpose, the control method of the invention consists in selecting the smallest cyclic ratio of the line (0.135 on the second line of the matrix M2) comprising the null phase and subtracting it from all the cyclic ratios of this same line. We then obtain: $$\mathrm{M}3=\left\{\begin{array}{ccc}\mathrm{0.65}& 0& \mathrm{0.59}\\ \mathrm{0135}-0135& \mathrm{1}-\mathrm{0135}& 0215-0135\\ \mathrm{0215}& \mathrm{0}& \mathrm{0195}\end{array}\right\}$$

$$\mathrm{M}3=\left\{\begin{array}{ccc}\mathrm{0.65}& 0& \mathrm{0.59}\\ \mathrm{0}& \mathrm{0865}& \mathrm{0.08}\\ \mathrm{0215}& 0& \mathrm{0195}\end{array}\right\}$$

In the matrix M3 thus obtained, the null phase is therefore eliminated since all the lines comprise at least one duty cycle equal to zero.

$$\mathrm{M}4=\left\{\begin{array}{ccc}\mathrm{0.65}& 0& \mathrm{0.59}\\ \mathrm{0}& \mathrm{0.865}& \mathrm{0.08}\\ \mathrm{0.35}& \mathrm{0.135}& \mathrm{0.33}\end{array}\right\}$$

To place the null phase on the line becoming the new zero phase, that is to say the third line, the control method consists in adding the cyclic ratio previously subtracted to the cyclic ratios of this line. We then obtain: $$\mathrm{M}4=\left\{\begin{array}{ccc}\mathrm{0.65}& 0& \mathrm{0.59}\\ \mathrm{0}& \mathrm{0865}& \mathrm{0.08}\\ \mathrm{0215}& \mathrm{0}+\mathrm{0135}& \mathrm{0195}+\mathrm{0135}\end{array}\right\}$$

$$\mathrm{M}4=\left\{\begin{array}{ccc}\mathrm{0.65}& 0& \mathrm{0.59}\\ \mathrm{0}& \mathrm{0865}& \mathrm{0.08}\\ \mathrm{0.35}& \mathrm{0135}& \mathrm{0.33}\end{array}\right\}$$

The null phase is then well on the third line because it then has no cyclic ratio equal to zero. It will be noted in this case that the matrix M4 which gives the optimal result in terms of reduction of the losses by switching and reduction of the common mode voltage does not have a duty cycle equal to 1. The introduction of the new zero phase allows thus a division of the three input voltages which implies that none of the three cells remains in a blocked state on the cutting period. The introduction of the new zero phase also makes it possible to limit to eight the number of states active over a cutting period, like the initial null phase which made it possible to block a cell over a cutting period.

Once the definitive cyclic ratio matrix has been obtained, the control method consists of defining the control commands of the nine bidirectional switches of the switching matrix so as to perform the PWM type modulation. The variable speed drive uses an intersutive modulation for making comparisons between modulators represented by the cyclic ratios of the control matrix and one or more determined carriers. According to the invention, the variable speed drive uses, for example, two distinct inverse triangular x, y carriers ( figure 7 ), of frequency equal to the switching frequency.

These two carriers x, y are used to define the cyclic ratios of the three cells A, B, C of the matrix converter. For each switching cell A, B, C, the two carriers x, y define the control commands of two of the three switches of the cell. The command order of the third switch is automatically defined by the complement of the other two since the sum of the duty cycles of a switching cell is always equal to one.

• les modulantes d'une ligne de la matrice de rapports cycliques s'appliquent toujours à la même porteuse,
• la ligne de la matrice de rapports cycliques comportant le rapport cyclique le plus grand est exclue,
• les deux lignes non exclues sont comparées chacune à l'une des porteuses x, y.

According to the invention, it is therefore a question of selecting the cyclic ratios of the control matrix to be applied to the two x, y carriers of the PWM-type modulator. This selection is made as follows:

• the modulants of a row of the cyclic ratio matrix always apply to the same carrier,
• the row of the cyclic ratio matrix with the largest duty cycle is excluded,
• the two non-excluded lines are each compared to one of the carriers x, y.

The choice of the carrier to be applied to one or the other non-excluded cyclic report lines makes it possible to modify the sequence of the active phases and zero over a half-period of division.

Depending on the choice of the carrier, the null phase of the control matrix may be at the beginning or at the end of the half-period of cutting.

Moreover, to preserve the advantages of the placement of the new null phase, the implementations of the zero phase cyclic ratios should not generate double or triple switching, that is to say switching of two or three arms at the same time. time. In order to eliminate any possibility of double or triple switching, it is necessary for the modulator to respect the following rule according to which if one of the two non-excluded cyclic report lines carries the null phase then this line must be considered as the master line. The master line will be compared alternately with the first carrier x and then with the second carrier y at each sector change of the vector of the input voltage v _input . The choice of the initial carrier x or y used for the comparison is arbitrary and fixed for example as on the figure 8 . The other non-excluded line is compared to the carrier not used by the master line.

On the other hand, if none of the two non-excluded lines carries the null phase, then the master line is the one which comprises the weakest non-zero duty cycle, and the slave line is the other non-excluded line. As before, the master line will be compared with each of the carriers x, y successively, the choice of the initial carrier being also arbitrary.

Starting from the example of the matrix M4 obtained previously: $$\mathrm{M}4=\left\{\begin{array}{ccc}\mathrm{0.65}& 0& \mathrm{0.59}\\ \mathrm{0}& \mathrm{0865}& \mathrm{0.08}\\ \mathrm{0.35}& \mathrm{0135}& \mathrm{0.33}\end{array}\right\}$$

Note that the middle line is the excluded line because it has the largest duty cycle. Among the non-excluded lines, the third line is the one containing the null phase. Therefore the third line is the master line and the first line is the slave line. During the first switching period P, the master line is therefore compared to one of the two carriers, for example arbitrarily the first carrier x, while the slave line is compared with the other carrier, that is to say say the second carrier y.

On the figure 9 are represented modulants m1, m2, m3, m10, m20, m30 which are for example applied to the two carriers x, y in order to deduce the control commands of the switches in time over a switching period. The modulators m1, m2, m3 applied to the first carrier x represent the cyclic ratios of the line of the cyclic ratio matrix to be applied to said carrier x and the modulators m10, m20, m30 applied to the second carrier y represent the cyclic ratios. of the row of the cyclic ratio matrix to be applied to said carrier y. These modulators represented on the figure 9 are only examples and are not representative of the matrix M4 defined above.

Claims (12)

1. A control method implemented in a variable speed drive of matrix converter type comprising:

   - three input phases (u, v, w) connected to an AC voltage source and three output phases (a, b, c) connected to an electrical load,

   - nine current and voltage bidirectional electronic switches (fau, fav, faw, fbu, fbv, fbw, fcu, fcv, fcw) distributed among three switching cells (A, B, C) and intended to be controlled individually so as to connect an output phase to any one of the input phases, the switching of the switches of the converter obeying a matrix of duty cycles making it possible to obtain an output voltage destined for the load,

   - said matrix of duty cycles comprising a null phase,

   - characterized in that the method comprises:

   - a step of eliminating the null phase from the matrix of duty cycles,

   - a step of positioning a new null phase in the matrix of duty cycles so as to reduce to the maximum the switching losses and the common-mode voltages.
2. The method as claimed in claim 1, characterized in that the step of positioning the new null phase consists in determining the input voltage vector (V_input) and in determining the location of the new null phase as a function of the position of this vector with respect to the various input simple voltages (V_un, V_vn, V_wn).
3. The method as claimed in claim 1 or 2, characterized in that the control commands for the bidirectional electronic switches are determined by modulation of intersective type.
4. The method as claimed in claim 3, characterized in that the modulation of intersective type is implemented by applying duty cycles of the matrix of duty cycles in the form of modulants (m1-m3, m10-m30) on two distinct carriers (x, y).
5. The method as claimed in claim 4, characterized in that the two carriers (x, y) are of triangular shape, of frequency equal to the switching frequency, one of the carriers being the inverse of the other carrier.
6. The method as claimed in claim 4 or 5, characterized in that the modulants of a row of the matrix of duty cycles always apply to the same carrier (x, y).
7. The method as claimed in one of claims 4 to 6, characterized in that the row of the matrix of duty cycles comprising the highest duty cycle is not applied to either of the two carriers (x, y) and in that the two non-excluded rows are each compared with one of the carriers (x, y).
8. A variable speed drive of matrix converter type comprising:

   - three input phases (u, v, w) connected to an AC voltage source and three output phases (a, b, c) connected to an electrical load,

   - nine current and voltage bidirectional electronic switches (fau, fav, faw, fbu, fbv, fbw, fcu, fcv, fcw) distributed among three switching cells (A, B, C) and intended to be controlled individually so as to connect an output phase to any one of the input phases, the switching of the switches of the converter obeying a matrix of duty cycles making it possible to obtain an output voltage destined for the load,

   - said matrix of duty cycles comprising a null phase,

   - characterized in that the variable drive comprises:

   - means for eliminating the null phase from the matrix of duty cycles,

   - means for positioning a new null phase in the matrix of duty cycles so as to reduce to the maximum the switching losses and the common-mode voltages.
9. The variable speed drive as claimed in claim 8, characterized in that it comprises means for determining the input voltage vector (V_input) and for determining the location of the new null phase as a function of the position of this vector with respect to the various input simple voltages (V_un, V_vn, V_wn).
10. The variable speed drive as claimed in claim 8 or 9, characterized in that the control commands for the bidirectional electronic switches are determined by modulation of intersective type.
11. The variable speed drive as claimed in claim 10, characterized in that the modulation of intersective type is implemented by applying duty cycles of the matrix of duty cycles in the form of modulants (m1-m3, m10-m30) on two distinct carriers (x, y).
12. The variable speed drive as claimed in claim 11, characterized in that the two carriers (x, y) are of triangular shape, of frequency equal to the switching frequency, one of the carriers being the inverse of the other carrier.

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