EP2337067A3 - Making TSV interconnection structures composed of an insulating contour and a conducting area located in the contour and separate from the contour - Google Patents

Making TSV interconnection structures composed of an insulating contour and a conducting area located in the contour and separate from the contour Download PDF

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Publication number
EP2337067A3
EP2337067A3 EP10194655A EP10194655A EP2337067A3 EP 2337067 A3 EP2337067 A3 EP 2337067A3 EP 10194655 A EP10194655 A EP 10194655A EP 10194655 A EP10194655 A EP 10194655A EP 2337067 A3 EP2337067 A3 EP 2337067A3
Authority
EP
European Patent Office
Prior art keywords
contour
separate
insulating
area located
interconnection structures
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP10194655A
Other languages
German (de)
French (fr)
Other versions
EP2337067A2 (en
EP2337067B1 (en
Inventor
Gabriel Pares
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Original Assignee
Commissariat a lEnergie Atomique CEA
Commissariat a lEnergie Atomique et aux Energies Alternatives CEA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Publication date
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Publication of EP2337067A2 publication Critical patent/EP2337067A2/en
Publication of EP2337067A3 publication Critical patent/EP2337067A3/en
Application granted granted Critical
Publication of EP2337067B1 publication Critical patent/EP2337067B1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/02—Bonding areas; Manufacturing methods related thereto
    • H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
    • H01L2224/0554—External layer
    • H01L2224/0556—Disposition
    • H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/1302—Disposition
    • H01L2224/13025—Disposition the bump connector being disposed on a via connection of the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
    • H01L2224/141—Disposition
    • H01L2224/1418—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/14181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

L'invention concerne un procédé de réalisation d'une structure d'interconnexion comprenant : la formation dans un substrat (100) d'au moins une tranchée (103, 105) réalisant un contour fermé et d'au moins un trou (102, 104) situé à l'intérieur du dit contour fermé, la tranchée et le trou étant séparés par une zone du substrat, le procédé comprenant en outre des étapes de remplissage de la tranchée par un matériau diélectrique (111) et du trou par un matériau conducteur (117, 122).

Figure imgaf001
The invention relates to a method for producing an interconnection structure comprising: forming in a substrate (100) at least one trench (103, 105) forming a closed contour and at least one hole (102, 104) located within said closed contour, the trench and the hole being separated by an area of the substrate, the method further comprising steps of filling the trench with a dielectric material (111) and a hole with a material conductor (117, 122).
Figure imgaf001
EP10194655.6A 2009-12-15 2010-12-13 Making TSV interconnection structures composed of an insulating contour and a conducting area located in the contour and separate from the contour Active EP2337067B1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0958999A FR2953992B1 (en) 2009-12-15 2009-12-15 IMPLEMENTING TSV INTERCONNECTION STRUCTURES FORMED OF AN INSULATING CONTOUR AND A CONDUCTIVE ZONE LOCATED IN THE CONTOUR AND DISJOINTE OF THE CONTOUR

Publications (3)

Publication Number Publication Date
EP2337067A2 EP2337067A2 (en) 2011-06-22
EP2337067A3 true EP2337067A3 (en) 2012-04-04
EP2337067B1 EP2337067B1 (en) 2013-12-11

Family

ID=42333336

Family Applications (1)

Application Number Title Priority Date Filing Date
EP10194655.6A Active EP2337067B1 (en) 2009-12-15 2010-12-13 Making TSV interconnection structures composed of an insulating contour and a conducting area located in the contour and separate from the contour

Country Status (4)

Country Link
US (1) US8541304B2 (en)
EP (1) EP2337067B1 (en)
JP (1) JP5858612B2 (en)
FR (1) FR2953992B1 (en)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2597677B1 (en) * 2011-11-23 2014-08-06 ams AG Semiconductor device with through-substrate via covered by a solder ball and related method of production
KR101934864B1 (en) * 2012-05-30 2019-03-18 삼성전자주식회사 Through silicon via structure, methods of forming the same, image sensor including the through silicon via structure and methods of manufacturing the image sensor
DE102012219769B4 (en) 2012-10-29 2020-06-25 Robert Bosch Gmbh Method of making an electrical via in a substrate
JP2014093392A (en) * 2012-11-02 2014-05-19 Renesas Electronics Corp Semiconductor device and method of manufacturing the same
FR2998710B1 (en) * 2012-11-29 2016-02-05 Commissariat Energie Atomique IMPROVED METHOD OF MAKING A STRUCTURE FOR THE ASSEMBLY OF MICROELECTRONIC DEVICES
KR20140073163A (en) 2012-12-06 2014-06-16 삼성전자주식회사 Semiconductor device and method of forming the same
KR102151177B1 (en) 2013-07-25 2020-09-02 삼성전자 주식회사 Integrated circuit device having through silicon via structure and method of manufacturing the same
US9666521B2 (en) * 2013-08-08 2017-05-30 Invensas Corporation Ultra high performance interposer
US9476927B2 (en) 2014-01-22 2016-10-25 GlobalFoundries, Inc. Structure and method to determine through silicon via build integrity
JP6363868B2 (en) * 2014-05-12 2018-07-25 国立大学法人東北大学 Semiconductor device and manufacturing method thereof
JP6362254B2 (en) * 2014-05-12 2018-07-25 国立大学法人東北大学 Semiconductor device and manufacturing method thereof
JP6427043B2 (en) * 2015-03-10 2018-11-21 Ｓｐｐテクノロジーズ株式会社 Wiring board manufacturing method
CN110277348B (en) * 2019-06-05 2021-09-28 浙江芯动科技有限公司 Manufacturing process method of semiconductor TSV structure and semiconductor TSV structure
CN112928095B (en) * 2021-02-03 2022-03-15 长鑫存储技术有限公司 Interconnection structure, preparation method thereof and semiconductor structure

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US20070069364A1 (en) * 2005-09-29 2007-03-29 Nec Electronics Corporation Semiconductor device and method for manufacturing same
US20080079131A1 (en) * 2006-09-30 2008-04-03 Sung Min Kim Stack package and method for manufacturing the same
US20080124845A1 (en) * 2006-11-28 2008-05-29 Taiwan Semiconductor Manufacturing Co., Ltd. Stacked structures and methods of fabricating stacked structures
US20090057899A1 (en) * 2007-08-30 2009-03-05 Keon-Yong Cheon Semiconductor integrated circuit device and method of fabricating the same
WO2010125164A1 (en) * 2009-04-29 2010-11-04 International Business Machines Corporation Through substrate vias

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JP4011695B2 (en) * 1996-12-02 2007-11-21 株式会社東芝 Chip for multi-chip semiconductor device and method for forming the same
FR2805709B1 (en) 2000-02-28 2002-05-17 Commissariat Energie Atomique ELECTRICAL CONNECTION BETWEEN TWO FACES OF A SUBSTRATE AND METHOD OF MAKING
SE526366C3 (en) 2003-03-21 2005-10-26 Silex Microsystems Ab Electrical connections in substrate
JP4795677B2 (en) * 2004-12-02 2011-10-19 ルネサスエレクトロニクス株式会社 Semiconductor device, semiconductor module using the same, and manufacturing method of semiconductor device
JP5021992B2 (en) * 2005-09-29 2012-09-12 ルネサスエレクトロニクス株式会社 Semiconductor device and manufacturing method thereof
US7902069B2 (en) 2007-08-02 2011-03-08 International Business Machines Corporation Small area, robust silicon via structure and process
JP2009124087A (en) * 2007-11-19 2009-06-04 Oki Semiconductor Co Ltd Method of manufacturing semiconductor device
JP2010177237A (en) * 2009-01-27 2010-08-12 Seiko Epson Corp Semiconductor device, method for manufacturing the same, through-electrode, method for manufacturing through-electrode, oscillator and electronic equipment
US20100224965A1 (en) * 2009-03-09 2010-09-09 Chien-Li Kuo Through-silicon via structure and method for making the same
US8062975B2 (en) * 2009-04-16 2011-11-22 Freescale Semiconductor, Inc. Through substrate vias

Patent Citations (5)

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US20070069364A1 (en) * 2005-09-29 2007-03-29 Nec Electronics Corporation Semiconductor device and method for manufacturing same
US20080079131A1 (en) * 2006-09-30 2008-04-03 Sung Min Kim Stack package and method for manufacturing the same
US20080124845A1 (en) * 2006-11-28 2008-05-29 Taiwan Semiconductor Manufacturing Co., Ltd. Stacked structures and methods of fabricating stacked structures
US20090057899A1 (en) * 2007-08-30 2009-03-05 Keon-Yong Cheon Semiconductor integrated circuit device and method of fabricating the same
WO2010125164A1 (en) * 2009-04-29 2010-11-04 International Business Machines Corporation Through substrate vias

Also Published As

Publication number Publication date
FR2953992B1 (en) 2012-05-18
US20110143535A1 (en) 2011-06-16
EP2337067A2 (en) 2011-06-22
JP2011129918A (en) 2011-06-30
US8541304B2 (en) 2013-09-24
JP5858612B2 (en) 2016-02-10
FR2953992A1 (en) 2011-06-17
EP2337067B1 (en) 2013-12-11

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