EP2324572A2 - Reseau logique programmable, commutateur d'interconnexion et unite logique pour un tel reseau - Google Patents

Reseau logique programmable, commutateur d'interconnexion et unite logique pour un tel reseau

Info

Publication number
EP2324572A2
EP2324572A2 EP09784255A EP09784255A EP2324572A2 EP 2324572 A2 EP2324572 A2 EP 2324572A2 EP 09784255 A EP09784255 A EP 09784255A EP 09784255 A EP09784255 A EP 09784255A EP 2324572 A2 EP2324572 A2 EP 2324572A2
Authority
EP
European Patent Office
Prior art keywords
routing elements
input
outputs
inputs
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP09784255A
Other languages
German (de)
English (en)
French (fr)
Inventor
Zied Marrakchi
Habib Mehrez
Hayder Mrabet
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Centre National de la Recherche Scientifique CNRS
Universite Pierre et Marie Curie Paris 6
Original Assignee
Centre National de la Recherche Scientifique CNRS
Universite Pierre et Marie Curie Paris 6
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Centre National de la Recherche Scientifique CNRS, Universite Pierre et Marie Curie Paris 6 filed Critical Centre National de la Recherche Scientifique CNRS
Publication of EP2324572A2 publication Critical patent/EP2324572A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/173—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components
    • H03K19/177—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using elementary logic circuits as components arranged in matrix form
    • H03K19/17736—Structural details of routing resources

Definitions

  • the subject of the invention is also a programmable logic network logical unit comprising logic blocks connected to four input ports grouping together a plurality of inputs and four output ports grouping a plurality of outputs, the inputs, the outputs and the logic blocks being connected to a link tree structure, going down from the input ports to the logic blocks and setting logical blocks to the output ports, comprising incoming routing elements and outgoing routing elements arranged in several levels, the incoming routing elements connecting by a single path each input of all the input ports to a single input of each logical block and the outgoing routing elements connecting by a single path each output of a logical block to a single output of each output port and to the incoming routing elements of the same group.
  • each logical unit has
  • interconnect switch a routing device arranged at the intersection of several channels and programmable to direct signals from some of the channels to one or more of the other channels, such a routing member may comprise several routing elements as defined below;
  • Each interconnect switch 2 comprises input ports from the interconnect switches I, output ports to the interconnect switches O, input ports from the logical units I ', output ports to the interconnection switches logical units O '.
  • Each interconnection switch 2 thus comprises eight faces or rather interfaces enabling it to be directly connected to the four adjacent interconnection switches 2 and to the four neighboring logical units 3.
  • Each input port I is thus also connected to all the output ports 0 'by the routing units 4 and 6.
  • the references 400, 500 and 600 shown in FIG. 2 denote all the routing elements 4, 5 and 6 respectively. It will be understood that: the interconnection switches 2 communicate with each other via the routing elements 4 and with the neighboring logic units 3 by the routing elements 4 and 6; the logical units 3 communicate with the neighboring logical units via the routing elements 5 and the routing elements 6 of the neighboring interconnection switches (each of the interconnection switches neighboring a logic unit allows this logic unit to be connected to the other three logical units to which this interconnect switch is connected, without going through another interconnect switch).
  • the link tree structure thus defined descends from the inputs to the outputs with the routing elements 4, 5, 6 organized according to several levels to connect: - an input of an input port from a neighboring logic unit I 'to kl outputs an output port to a neighboring logical unit O 'passing through two routing elements 5, 6, where k1 is the ratio of the number of outputs of said output port to the number of inputs of said input port,
  • first-level incoming routing elements 8 having four outputs each connected to an input of all the logical blocks 7 of its first-level group

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
  • Logic Circuits (AREA)
EP09784255A 2008-07-09 2009-07-08 Reseau logique programmable, commutateur d'interconnexion et unite logique pour un tel reseau Withdrawn EP2324572A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR0803903A FR2933826B1 (fr) 2008-07-09 2008-07-09 Reseau logique programmable, commutateur d'interconnexion et unite logique pour un tel reseau
PCT/FR2009/000845 WO2010004140A2 (fr) 2008-07-09 2009-07-08 Reseau logique programmable, commutateur d'interconnexion et unite logique pour un tel reseau

Publications (1)

Publication Number Publication Date
EP2324572A2 true EP2324572A2 (fr) 2011-05-25

Family

ID=40485730

Family Applications (1)

Application Number Title Priority Date Filing Date
EP09784255A Withdrawn EP2324572A2 (fr) 2008-07-09 2009-07-08 Reseau logique programmable, commutateur d'interconnexion et unite logique pour un tel reseau

Country Status (6)

Country Link
US (1) US7795911B2 (zh)
EP (1) EP2324572A2 (zh)
JP (1) JP2011527543A (zh)
CN (1) CN102089976B (zh)
FR (1) FR2933826B1 (zh)
WO (1) WO2010004140A2 (zh)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
BR112014024312B1 (pt) * 2012-03-30 2022-04-12 Intel Corporation Sistema e método de implementação de uma matriz de dispositivo programável em um sistema eletrônico
US9900011B2 (en) * 2016-03-07 2018-02-20 Kabushiki Kaisha Toshiba Semiconductor apparatus, routing module, and control method of semiconductor apparatus
CN112131813B (zh) * 2020-09-25 2022-02-18 无锡中微亿芯有限公司 基于端口交换技术的用于提升布线速度的fpga布线方法

Family Cites Families (16)

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Publication number Priority date Publication date Assignee Title
US5477165A (en) * 1986-09-19 1995-12-19 Actel Corporation Programmable logic module and architecture for field programmable gate array device
JPH02224439A (ja) * 1989-02-27 1990-09-06 Nippon Telegr & Teleph Corp <Ntt> 分散制御形データ通信方法
US5255203A (en) * 1989-08-15 1993-10-19 Advanced Micro Devices, Inc. Interconnect structure for programmable logic device
US5198705A (en) * 1990-05-11 1993-03-30 Actel Corporation Logic module with configurable combinational and sequential blocks
GB9312674D0 (en) * 1993-06-18 1993-08-04 Pilkington Micro Electronics Configurabel logic array
WO1995022205A1 (en) * 1994-02-15 1995-08-17 Xilinx, Inc. Tile based architecture for fpga
US5682107A (en) * 1994-04-01 1997-10-28 Xilinx, Inc. FPGA architecture with repeatable tiles including routing matrices and logic matrices
US5894565A (en) * 1996-05-20 1999-04-13 Atmel Corporation Field programmable gate array with distributed RAM and increased cell utilization
GB2374242B (en) * 2001-04-07 2005-03-16 Univ Dundee Integrated circuit and related improvements
US7058918B2 (en) * 2003-04-28 2006-06-06 Dafca, Inc. Reconfigurable fabric for SoCs using functional I/O leads
US7768314B2 (en) * 2004-05-12 2010-08-03 National University Corporation Okayama University Integrated circuit with multidimensional switch topology
EP1953916A1 (en) * 2005-11-25 2008-08-06 Matsushita Electric Industrial Co., Ltd. Logic block control system and logic block control method
US7274215B2 (en) * 2006-01-17 2007-09-25 M2000 Sa. Reconfigurable integrated circuits with scalable architecture including one or more adders
JP4755033B2 (ja) * 2006-07-05 2011-08-24 ルネサスエレクトロニクス株式会社 半導体集積回路
US9071246B2 (en) * 2007-09-14 2015-06-30 Agate Logic, Inc. Memory controller for heterogeneous configurable integrated circuits
US7557605B2 (en) * 2007-09-14 2009-07-07 Cswitch Corporation Heterogeneous configurable integrated circuit

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO2010004140A2 *

Also Published As

Publication number Publication date
WO2010004140A2 (fr) 2010-01-14
CN102089976A (zh) 2011-06-08
JP2011527543A (ja) 2011-10-27
WO2010004140A3 (fr) 2010-10-14
FR2933826B1 (fr) 2011-11-18
US7795911B2 (en) 2010-09-14
FR2933826A1 (fr) 2010-01-15
US20100007378A1 (en) 2010-01-14
CN102089976B (zh) 2014-04-23

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