EP2317413A1 - Verfahren zur Spannungsregulierung und Spannungsregelungsanordnung - Google Patents

Verfahren zur Spannungsregulierung und Spannungsregelungsanordnung Download PDF

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Publication number
EP2317413A1
EP2317413A1 EP09013621A EP09013621A EP2317413A1 EP 2317413 A1 EP2317413 A1 EP 2317413A1 EP 09013621 A EP09013621 A EP 09013621A EP 09013621 A EP09013621 A EP 09013621A EP 2317413 A1 EP2317413 A1 EP 2317413A1
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EP
European Patent Office
Prior art keywords
voltage
input voltage
vfin
terminal
vint
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Withdrawn
Application number
EP09013621A
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English (en)
French (fr)
Inventor
Alessandro Carbonini
Carlo Fiocchi
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Ams AG
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Austriamicrosystems AG
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Priority to EP09013621A priority Critical patent/EP2317413A1/de
Publication of EP2317413A1 publication Critical patent/EP2317413A1/de
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00—Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10—Regulating voltage or current
    • G05F1/46—Regulating voltage or current wherein the variable actually regulated by the final control device is dc
    • G05F1/56—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices
    • G05F1/565—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G05F1/569—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection
    • G05F1/571—Regulating voltage or current wherein the variable actually regulated by the final control device is dc using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection with overvoltage detector

Definitions

  • the present invention relates to a method for voltage regulation and a voltage regulator arrangement.
  • Voltage regulators achieve that goal and are as diverse as their fields of application.
  • LDOs low-dropout regulators
  • combination of fast start-up and low overshoot is detrimental to many applications. Achieving such performance is usually far from being straightforward and, in most cases, goes along with accepting other restrictions like in load and line regulation, high frequency PSSR (power supply rejection ratio) or load transient response.
  • FIG. 1A shows an exemplary embodiment of a voltage regulator arrangement based on a LDO according to prior art.
  • the voltage regulator VR comprises an input terminal In and an output terminal Out.
  • the output terminal Out is coupled to a series connection of a first resistor R1 and a second resistor R2. Furthermore, the output terminal Out feeds back via the first resistor R1 to a reference input terminal Ref of the voltage regulator VR.
  • the second resistor R2 is connected to common ground GND.
  • Figure 1B shows an exemplary start-up phase for the voltage regulator VR according to Figure 1A .
  • the graph depicted in Figure 1B shows input voltage and regulated output voltages applied to or provided by the voltage regulator arrangement as a function of time.
  • input voltage Vin and regulated output voltage Vout are not equal but scaled with respect to each other by a certain factor, e.g. determined by a ratio of resistances R1, R2 given as (1 + R1/R2).
  • the gain bandwidth of the voltage regulator VR may be reduced according to prior art.
  • the input voltage Vin is applied in the same way as before.
  • the black line in Figure 1B represents the reduced output voltage rVout output by a voltage regulator VR with reduced bandwidth. It is apparent from Figure 1B that no significant overshoot in the reduced output voltage rVout occurs.
  • Reducing bandwidth may be achieved by filtering the bias current of the voltage regulator VR, e.g. of a low dropout regulator LDO, by means of ⁇ filters.
  • Figure 1C shows the start-up phase of the voltage regulator arrangement of Figure 1A according to prior art.
  • an alternative solution is possible. By ramping up or smoothing the input voltage Vin the regulated output voltage Vout stays close to the input voltage Vin at all times. This way, overshoot is prevented from exceeding the final desired value.
  • an integrated circuit comprises more than one regulated output terminal Out or channel (hereinafter denoted a multi-channel voltage regulator arrangement).
  • a multi-channel voltage regulator arrangement regulated output terminal Out or channel
  • Prior art solutions as described above may lead to serious trade-offs between large area requirement and corresponding high noise levels. This is due to the fact that in multi-channel arrangements like components (e.g. filters or intermediate buffers) have to be implemented for each individual channel. In case of very high load capacities and load currents such solutions are not very effective as settling takes place at maximum bandwidth if a long time elapses from power down release.
  • a method for voltage regulation comprises a step of providing a sequence of input voltages of at least one intermediate input voltage and a target input voltage, and selecting the at least one intermediate input voltage from the sequence of input voltages. Furthermore, regulating an output voltage depending on the at least one intermediate input voltage such that the output voltage reaches a steady-state condition. Moreover, the method comprises a step of selecting the target input voltage in the sequence of input voltages. Next, regulating the output voltage depending on the target input voltage such that the output voltage reaches the steady-state condition is performed.
  • the step-size denotes a voltage difference between two consecutively applied input voltages, e.g. the voltage difference between the at least one intermediate input voltage or the target input voltage. Any voltage coupled to an input terminal of the voltage regulator shall be considered an input voltage.
  • input voltages and step-sizes can be tailored depending on the application and such that overshoot stays lower than the target input voltage or exceeds this voltage by just a little but tolerable amount. This way, only a final step-size determines the overshoot which can be rather low. Consequently, the method for voltage regulation mitigates the trade-offs between overshooting amplitude and fast start-up times.
  • the method for voltage regulation is flexible and can be applied to any kind of voltage regulator, preferably low dropout regulators (LDOs).
  • the method for voltage regulation is advantageously implemented in dual or multiple channel arrangements. Area requirement and noise level are advantageously reduced due to few components needed for implementing the method e.g. with appropriate components on an integrated circuit. Additionally, performance of the voltage regulator does not depend on load conditions and bandwidth is not modified as no filters are necessary to create increase the voltage regulator's bias current.
  • the steps of voltage regulation are implemented during a start-up phase.
  • the start-up phase shall be defined as that particular period of time, starting from switching-on the voltage regulator, necessary for the regulated output voltage to reach a value characterized by the desired target input voltage.
  • the steady-state condition may be used to indicate the end of the start-up phase.
  • the method for voltage regulation comprises a step of selecting a further intermediate input voltage from the sequence of input voltages and is provided between the at least one intermediate input voltage and the target input voltage. Furthermore, it comprises a step of regulating the output voltage depending on the further intermediate input voltage such that the output voltage reaches the steady-state condition.
  • selecting input voltages follows a step-wise approach, i.e. the at least one input voltage is selected first. In a next step the further intermediate input voltage is selected and so on. Finally, in a last step the target input voltage is selected.
  • corresponding step-sizes are chosen so as to increase input voltages up to the target input voltage. Note that in conjunction with each step and selection of input voltages just a single i.e. selected input voltage is coupled to the input terminal.
  • choosing more than one intermediate input voltage allows for a more flexible approach to reach the final target input voltage.
  • the number and step-size of each individual intermediate input voltage may be chosen appropriate to a given application. This way, overshoot is further reduced for all intermediate input voltages.
  • the method for voltage regulation comprises successive selection of a number of N further intermediate input voltages in the sequence of input voltages. Furthermore, it comprises corresponding successive regulation of the output voltage depending on the respective of the N further intermediate input voltages such that the output voltage increases in a step-like fashion until the target input voltage in the sequence of input voltages is selected.
  • the method for voltage regulation comprises a step of regulating the output voltage depending on the target input voltage.
  • the output voltage can be regulated as, approximately, a smooth function without any substantial edges. This way, overshoot is reduced at all times during start-up. Essentially this approach mimics filtering or smoothing of input voltage edges but, however, without using any additional arrangements, e.g. filters for each individual channel as for multi-channel arrangements. Therefore, area requirements and noise level are advantageously reduced.
  • the method for voltage regulation comprises a steady-state condition which is reached if the input voltage, e.g. intermediate input voltage, further intermediate input voltage or target input voltage equals the regulated output voltage multiplied by a scaling factor.
  • the scaling factor may be defined by system parameters such as resistances.
  • detecting reaching the steady-state condition using appropriate measuring means can help optimizing start-up times.
  • the steady-state condition may account for experimental tolerances, e.g. noise and other distortions.
  • the steady-state condition may be reached already if the output voltage is regulated within a certain tolerance interval, e.g. ⁇ 10 %.
  • reaching the steady-state condition is indicated by a steady-state signal.
  • start-up phase of a voltage regulator can be further shortened to provide fast start-up times.
  • a power ok signal is used for that purpose which, conveniently, is already implemented in many conventional LDO circuits.
  • the method for voltage regulation comprises a step in which reaching the steady-state condition is indicated by a time period.
  • the time to reach steady-state may be within a characteristic time period.
  • Such time period can be employed to indicate steady-state by simple components such as timers.
  • the timer may define a certain amount of time between selection of an input voltage, e.g. at least one intermediate input voltage, further intermediate input voltage or target input voltage, which then is coupled to the input terminal.
  • timers are inexpensive and simple components to be integrated into applications where an appropriate time period between selection of input voltages is known or defined by a desired value.
  • Timers may be used as an alternative to appropriate means to indicate the steady-state signal as e.g. the power ok signal.
  • the method for voltage regulation comprises a step in which the further intermediate input voltage is selected depending on the steady-state signal indicating the steady-state condition.
  • a voltage regulator arrangement comprises a voltage regulator having an input terminal and an output terminal. Furthermore, the voltage regulator arrangement comprises an arrangement for generating at least one intermediate input voltage and a target input voltage. Next, the voltage regulator arrangement comprises a start-up selection circuit for selecting the at least one intermediate input voltage or the target input voltage.
  • the start-up selection circuit selects the at least one intermediate input voltage or the target input voltage and couples the at least one intermediate input voltage or the target input voltage to the input terminal during a start-up phase.
  • the at least one intermediate input voltage is smaller than the target input voltage.
  • the at least one intermediate input voltage may preferably be consecutively applied to the voltage regulator in a step-like fashion.
  • the voltage regulator arrangement can be implemented with any kind of voltage regulator, preferably low dropout regulators (LDO).
  • LDO low dropout regulators
  • this is an advantage if implemented in dual or multiple channel voltage regulator arrangements as components are shared for each channel. This way, area consumption and noise are advantageously reduced.
  • performance does not depend on load conditions and bandwidth of the voltage regulator, e.g. a LDO, is not modified.
  • stepwise approach i.e. using the start-up selection circuit to consecutively couple the at least one intermediate input voltage or target input voltage to the input terminal.
  • overshoot is almost proportional to the step-size and allows for keeping overshoot comparably low during the entire start-up phase.
  • a step-size associated with selection of the target input voltage leads to an overshoot which can be quite small compared to the target input voltage.
  • the start-up selection circuit comprises a further intermediate input voltage which is provided between the at least one intermediate input voltage and the target input voltage.
  • the start-up selection circuit selects the further intermediate input voltage and couples the further intermediate input voltage to the input terminal.
  • the start-up selection circuit only selects one input voltage, i.e. either the at least one intermediate input voltage, further intermediate input voltage or target input voltage such that only a single input voltage is coupled to the input terminal at a time.
  • the start-up selection circuit successively selects a number of N increasing further intermediate input voltages.
  • the number of N increasing further intermediate input voltages are provided between the at least one intermediate input voltage and the target input voltage.
  • the start-up selection circuit selects a number of N increasing further intermediate input voltages such that it, in a step-like fashion, successively couples the number of N increasing further intermediate input voltages to the input terminal.
  • the regulated output voltage approximately follows a smooth function without any significant edges.
  • the voltage regulator arrangement removes the need of an individual input circuit like a filter for each channel.
  • the start-up selection circuit selects the at least one intermediate input voltage, further intermediate input voltage or the target input voltage depending on a steady-state signal indicating a steady-state condition.
  • the steady-state condition is reached if the intermediate input voltage, further intermediate input voltage or target input voltage equals a regulated output voltage at the output terminal.
  • indicating a steady-state condition allows for improved control of the start-up phase of the voltage regulator arrangement.
  • start-up phase can be reduced in time. This is especially important for applications demanding fast start-up times.
  • the steady-state condition may account for experimental tolerances, e.g. noise and other distortions.
  • the steady-state condition may be reached already if the output voltage is regulated within a certain tolerance interval, e.g. ⁇ 10 %.
  • the voltage regulator arrangement comprises a start-up selection circuit selecting the at least one intermediate input voltage, further intermediate input voltage or target input voltage depending on the steady-state signal.
  • the steady-state signal constitutes a power ok signal of a LDO.
  • a power ok signal asserts that the LDO has reached the steady-state condition and is conveniantly implemented in most commercially available LDO circuits.
  • the power ok signal is only applied after a delay depending on the LDO gain bandwidth and phase margin, i.e. the time it takes for the overshoot to die out. Thus, the power ok signal indicates that LDO is ready to settle to a next input voltage again.
  • the start-up selection circuit selects the at least one intermediate input voltage, further intermediate input voltage or target input voltage depending on a predetermined time period.
  • the start-up selection circuit comprises a timer circuit, which usually is already present in commercially available LDOs and implemented into sub-circuits that regulate pre-charging of noise filters.
  • the voltage regulator arrangement comprises a voltage regulator having a reference input terminal and the output terminal feeds back to the reference input terminal.
  • the voltage regulator is a LDO.
  • the arrangement comprises at least one intermediate input voltage terminal fed by the intermediate input voltage and a target input voltage terminal fed by the target input voltage.
  • the start-up selection circuit may comprise a multiplexer.
  • the multiplexer electrically couples the at least one intermediate input voltage terminal or the target input voltage terminal to the input terminal.
  • the arrangement comprises a variable resistor coupled between the output terminal and the reference input terminal and is connected to common ground.
  • the variable resistor comprises taps which are coupled to the reference terminal of the voltage regulator.
  • the start-up selection circuit sets the variable resistor such that the at least one intermediate input voltage or the target input voltage terminal is effectively connected to the reference input terminal.
  • the voltage applied at the input terminal is kept constant and the regulated output at the output terminal changes in steps of resistance set to the variable resistor.
  • the start-up selection circuit may comprise a multiplexer and the arrangement may comprise a variable resistor coupled between the output terminal and the reference input terminal.
  • FIG. 2A shows an exemplary embodiment of a voltage regulator arrangement according to the principle presented.
  • a voltage regulator VR comprises an input terminal In and an output terminal Out.
  • the output terminal Out is connected to a series connection of a first resistor R1 and a second resistor R2.
  • the first resistor R1 is connected to a reference input terminal Ref of the voltage regulator VR.
  • the second resistor R2 is connected to the ground level GND.
  • the input terminal In is connected to a start-up selection circuit Sel which comprises a multiplexer Mux.
  • the start-up selection circuit Sel is coupled to an arrangement Arr for generating at least one intermediate input voltage Vint and a target input voltage Vfin which comprises an intermediate input voltage terminal Int and a target input voltage terminal Fin.
  • the intermediate input voltage terminal Int is coupled to the intermediate input voltage Vint
  • the target input voltage terminal Fin is coupled to the target input voltage Vfin.
  • the start-up selection circuit Sel successively selects the intermediate input voltage Vint and the target input voltage Vfin and couples the respectively selected one input voltage to the input voltage terminal of the voltage regulator VR.
  • the start-up selection circuit triggers the multiplexer Mux to electrically couple the intermediate input voltage Vint and the target input voltage Vfin, respectively, to the input voltage terminal In of the voltage regulator VR.
  • Figure 2B shows another exemplary embodiment of a voltage regulator arrangement according to the presented principle.
  • the arrangement Arr comprises the first resistor R1 and the second resistor R2, in turn, comprising a variable resistor Rvar.
  • resistor R1 or both R1 and R2 can be made variable.
  • the start-up selection circuit Sel sets the resistance of the variable resistor Rvar. Thereby, the arrangement Arr generates the at least one intermediate input voltage Vint or target input voltage Vfin which is then coupled to the reference input terminal Ref.
  • the voltage regulator arrangements according to Figure 2A and 2B can be implemented with any kind of voltage regulator VR, preferably with LDOs, i.e. low dropout regulators.
  • this is an advantage if implemented in dual or multiple channel voltage regulator arrangements. Area requirements and noise are lowered and performance does not depend on load conditions. Furthermore, bandwidth of the voltage regulator VR, e.g. an LDO, is not modified.
  • the start-up selection circuit Sel comprises a logic circuitry to modulate the variable resistor Rvar depending on the target input voltage Vfin.
  • Figure 2C shows the start-up phase of the voltage regulator arrangement according to Figures 2A or 2B.
  • Figure 2C shows input voltages and regulated output voltages applied to or provided by the voltage regulator arrangement as a function of time.
  • the selection circuit Sel couples the at least one intermediate input voltage Vint to the input terminal In or the reference input terminal Ref, respectively.
  • the voltage regulator VR regulates the output voltage Vout. This results in a first overshoot 1 in the output voltage Vout.
  • the selection circuit Sel couples the target input voltage Vfin to the input terminal In or the reference input terminal Ref, respectively.
  • the voltage regulator VR regulates the output voltage Vout resulting in a relatively small second overshoot 2.
  • the start-up selection circuit Sel the at least one intermediate input voltage Vint or target input voltage Vfin is coupled to the input terminal In or reference input terminal Ref, respectively, during the start-up phase in a stepwise approach.
  • overshoot is almost proportional to the step-size and can be tailored to keep overshoot low during the entire start-up phase.
  • a final step-size leads to an overshoot which can be quite small compared to the target input voltage Vfin.
  • the arrangement Arr comprises at least one further intermediate input voltage which is provided between the at least one intermediate input voltage Vint and the target input voltage Vfin.
  • the arrangement Arr comprises an at least one further intermediate input voltage terminal.
  • the start-up selection circuit Sel selects and couples the further intermediate input voltage to the input terminal In or reference input terminal Ref, respectively.
  • the arrangement Arr generates a number of N increasing further intermediate input voltages provided between the at least one intermediate input voltage Vint and the target input voltage Vfin.
  • the start-up selection circuit Sel successively selects and couples, in a step like fashion, the number of N increasing further intermediate input voltages to the input terminal In or reference input terminal Ref, respectively.
  • FIG. 3 shows an exemplary embodiment of the start-up selection circuit according to the presented principle.
  • the start-up selection circuit Sel comprises a multiplexer Mux which is embedded in a first amplification stage of the voltage regulator VR.
  • the multiplexer comprises a first and second source-coupled transistor pair circuit TP1 and TP2 plus a current switch S1a and S1b coupled to transistor pair circuit TP1 and TP2, respectively.
  • Each transistor pair circuit TP1 and TP2 further comprises a first transistor T1 and a second transistor T2 which share the same source terminal.
  • Each first and second transistor T1 and T2 is, at its drain side, coupled to a loading block of the first amplification stage, made up by a first and second load transistor MP1, MP2, respectively, which are connected in a current mirror configuration.
  • a bias current Itail coupled to a supply rail is deviated into one out of the two common sources of the transistor pair circuits TP1, TP2 by means of the complementary switches S1a and S1b which may be digitally driven by a selection block.
  • the supply rail may either be ground potential GND or any supply-voltage, e.g. Vdd in case the transistor pair circuit is in PMOS.
  • the first transistor T1 has a control terminal C1a and the second transistor T2 a control terminal C2a.
  • the first transistor T1 has a control terminal C1b and the second transistor T2 a control terminal C2b.
  • the second control terminal C2a of the first transistor pair circuit TP1 is connected to the first control terminal C1b of the second transistor pair circuit TP2.
  • the at least one input voltage Vint is coupled to the first control terminal C1a of the first transistor pair circuit TP1 and the target input voltage Vfin is coupled to the second control terminal C2b of the second transistor pair circuit TP2.
  • Both control terminals C1a and C2b are coupled to the reference input terminal Ref of the voltage regulator VR.
  • the bias current Itail is deviated between the first transistor pair circuit TP1 and the second transistor pair circuit TP2.
  • the bias current Itail is deviated between the first transistor pair circuit TP1 and the second transistor pair circuit TP2.
  • only one of the two transistor pair circuits TP1, TP2 is effectively connected to the load transistors MP1, MP2 of the first amplification stage of the voltage regulator VR while the other is left in an off-state. Consequently, only one input voltage between Vint and Vfin is effectively coupled to input terminal In of the voltage regulator VR.
  • switching tail current Itail from one transistor pair circuit to another is so fast that no significant spikes occur at the control terminals C1a, C1b, C2a and C2b of the transistors.
  • the control terminals are loaded by parasitics such that if tail currents Itail are not fed for fractions of nanoseconds operation of the voltage regulator VR does not fail.
  • the at least one intermediate input voltage Vint and target input voltage Vfin, as well other appropriate input voltages may e.g. be obtained from the arrangement Arr by taking some taps of a resistor string which generates a reference voltage. Such an approach is effective if the final output voltage Vout of the voltage regulator VR stays higher than a minimum common mode voltage.
  • the multiplexer Mux comprises series connection of a number of N parallel transistor pair circuits TP to provide N further intermediate input voltages to the voltage regulator VR.
EP09013621A 2009-10-29 2009-10-29 Verfahren zur Spannungsregulierung und Spannungsregelungsanordnung Withdrawn EP2317413A1 (de)

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EP09013621A EP2317413A1 (de) 2009-10-29 2009-10-29 Verfahren zur Spannungsregulierung und Spannungsregelungsanordnung

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9385587B2 (en) 2013-03-14 2016-07-05 Sandisk Technologies Llc Controlled start-up of a linear voltage regulator where input supply voltage is higher than device operational voltage

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5917313A (en) * 1997-12-19 1999-06-29 Stmicroelectronics, Inc. DC-to-DC converter with soft-start error amplifier and associated method
US6218887B1 (en) * 1996-09-13 2001-04-17 Lockheed Martin Corporation Method of and apparatus for multiplexing multiple input signals
US20070018623A1 (en) * 2005-07-21 2007-01-25 Agere Systems Inc. Low-dropout regulator with startup overshoot control
US20070063736A1 (en) * 2005-09-19 2007-03-22 Texas Instruments Incorporated Soft-start circuit and method for power-up of an amplifier circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6218887B1 (en) * 1996-09-13 2001-04-17 Lockheed Martin Corporation Method of and apparatus for multiplexing multiple input signals
US5917313A (en) * 1997-12-19 1999-06-29 Stmicroelectronics, Inc. DC-to-DC converter with soft-start error amplifier and associated method
US20070018623A1 (en) * 2005-07-21 2007-01-25 Agere Systems Inc. Low-dropout regulator with startup overshoot control
US20070063736A1 (en) * 2005-09-19 2007-03-22 Texas Instruments Incorporated Soft-start circuit and method for power-up of an amplifier circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9385587B2 (en) 2013-03-14 2016-07-05 Sandisk Technologies Llc Controlled start-up of a linear voltage regulator where input supply voltage is higher than device operational voltage

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