EP2309543B1 - Verfahren zur Verbesserung der Zuverlässigkeit eines P-Kanal-Halbleiterbauelements und damit hergestelltes P-Kanal-Halbleiterbauelement - Google Patents

Verfahren zur Verbesserung der Zuverlässigkeit eines P-Kanal-Halbleiterbauelements und damit hergestelltes P-Kanal-Halbleiterbauelement Download PDF

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EP2309543B1
EP2309543B1 EP10186985A EP10186985A EP2309543B1 EP 2309543 B1 EP2309543 B1 EP 2309543B1 EP 10186985 A EP10186985 A EP 10186985A EP 10186985 A EP10186985 A EP 10186985A EP 2309543 B1 EP2309543 B1 EP 2309543B1
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layer
channel
semiconductor
semiconductor device
bandgap
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EP2309543A1 (de
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Ben Kaczer
Jacopo Franco
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Katholieke Universiteit Leuven
Interuniversitair Microelektronica Centrum vzw IMEC
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Katholieke Universiteit Leuven
Interuniversitair Microelektronica Centrum vzw IMEC
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1054—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure with a variation of the composition, e.g. channel with strained layer for increasing the mobility
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4966—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane

Definitions

  • the present invention relates to the field of semiconductor devices, more particularly to the field of P-channel semiconductor devices.
  • the present invention relates to enhancing reliability, more particularly NBTI reliability, of such devices.
  • Embodiments of the present invention are particularly useful for sub-1 nm EOT devices.
  • Negative bias temperature instability is a significant reliability concern for submicron CMOS technologies, particularly to the PMOS transistors therein. It is widely believed that NBTI degradation is due to generation of interface traps, which are unsaturated silicon dangling bonds.
  • One of the most popular models explaining NBTI phenomenon is the reaction diffusion model. This model proposes that the generation of interface traps is because of a hole induced electrochemical reaction at the Si-SiO 2 interface. In the initial times the degradation is reaction rate controlled, however, with time the phenomenon becomes diffusion limited. In addition to this, it is also believed that a consistent part of the NBTI degradation is due to a hole-trapping mechanism, whereby a hole gets trapped in a trap state, causing a shift in the threshold voltage.
  • NBTI has always been associated with the CMOS development, but it was not considered of great importance because of the low electric fields in operation. However, as there is an increasing demand for higher drive current, NBTI has become a major reliability problem for the semiconductor industry, in particular it is a key reliability issue in MOSFETs.
  • NBTI When a P-channel semiconductor device, such as a PMOSFET, is biased with negative gate voltages especially at elevated temperatures, i.e. normal operating conditions, degradation of main device parameters (threshold voltage, transconductance, drive current, subthreshold slope, etc.) is observed: NBTI manifests as an increase in the threshold voltage and a consequent decrease in drain current and transconductance. The mechanism is caused by holes interacting with defect precursors in the oxide and at the oxide/semiconductor interface.
  • EOT effective oxide thickness
  • the present invention provides a method for forming a P-channel semiconductor device with good NBTI reliability.
  • the method comprises providing a P-channel semiconductor device comprising a P-channel layer, and a control electrode on the semiconductor P-channel layer comprising at least a gate dielectric layer.
  • the gate dielectric layer has a conduction band and a valence band, there being an energy bandgap between the conduction band and the valence band.
  • the gate dielectric layer has an exponentially-shaped distribution of defect levels E(defect) in its energy bandgap, the exponentially-shaped distribution of defect levels having a lower concentration of defect levels at the centre of the bandgap and a higher concentration of defect levels at the edges of the bandgap.
  • the density of defect levels in the gate dielectric layer is exponentially decreasing as a function of energy from the band edges of an adjacent layer.
  • the adjacent layer considered is the one adjacent to the gate dielectric layer at a same side of the gate dielectric layer as the P-channel layer.
  • the exponentially decreasing distribution of defect levels may be expressed as function of the energy of the band edges of the semiconductor P-channel layer itself.
  • the exponentially decreasing distribution of defect levels may be expressed as a function of the energy of the band edges of a capping layer between the P-channel layer and the gate dielectric layer.
  • the method according to embodiments of the present invention comprises selecting at least one parameter of the P-channel semiconductor device such that the inversion carrier injection into the distribution of defect levels occurs as close as possible to the centre of the bandgap of a layer adjacent the gate dielectric layer at the side of the P-channel layer, i.e. so that the inversion carrier injection level does deviate from the energy level at the centre of the bandgap of the adjacent layer with a value not more than 49%, such as not more than 40%, for example not more than 20%, not more than 10%, even not more than 5% of that bandgap (in eV).
  • the layer adjacent the gate dielectric layer at the side of the P-channel layer may be the P-channel layer itself, or optionally a capping layer.
  • selecting at least one parameter of the P-channel semiconductor device such that the inversion carrier injection level does deviate from the energy level at the centre of the bandgap of the adjacent layer with a value not more than 49%, such as not more than 40%, for example not more than 20%, not more than 10%, even not more than 5% of that bandgap (in eV) may comprise selecting the thickness of the semiconductor P-channel layer between a few mono-layers and 20 nm, for example between 3 nm and 20 nm, for example between 5 nm and 20 nm, such as between 7 nm and 20 nm.
  • selecting parameters of the P-channel semiconductor device such that the inversion carrier injection level does deviate from the energy level at the centre of the bandgap of the adjacent layer with a value not more than 49%, such as not more than 40%, for example not more than 20%, not more than 10%, even not more than 5% of that bandgap (in eV) may comprise selecting the concentration in the semiconductor P-channel layer of the semiconductive element with the smallest bandgap between 25% and 99%.
  • a method according to the present invention may comprise selecting the concentration in the semiconductor P-channel layer of the semiconductive element with the smallest bandgap higher than 50%, for example higher than 55%, e.g. higher than 60%.
  • selecting parameters of the P-channel semiconductor device such that the inversion carrier injection level does deviate from the energy level at the centre of the bandgap of the adjacent layer with a value not more than 49%, such as not more than 40%, for example not more than 20%, not more than 10%, even not more than 5% of that bandgap (in eV) may comprise selecting the thickness of the semiconductor capping layer between 0.1 nm and 5 nm.
  • a method according to the present invention may comprise selecting the thickness of the semiconductor capping layer 2 nm or below, for example 1.5 nm or below, 1 nm or below, 0.65 nm or below.
  • a method according to embodiments of the present invention comprises selecting at least one parameter of the P-channel semiconductor device so as to obtain, compared to prior art methods, increased thickness of the P-channel layer, e.g. SiGe layer, and/or increased content of the smallest bandgap semiconductive element in the P-channel layer, e.g. increased Ge content in a SiGe layer, and/or decreased thickness of a capping layer, e.g. Si capping layer.
  • a decreased thickness of a capping layer which is only optionally present, per se already yields good results in terms of NBTI reliability.
  • the present invention provides a P-channel semiconductor device comprising a semiconductor P-channel layer, and a control electrode on the semiconductor P-channel layer.
  • the control electrode comprises at least a gate dielectric layer, the gate dielectric layer having an exponentially-shaped distribution of defect levels E(defect) in its energy bandgap, the exponentially-shaped distribution of defect levels having a lower concentration of defect levels at the centre of the bandgap and a higher concentration of defect levels at the edges of the bandgap.
  • the density of defect levels in the gate dielectric layer is exponentially decreasing as a function of energy from the band edges of an adjacent layer.
  • the adjacent layer may be the semiconductor P-channel layer itself, or alternatively the adjacent layer may be a capping layer provided between the semiconductor P-channel layer and the gate dielectric layer.
  • the P-channel semiconductor device has an inversion carrier injection into the distribution of defect levels which does deviate from the energy level at the centre of the bandgap of the adjacent layer with a value not more than 49%, such as not more than 40%, for example not more than 20%, not more than 10%, even not more than 5% of that bandgap (in eV).
  • the P-channel layer comprises a combination of at least two semiconductive elements.
  • the P-channel layer may be a SiGe layer.
  • the thickness of the semiconductor P-channel layer e.g. the thickness of the SiGe layer, is between a few mono-layers and 20 nm, preferably higher than 3 nm, for example between 3 nm and 20 nm, for example between 5 nm and 20 nm, such as between 7 nm and 20 nm.
  • the concentration in the semiconductor P-channel layer of the semiconductive element with the smallest bandgap may be between 25% and 99%, for example higher than 50%, for example higher than 55%, e.g. higher than 60%.
  • the P-channel semiconductor device may comprise a capping layer between the semiconductor P-channel layer and the gate dielectric layer, and the thickness of the capping layer may be 2 nm or below, for example 1.5 nm or below, 1 nm or below, 0.65 nm or below.
  • a P-channel semiconductor device may have a sub-1 nm EOT.
  • One way to improve FET performance is by using a strained Si channel layer which incorporates Ge.
  • the NBTI reliability of, in particular, such SiGe devices is described. This is, however, intended to be an example only, and is not intended to be limiting for the invention.
  • the semiconductor device 10 also called herein a P-channel semiconductor device, illustrated in FIG. 1 comprises a substrate 11, e.g. Si substrate, with a semiconductor P-channel layer 12 thereon, e.g. a SiGe P-channel layer.
  • the semiconductor P-channel layer has a valence band energy level E v (channel).
  • the P-channel semiconductor device 10 furthermore comprises a gate dielectric layer 14, e.g. a SiO 2 layer, on the semiconductor P-channel layer 12.
  • the gate dielectric layer 14 has a valence band energy level E v (gate dielectric).
  • the density of defect levels E t in the gate dielectric layer 14 as function of energy is assumed to be exponentially decreasing from the band edges of the adjacent layer (being the semiconductor P-channel layer 12 or optionally, if present, a capping layer 13 between the P-channel layer 12 and the gate dielectric layer 14) toward the centre of the bandgap of this adjacent layer.
  • the channel-dielectric band offset ⁇ E v towards a particular defect level at which charge carriers are injected from the channel into the dielectric is defined as E v (channel) - E t .
  • the semiconductor device 10 may furthermore optionally comprise a capping layer 13, e.g. a Si cap, between the P-channel layer 12 and the gate dielectric layer 14 for having a good passivation of the interface, which is advantageous for device performance, a high-k dielectric layer 15, e.g. a HfO 2 dielectric layer, and a metal gate 16.
  • the corresponding energy band diagram is illustrated in FIG. 2 for an exemplary semiconductor device according to embodiments comprising a SiGe p-channel layer, a Si capping layer and a gate stack comprising a metal gate (MG), a SiO 2 dielectric layer and HfO 2 dielectric layer.
  • MG metal gate
  • SiO 2 dielectric layer a SiO 2 dielectric layer
  • HfO 2 dielectric layer a metal gate
  • the semiconductor device 10 is by purpose engineered such that the inversion carrier injection into the distribution of defect levels occurs as close as possible to the centre of the bandgap of a layer adjacent the gate dielectric layer at the side of the P-channel layer(the semiconductor P-channel layer 12 itself or optionally the capping layer 13).
  • the inversion carrier injection level does deviate from the energy level at the centre of the bandgap of the adjacent layer (the semiconductor P-channel layer 12 or optionally the capping layer 13) with a value not more than 49%, such as not more than 40%, for example not more than 20%, not more than 10%, even not more than 5% of that bandgap (in eV).
  • the gate dielectric defect energy level is actually decoupled from the majority carriers in the channel, which are holes as the channel under consideration is of P-type, because of the low concentration of defects at that energy level.
  • parameters of the semiconductor device 10 are selected such that holes from the semiconductor P-channel layer are prevented from interacting with the gate dielectric defect energy level. This may be obtained by engineering the semiconductor device such that the inversion carrier injection into the distribution of defect levels is so as to avoid interaction between carriers and a high concentration in the distribution of defect levels. This allows reducing NBTI (holes do not "see" the defect level).
  • semiconductor devices for example SiGe semiconductor devices, provides a solution to the NBTI problem, in particular also for sub-1 nm EOT devices, thus significantly increasing operating overdrive voltages while still guaranteeing 10 year device lifetime.
  • selecting parameters of the P-channel semiconductor device such that the inversion carrier injection into the distribution of defect levels does deviate from the energy level at the centre of the bandgap of the adjacent layer with a value not more than 49%, such as not more than 40%, for example not more than 20%, not more than 10%, even not more than 5% of that bandgap (in eV) comprises increasing the thickness of the semiconductor P-channel layer 12.
  • the energy band diagrams of this embodiment are illustrated in FIG. 3 .
  • the left hand side of FIG. 3 illustrates the energy band diagram of a standard SiGe semiconductor device, having a thinner semiconductor P-channel layer 12, while the right hand side of FIG.
  • FIG. 3 illustrates the energy band diagram of a gate stack in accordance with embodiments of the present invention, where the thickness of the semiconductor P-channel layer 12 is increased.
  • Suitable thicknesses of the semiconductor P-channel layer 12, in case the semiconductor P-channel layer is a SiGe layer, are between a few mono-layers and about 20 nm. This upper limit corresponds to the critical thickness for which the SiGe layer relaxes and loses its compressive strain.
  • the defect level distribution responsible for NBTI is indicated by 30.
  • This defect level distribution 30 corresponds to energy levels and corresponding defect concentrations for a specific example of a SiGe P-FET device.
  • the energy bands of the gate dielectric layer 14, indicated by 32 in FIG. 3 correspond to a specific example of a SiO 2 gate dielectric layer with a valence band energy level E v (gate dielectric) of a particular example of a SiGe P-FET device.
  • FIG. 4 shows graphs setting out lifetime of devices in function of
  • Graphs are set out for three different SiGe semiconductor devices: a first device with a SiGe layer of 3 nm thickness (graph 40), a second device with a SiGe layer of 5 nm thickness (graph 41) and a third device with a SiGe layer of 7 nm thickness (graph 42).
  • the SiGe layer comprises Germanium as a smallest bandgap semiconductive element with a concentration of 55%, the Si capping layers is 1.3 nm thick.
  • the first device in order to have a lifetime of 10 years, cannot be allowed to have a
  • cannot be larger than 0.92 V and for the third device, the
  • selecting parameters of the P-channel semiconductor device such that the inversion carrier injection into the distribution of defect levels does deviate from the energy level at the centre of the bandgap of the adjacent layer with a value not more than 49%, such as not more than 40%, for example not more than 20%, not more than 10%, even not more than 5% of that bandgap (in eV) comprises increasing the fraction of the smallest bandgap semiconductive element of the semiconductor P-channel layer 12 in case the semiconductor P-channel layer 12 comprises a combination of semiconductive elements, e.g. the Ge concentration in the SiGe layer.
  • the energy band diagrams of this embodiment are illustrated in FIG. 5 . The left hand side of FIG.
  • FIG. 5 illustrates the energy band diagram of a standard semiconductor device, having a lower fraction of the smallest bandgap semiconductive element in the semiconductor P-channel layer 12, while the right hand side of FIG. 5 illustrates the energy band diagram of a semiconductor device in accordance with embodiments of the present invention, where the fraction of the semiconductive element in the semiconductor P-channel layer 12 is increased. Suitable fractions of the semiconductive element in the semiconductor P-channel layer 12 are between 25 and 99%, for example between 45 and 75%, such as between 55 and 65%.
  • the defect level distribution responsible for NBTI is indicated by 50. This defect level distribution 50 corresponds to energy levels and corresponding defect concentrations for a specific example of a SiGe P-FET device.
  • the energy bands of the semiconductor P-channel layer 12, indicated by 51 in FIG. 5 correspond to a specific example of a SiGe semiconductor P-channel with a particular E v (channel) of a particular SiGe P-FET device.
  • the energy bands of the gate dielectric layer 14, indicated by 52 in FIG. 5 correspond to a specific example of a SiO 2 gate dielectric layer with a valence band energy level E v (gate dielectric) of a particular example of a SiGe P-FET device.
  • FIG. 6 shows graphs setting out lifetime of devices in function of
  • Graphs are set out for three different semiconductor devices: a fourth device with a Ge content in the SiGe layer of 0% (graph 60), a fifth device with a Ge content in the SiGe layer of 45% (graph 61) and a sixth device with a Ge content in the SiGe layer of 55% (graph 62).
  • the thickness of the SiGe layer is about 7 nm and the thickness of the Si capping layer is about 2 nm.
  • the fourth device in order to have a lifetime of 10 years, cannot be allowed to have a
  • cannot be larger than 0.8 V and for the sixth device, the
  • selecting parameters of the P-channel semiconductor device such that the inversion carrier injection into the distribution of defect levels does deviate from the energy level at the centre of the bandgap of the adjacent layer with a value not more than 49%, such as not more than 40%, for example not more than 20%, not more than 10%, even not more than 5% of that bandgap (in eV) comprises decreasing the thickness of the capping layer 13 on the semiconductor P-channel layer 12, e.g. the Si capping layer thickness.
  • the energy band diagrams of this embodiment are illustrated in FIG. 7 .
  • the left hand side of FIG. 7 illustrates the energy band diagram of a standard semiconductor device, having a thicker capping layer, while the right hand side of FIG.
  • FIG. 7 illustrates the energy band diagram of a semiconductor device in accordance with embodiments of the present invention, having a thinner capping layer. Suitable thicknesses of the capping layer are between 0 nm and 5 nm, e.g. between 0.1 nm and 5 nm, such as between 0.65 nm and 3 nm.
  • the defect level distribution responsible for NBTI is indicated by 70. This defect level distribution 70 corresponds to energy levels and torresponding defect concentrations for a specific example of a SiGe P-FET device.
  • the energy bands of the gate dielectric layer 14, indicated by 72 in FIG. 7 correspond to a specific example of a SiO 2 gate dielectric layer with a valence band energy level E v (gate dielectric) of a particular example of a SiGe P-FET device.
  • the energy bands of the capping layer 13, indicated by 73 in FIG. 7 correspond to a specific example of a Si capping layer.
  • FIG. 8 shows graphs setting out lifetime of devices in function of
  • Graphs are set out for four different devices: a seventh device with a Si cap thickness of 0.65 nm (graph 80), an eighth device with a Si cap thickness of 1 nm (graph 81), a ninth device with a Si cap thickness of 1.3 nm (graph 82) and a tenth device with a Si cap thickness of 2 nm (graph 83).
  • the Ge content of the SiGe layer is about 55%.
  • the thickness of the SiGe layer is about 5 nm.
  • the tenth device in order to have a lifetime of 10 years, cannot be allowed to have a
  • cannot be larger than 0.9 V
  • cannot be larger than 1.08 V
  • should not be larger than 1.15 V in order for these to have a lifetime of 10 years.
  • the smaller the cap thickness, e.g. the thinner the Si cap the more the NBTI is reduced.
  • using no Si cap when using a SiGe channel layer leads to very bad interface passivation.
  • the NBTI reliability of the device would still be good, but the device performance would be poor. Hence a trade-off between device passivation and NBTI reliability needs to be made.
  • An example of a P-channel semiconductor device may be a SiGe-channel P-FET comprising a Si capping layer in between the buried SiGe channel layer and a SiO 2 gate dielectric layer. More details for this example are presented hereinafter.
  • NBTI stress experiments were performed on buried SiGe channel P-FETS using the extended-stress-measure technique as described by B. Kaczer et al. in Proc. IEEE IRPS, pp.20-27, 2008 .
  • the gate stack of devices under test and a band diagram of this type of stack in inversion are depicted in FIG. 1 and FIG. 2 , respectively.
  • Three major parameters were varied separately in order to assess their impact on NBTI reliability, i.e. the Ge concentration, the SiGe layer thickness and the Si cap thickness.
  • E ox is calculated from the EOT, equivalent to the E ox that a SiO 2 dielectric with thickness equal to the EOT of the stack would experience.
  • Equivalent E ox extraction is not trivial for such complex gate stacks.
  • Q-V curve is obtained integrating C-V curve; a line is fitted to the linear part of the Q-V curve; the slope of the line represents the extracted C ox ;
  • EOT is calculated from C ox ; finally the equivalent E ox is calculated as
  • ultra-thin EOT semiconductor devices e.g. semiconductor devices with an EOT below 1 nm.
  • ultra-thin EOT devices are implemented by consumption of the gate dielectric interfacial layer, e.g. SiO2 layer, which is known to be detrimental for reliability.
  • the Si capping layer has a considerable impact on the NBTI reliability with thinner cappping layers enhancing the lifetime.
  • EOT reduction by IL scavenging degrades the NBTI reliability faster than high-k scaling.
  • there is an additional reliability deterioration on top of that caused by the electric field increase due to EOT scaling (maximum operating Eox vs. T inv would stay constant as observed for thick EOT Si devices).
  • FIG. 9 illustrates that a high Ge fraction (55%) and a thick SiGe layer (6.5 nm) combined with the use of a thin Si cap (0.8 nm) boost NBTI lifetime to meet the target condition (

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Claims (14)

  1. Verfahren zum Bilden eines P-Kanal-Halbleiterbauelements (10) mit guter NBTI-Zuverlässigkeit,
    das Verfahren umfassend Bereitstellen eines P-Kanal-Halbleiterbauelements (10), umfassend eine P-Kanal-Schicht (12), und eine Steuerelektrode (16) auf der Halbleiter-P-Kanal-Schicht, umfassend mindestens eine Gatedielektrikumsschicht (14), wobei die Gatedielektrikumsschicht (14) eine exponentiell geformte Verteilung von Störstellenniveaus E(defect) in der Energie-Bandlücke aufweist, wobei die exponentiell geformte Verteilung von Störstellenniveaus eine niedrigere Konzentration von Störstellenniveaus in der Mitte der Bandlücke und eine höhere Konzentration von Störstellenniveaus an den Rändern der Bandlücke aufweist,
    wobei das Verfahren umfasst, mindestens einen technischen Parameter des P-Kanal-Halbleiterbauelements (10) derart auszuwählen, dass die Inversionsträgerinjektion in die Verteilung von Störstellenniveaus von dem Energieniveau in der Mitte der Bandlücke einer Schicht (13) angrenzend an die Gatedielektrikumsschicht (14) an derselben Seite der Gatedielektrikumsschicht (14) wie die P-Kanal-Schicht (12) mit einem Wert von nicht mehr als 49 % dieser Bandlücke in eV abweicht.
  2. Verfahren nach Anspruch 1, wobei das Auswählen mindestens eines technischen Parameters des P-Kanal-Halbleiterbauelements (10) umfasst, die Dicke der Halbleiter-P-Kanal-Schicht (12) zwischen einigen wenigen Monoschichten und 20 nm auszuwählen.
  3. Verfahren nach Anspruch 2, wobei das Auswählen mindestens eines technischen Parameters des P-Kanal-Halbleiterbauelements (10) umfasst, die Dicke der Halbleiter-P-Kanal-Schicht (12) höher als 3 nm auszuwählen.
  4. Verfahren nach einem der vorhergehenden Ansprüche, wobei die Halbleiter-P-Kanal-Schicht (12) eine Kombination von mindestens zwei halbleitenden Elementen umfasst, wobei eines der halbleitenen Elemente eine kleinere Bandlücke als die anderen aufweist, wobei das Auswählen von technischen Parametern des P-Kanal-Halbleiterbauelements (10) umfasst, die Konzentration in der Halbleiter-P-Kanal-Schicht (12) des halbleitenden Elements mit der kleinsten Bandlücke zwischen 25 % und 99 % auszuwählen.
  5. Verfahren nach Anspruch 4, wobei das Auswählen mindestens eines technischen Parameters der P-Kanal-Halbleiterbauelements (10) umfasst, die Konzentration in der Halbleiter-P-Kanal-Schicht (12) des halbleitenden Elements mit der kleinsten Bandlücke höher als 50 % auszuwählen.
  6. Verfahren nach einem der vorgehenden Ansprüche, wobei das P-Kanal-Halbleiterbauelement (10) eine Halbleiter-Abdeckschicht (13) zwischen der Halbleiter-P-Kanal-Schicht (12) und der Gatedielektrikumsschicht (14) umfasst, wobei das Auswählen von technischen Parametern des P-Kanal-Halbleiterbauelements (10) umfasst, die Dicke der Halbleiter-Abdeckschicht (13) zwischen 0,1 nm und 5 nm auszuwählen.
  7. Verfahren nach Anspruch 6, wobei das Auswählen mindestens eines technischen Parameters des P-Kanal-Halbleiterbauelements (10) umfasst, die Dicke der Halbleiter-Abdeckschicht (12) als 2 nm oder darunter auszuwählen.
  8. P-Kanal-Halbleiterbauelement (10), umfassend eine Halbleiter-P-Kanal-Schicht (12) und eine Steuerelektrode (16) auf der Halbleiter-P-Kanal-Schicht (112), umfassend mindestens eine Gatedielektrikumsschicht (14), wobei die Gatedielektrikumsschicht (14) eine exponentiell geformte Verteilung von Störstellenniveaus E(defect) in der Energie-Bandlücke aufweist, wobei die exponentiell geformte Verteilung von Störstellenniveaus eine niedrigere Konzentration von Störstellenniveaus in der Mitte der Bandlücke und eine höhere Konzentration von Störstellenniveaus an den Rändern der Bandlücke aufweist, wobei das P-Kanal-Halbleiterbauelement (10) eine Inversionsträgerinjektion in die Verteilung von Störstellenniveaus aufweist, die von dem Energieniveau in der Mitte der Bandlücke einer Schicht (13) angrenzend an die Gatedielektrikumsschicht (14) an derselben Seite der Gatedielektrikumsschicht (14) wie die P-Kanal-Schicht (12) mit einem Wert von nicht mehr als 49 % dieser Bandlücke in eV abweicht.
  9. P-Kanal-Halbleiterbauelement (10) nach Anspruch 8, wobei die P-Kanal-Schicht (12) eine Kombination von mindestens zwei halbleitenden Elementen umfasst.
  10. P-Kanal-Halbleiterbauelement (10) nach Anspruch 9, wobei die P-Kanal-Schicht (12) eine SiGe-Schicht ist.
  11. P-Kanal-Halbleiterbauelement (10) nach einem der Ansprüche 8 bis 10, wobei die Dicke der Halbleiter-P-Kanal-Schicht (12) größer als 3 nm ist.
  12. P-Kanal-Halbleiterbauelement (10) nach einem der Ansprüche 9 bis 11, wobei eines der halbleitenden Elemente eine kleinere Bandlücke als die anderen aufweist, wobei die Konzentration in der Halbleiter-P-Kanal-Schicht (12) des halbleitenden Elements mit der kleinsten Bandlücke höher als 50 % ist.
  13. P-Kanal-Halbleiterbauelement (10) nach einem der Ansprüche 8 bis 12, wobei das P-Kanal-Halbleiterbauelement (10) eine Abdeckschicht (13) zwischen der Halbleiter-P-Kanal-Schicht (12) und der Gatedielektrikumsschicht (14) umfasst, wobei die Dicke der Abdeckschicht (13) 2 nm oder darunter ist.
  14. P-Kanal-Halbleiterbauelement (10) nach einem der Ansprüche 8 bis 13, aufweisend ein Sub-1-nm-EOT.
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