Classifications

• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03F—AMPLIFIERS
  • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
  • H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
  • H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
  • H03F3/217—Class D power amplifiers; Switching amplifiers
  • H03F3/2175—Class D power amplifiers; Switching amplifiers using analogue-digital or digital-analogue conversion

Definitions

• the present invention relates to an amplifier device comprising a digital modulator and a power circuit.
• the present invention particularly relates to amplifiers comprising a digital delta-sigma modulator and a class D power circuit.
• Class D amplification has in recent years undergone considerable development due to the need for compact power amplifiers with much higher efficiency than conventional AB class amplifiers, which generally do not exceed 30 dB. %.
• class D amplifier easily offers a 90% efficiency and thus wastes only 10% of the energy it consumes, compared to 70% of energy wasted in an amplifier class AB. This is because class D amplifiers are switching amplifiers operating by switching MOS transistors and thus only consuming power during switching periods.
• FIG. 1A represents a classical amplifier architecture in class D.
• the amplifier comprises a modulator 1 whose input receives a signal to be amplified IS and whose output controls a power circuit PA in class D.
• the output of the circuit of FIG. PA power provides an OS output signal at a LD load, for example a speaker.
• the PA power circuit in class D generally comprises MOSFET transistors arranged according to the "totem pole" assembly. It is a switching circuit that provides a square waveform OS in the form of a voltage slot oscillating between two voltages + Vcc and -Vcc.
• OS square waveform
• the conversion of the OS output signal into an analog audio signal is provided either by means of an LC-type low-pass filter LP arranged between the output of the power circuit PA and the load LD, or by leaving the load filter itself the output signal (mounting said "without filter", or "filterless”).
• class D amplifiers are equipped with PWM pulse width modulators ("Pulse Width Modulation”).
• Others include a delta-sigma modulator providing a pulse density modulated signal or PDM signal (“Puise Density Modulation”).
• a delta-sigma modulator has the advantage of performing noise shaping, which consists in rejecting the quantization noise in the high frequency domain, outside the useful band, through feedback. of the output on the input of the modulator and the prediction of a high sampling frequency relative to the bandwidth of the input signal.
• class D amplifiers In return for their advantageous performance, class D amplifiers generally offer much lower performance than class AB amplifiers.
• a class KB amplifier can easily have a total harmonic distortion (THD) of the order of 90 dB and a signal-to-noise ratio (SNR) of 100 dB.
• THD total harmonic distortion
• SNR signal-to-noise ratio
• a Class D amplifier has difficulty reaching a THD of 40 dB and an SNR of 80 dB.
• the noise shaping performed by the delta-sigma modulator the faults inherent in the power circuit are not suppressed because they are generated downstream of the modulator, and cause a significant increase in the rate of distortion and noise in the signal. Release.
• U.S. Patent 5,777,512 of Tripath Technology discloses a class D amplifier comprising a high frequency delta-sigma modulator operating at high frequency (1.5 MHz).
• the output signal provided by the power circuit is fed back into a state loop of the delta-sigma modulator via an anti-aliasing (anti-aliasing) filter and a continuous time gain circuit.
• anti-aliasing anti-aliasing
• delta-sigma modulators with continuous time or discrete time pose problems of stability with architectures of order higher than 2. Or, one can hardly hope to obtain performances comparable to those of class KB amplifiers with a delta-sigma modulator of order 1 or 2, unless a modulator of great complexity and costly to implement.
• FIG. 1B shows a classical architecture of digital delta-sigma modulator 1.
• the modulator 1 is here of order 3 and comprises three delta-sigma stages DSa, DSb, DSc and a quantizer QT.
• the delta-sigma stages each comprise an input semiconductor Sa, Sb, Sc whose output attacks an integrator ITa, ITb, ITc.
• the positive input of the summator Sa of the delta-sigma stage DSa receives the input signal IS
• the positive input of the summator Sb of the delta-sigma stage DSb receives the output of the integrator ITa
• the input positive of the summator Sc of the delta-sigma stage DSc receives the output of the integrator ITb.
• the integrator ITc provides the quantizer with an NSS signal and the quantizer QT provides a quantized signal QS.
• the signal QS is sent back to the negative input of the summator Sa via a state loop SLa, on the negative input of the summator Sb via a state loop SLb, and on the negative input of the summator Sc via a state loop SLc.
• the quantization noise is conventionally formatted by applying to the integrators ITa, ITb, ITc a clock signal having a frequency Fs much greater than the bandwidth of the input signal IS, generally greater than the Megahertz for an audio signal in the 30Hz-20KHz band.
• the Quantized signal QS is applied to the power circuit PA.
• the latter provides the OS output signal oscillating between + Vcc and -Vcc which is applied to the load LD, possibly via a LPF low-pass filter.
• a major challenge in the realization of a digital amplifier is to correct the defects introduced into the output signal OS by the power circuit PA. Such defects are called “non-idealities" and generate distortion and noise.
• the technique generally used consists of returning an error signal in the delta-sigma modulator.
• This error signal is for example elaborated by calculating a difference between an ideal slot and the slot provided by the power circuit PA.
• US Pat. No. 6,373,334 describes, in relation with FIGS. 2A, a digital delta-sigma modulator whose delta-sigma stages receive two types of feedback signals, namely a signal taken at the output of the quantizer ("a priori feedback ") and an error signal (" real time feedback ”) which is previously converted into a digital signal by an analog-digital converter.
• the error signal is generated by comparing the signals provided by the power circuit when connected to a load, to "ideal" signals provided by reference switches that simulate the ideal operation of the power circuit at the same time. no load.
• Audio codecs compression-decompression circuits
• Audio codecs generally include, on the same semiconductor chip, one or more amplifiers, analog-to-digital converters for converting analog external signals to digital signals, and signal processing or DSP processors for converting to amplifiable audio signals. digital audio data received or read in compressed or encoded form and vice versa. It may be desired to improve the structure of these codes to reduce their complexity and cost.
• digital modulators generate a quantization or sampling noise that is constant and independent of the signal, and which depends on the quantization or sampling step and the quantization or sampling frequency. Although this noise is of the order of the least significant bit of the modulated signal, its impact on the signal-to-noise ratio is all the more important that the signal is weak. It may thus be desirable to provide for technique to reduce the influence of noise on low amplitude signals.
• An embodiment of the present invention relates to an amplifier device comprising a digital modulator receiving a digital input signal and introducing a noise component into a signal it provides, and means for applying a gain to the input signal or to a signal coming from the input signal and passing through the modulator, when the amplitude of the input signal is below a threshold, so as to increase the signal-to-noise ratio between the output signal of the device and the noise component introduced by the modulator.
• the amplifier device comprises a circuit for monitoring the amplitude of the input signal and providing a gain activation signal when the amplitude of the input signal is below the threshold.
• the amplifier device comprises means for applying a reverse gain downstream of the modulator when the amplitude of the input signal is below the threshold, so that the overall gain of the amplifier device is unchanged.
• the means for applying a reverse gain downstream of the modulator comprise a converter configured to convert a signal supplied by the modulator into an RTZ signal whose duty cycle is divided by the gain.
• the modulator is a digital delta-sigma modulator comprising delta-sigma stages, a quantizer receiving a signal provided by a delta-sigma stage and providing a quantized signal forming the modulated signal, and the device comprises a circuit for supplying the output signal to an electrical load, and means for, when the amplitude of the input signal is less than the threshold: applying the gain to the signal supplied to the quantizer, and applying a reverse gain to a signal of control of the power circuit which is a function of the quantized signal.
• the quantizer is configured to provide a quantized coded thermometer signal.
• the amplifier device comprises a circuit for monitoring the amplitude of the input signal and providing a gain selection signal having an active value when the amplitude of the input signal is lower than said threshold, a gain circuit for applying the gain to the signal supplied to the quantizer when the gain selection signal has the active value, and a circuit for driving the power circuit, providing the control signal of the power circuit and configured to apply a reverse gain to the control signal when the gain selection signal has the active value.
• the circuit for driving the power circuit comprises a converter RTZ receiving the quantized signal and supplying the power circuit with a coded control signal RTZ whose duty cycle is a function of the amplitude of the quantized signal, and the The RTZ converter is configured to divide the duty cycle of the control signal by the gain when the control signal has the active value.
• the delta-sigma modulator comprises M delta-sigma stages each comprising a state loop, M being at least equal to 3, and the amplifier device comprises: N state loops of a first type, configured to return the output signal to summators of N lower-order delta-sigma stages, with N at least 1, each state loop of the first type including an analog low-pass filter for filtering the output signal and providing a filtered output signal, an analog-to-digital converter for converting the filtered output signal into a digitized filtered output signal; and M-N status loops of a second type, configured to return the quantized signal to summators of M-N higher-order delta-sigma stages.
• the amplifier device comprises nonlinear stabilization elements arranged in all or part of the delta-sigma stages.
• the power circuit is connected to or intended to be connected to the load without the interposition of a low-pass filter, and the low-pass filter of the first type of state loops is arranged between the load and the analog-digital converter.
• the low-pass filter is disposed between the power circuit and the load.
• the power circuit is a class D amplifier with symmetrical or non-symmetrical configuration.
• FIGS. 1A and 1B previously described, represent the classical architecture of a digital amplifier
• FIGS. 2A to 2D show embodiments of amplifiers according to the first refinement of the invention, of the type without an output filter
• FIGS. 3A to 3C show embodiments of amplifiers according to the first improvement of FIG. of the output filter type
• FIG. 4 shows in more detail an embodiment of the amplifier shown in FIG. 2C
• FIGS. 5A and 5B show exemplary embodiments of an integrator and a quantizer represented in the form of blocks in FIG. 4;
• FIG. 6 represents an exemplary embodiment of an RTZ converter represented in block form in FIG. 4,
• FIGS. 7A, 7B are timing diagrams illustrating the operation of the converter shown in FIG. 6;
• FIGS. 8A, 8B show two exemplary embodiments of a power circuit represented in the form of a block in FIG. 4;
• FIGS. 9A, 9B are tables illustrating the conversion of RTZ control signals into output signals provided by the power circuits represented in FIGS. 8A, 8B;
• FIG. 10 represents an exemplary embodiment of a level quantizer; multiple output,
• FIG. 11 represents an exemplary embodiment of a converter RTZ with multiple modulation levels
• FIGS. 12 and 13 show exemplary embodiments of audio codecs according to the second improvement of the invention
• FIG. 14A is a diagram of a conventional digital delta-sigma modulator and FIG. 14B the diagram of an embodiment of a delta-sigma modulator according to the third improvement of the invention,
• FIG. 15 represents an embodiment of an amplifier according to the third improvement of the invention.
• FIG. 16 represents an embodiment of a gain unit represented in block form in FIG. 15;
• FIG. 17 shows a first embodiment of a variable gain RTZ converter represented in block form in FIG. 15;
• FIGS. 18A to 18C are timing diagrams illustrating the operation of the converter of FIG. 17;
• FIG. 19 represents another embodiment of a variable gain RTZ converter represented in block form in FIG. 15,
• FIGS. 20A to 20C are timing diagrams illustrating the operation of the converter of FIG. 19,
• FIG. 21 represents yet another embodiment of a variable gain RTZ converter represented in block form in FIG. 15,
• FIG. 22 represents an embodiment of an amplifier implementing the first and third improvements of the invention.
• the present invention provides three improvements applicable to amplifiers comprising a delta-sigma type digital modulator, the third improvement being more generally applicable to amplifiers comprising a digital modulator regardless of its type, since the modulator behaves like a source of noise. constant.
• each improvement is in itself independent of the other and the improvements can thus be implemented independently or in combination.
• FIGS. 2A, 2B, 2C, 2D represent embodiments of amplifiers according to the first improvement, designated respectively A2, A3, A4, A5.
• These amplifiers each comprise a delta-sigma modulator 2 (FIG 2A), 3 (FIG 2B), 4 (FIG 2C), 5 (FIG 2D) and a power circuit PA connected to a load LD, for example a speaker.
• the power circuit PA is a class D amplifier circuit.
• conventional continuous-time or capacitance delta-sigma modulators pose development difficulties for orders greater than 2, because of the stability problems that appear from the order 3, so that high performance in terms of THD
• total harmonic distortion or SNR (signal-to-noise ratio) can be difficult to achieve, or at the cost of unacceptable complexity.
• the amplifiers according to the first improvement A2, A3, A4, A5 all comprise an entirely numerical delta-sigma 2, 3, 4, 5 modulator of order greater than or equal to 3 and generally of order "M" with M at less than 3.
• each delta-sigma modulator 2, 3, 4, 5 is of order 5 and has 5 delta-sigma stages DS1, DS2, DS3, DS4, DS5, five loops of state SL1, SL2, SL3, SL4, SL5 as well as a quantizer QT1.
• the lower-rank delta-sigma stage DS1 receives the input signal IS from the amplifier and the higher-order delta-sigma stage DS5 supplies the quantizer QT1 with an NSS signal.
• the quantizer QT1 provides a quantized signal QS to the power circuit PA.
• Each delta-sigma modulator 2 to 5 is clocked by an oversampling clock signal of frequency Fs much greater than the bandwidth of the signal IS, for example 4 MHz.
• the signal IS is a digital signal, for example a 30Hz-20kHz bandwidth audio signal provided by a digital audio processor of the DSP type (not shown) and coming from a musical signal source such as a CD, a radio station, a MP3 file ...
• a DCTl driver circuit described below, can be provided between the quantizer QT1 and the power circuit PA.
• Each delta-sigma stage DS1, DS2, DS3, DS4, DS5 comprises in a conventional manner an adder, respectively Sl, S2, S3, S4, S5, whose output is applied to an integrator, respectively IT1, IT2, IT3, IT4, IT5.
• Each adder includes at least one positive input and one negative input.
• Each positive and negative input of an adder may have a gain, schematized in FIG. 2A by gain units placed on the positive and negative inputs of the summers.
• the positive input of the adder Sl of the delta-sigma stage DSl has a gain g11 and its negative input has a gain gl2
• the positive input of the adder S2 of the delta-sigma stage DS2 has a gain g21 and his entry negative has a gain g22, and so on until the caremateur S5 whose positive input has a gain g5l and the negative input a gain g52.
• the summator S1 receives the signal IS on its positive input, its negative input is connected to the state loop SL1 and its output is applied to the integrator IT1.
• the summator S2 has its positive input connected to the output of the integrator IT1, its negative input connected to the state loop SL2 and its output applied to the integrator IT2.
• the processor S3 has its positive input connected to the output of the integrator IT2, its negative input connected to the state loop SL3 and its output applied to the integrator IT3;
• the summator S4 has its positive input connected to the output of the integrator IT3, its negative input connected to the state loop SL4 and its output applied to the integrator IT4.
• each delta-sigma modulator 2, 3, 4, 5 carries out a noise shaping that integrates the non-idealities (distortion, noise, ...) generated by the power circuit PA . More particularly, this formatting of the non-idealities of the output signal OS is obtained thanks to the low rank status loops which return the output signal OS in lower-order delta-sigma stages via a LPFl analog low-pass filter and an ADC analog-to-digital converter. In the embodiments shown in FIGS.
• one or more digital filters are also provided between the analog-to-digital converter ADC and the lower-order delta-sigma stages.
• the output signal OS is returned to the lower rank state loop SL1 via the LPF1 low pass filter, the ADC converter and a digital pass filter. down DFl.
• the filter LPF1 provides a filtered output signal FOS.
• the ADC provides a DFOS digitized filtered output signal.
• the digital filter DF1 supplies the negative input of the summator S1 with a filtered filtered filtered output signal FDFOS1.
• the output signal OS is thus filtered twice, on the one hand in the analog domain and on the other hand in the digital domain, before being applied to the negative input of the summator S1 of the delta-sigma modulator 2.
• the output signal OS is returned in the two lower-order state loops SL1, SL2 by via the filter LPF1, the converter ADC, the digital filter DF1 arranged in the state loop SL1 and a digital low-pass filter DF2 arranged in the state loop SL2.
• the filter LPF1 provides the filtered output signal FOS
• the converter ADC provides the filtered output signal DFOS
• the digital filter DF1 provides the negative input of the adder S1 the filtered filtered output signal FDFOS1
• the digital filter DF2 supplies the negative input of the adder S2 with a filtered filtered filtered output signal FDF0S2.
• the output signal OS is returned in the three lower-ranking state loops SL1, SL2, SL3 via the filter LPF1, the converter ADC, the digital filter DF1. arranged in the state loop SL1, the digital filter DF2 arranged in the state loop SL2 and a digital low-pass filter DF3 arranged in the state loop SL3.
• the filter LPF1 provides the filtered output signal FOS
• the converter ADC supplies the digitized filtered output signal DFOS
• the digital filter DF1 supplies the negative input of the adder S1 with the filtered filtered output signal FDFOS1.
• the digital filter DF2 supplies the negative input of the adder S2 with a filtered filtered filtered output signal FDF0S2 and the digital filter DF3 supplies the negative input of the adder S3 with a filtered filtered filtered output signal FDF0S3.
• the output signal OS is returned in the three lower rank status loops SL1, SL2, SL3 through the filter LPF1, the ADC and a filter digital low-pass DFC common to the three status loops SL1, SL2, SL3.
• the filter LPF1 provides the filtered output signal FOS
• the converter ADC provides the digitized filtered output signal DFOS
• the common digital filter DFC supplies the negative inputs of the summers S1, S2, S3 a filtered filtered filtered output signal common FDFOSC .
• this filter LPF1 is designed to simulate the impedance of the load LD between its input and its output, ie an electroacoustic transducer impedance in the case of a load LD type loudspeaker.
• the analog electrical signal FOS supplied by the LPF1 filter to the ADC converter is the image of the signal that animates the speaker's membrane and is therefore the image of the acoustic signal that the user hears. It contains all the audible imperfections that we want to correct.
• the filter LPF1 is preferably an RC filter which can be integrated with the rest of the amplifier on a semiconductor chip, the use of an LC filter being desirable in this embodiment because it would require the prediction of a self-inductance whose integration on a semiconductor substrate would be prohibitive because of its dimensions.
• the integration of the non-idealities into the noise shaping process is performed in a manner that differs from the known techniques, by means of feedback of the OS output signal in its entirety in the loops. state of lower order delta-sigma stages SL1 (Fig. 2A), SL1 and SL2 (Fig. 2B) or SL1, SL2 and SL3 (Fig. 2C and 2D) via LPFl low-pass filter , which simulates the impedance of the LD load and is not comparable to a conventional anti-aliasing filter, the ADC and digital filters.
• the other status loops receive the quantized signal QS, the latter being applied on the negative inputs of the corresponding summators S2 to S5 (Fig. 2A), S3 to S5 (Fig. 2B) or S4 and S5 (Fig. 2C and 2D).
• the filter LPF1 preferably has a cut-off frequency at -3 dB of the order of 5 to 10 times the cut-off frequency at -3 dB of the input signal (IS), a frequency of cut on the order of 100 to 200 kHz if the input signal IS has a cut-off frequency at -3 dB of the order of 20 kHz.
• Tests carried out with an LPF1 filter having a cut-off frequency of the order of 100 kHz have, for example, given excellent results in terms of total harmonic distortion THD and signal-to-noise ratio SNR.
• the ADC converter is a fast converter clocked by a sampling frequency Fc greater than or equal to twice the sampling frequency Fs of the delta-sigma modulator.
• the ADC converter can for example be a fast converter type MASH ("Multi-Stage noise shaping") or equivalent.
• the ADC may be a switched capacitor converter or a continuous time converter. It should be noted that in the case where the ADC converter is a continuous-time converter, the action of the low-pass filter LPF1 can be provided by the converter itself. In other words, the ADC converter and the LPF1 filter form, in this case, one and the same element.
• the filters DF1, DF2, DF3 or DFC can be HR Chebyschev type II filters ("Infinity Impulse Response" or infinite impulse response filters).
• the digital filters DF1, DF2, DF3, DFC have a complementary action on the stability of the delta-sigma modulator and the obtaining of an amplifier which presents high performances in terms of THD and SNR.
• This complementary action is desirable in certain embodiments, when the ADC converter operates at a higher frequency than the sampling frequency Fs of the delta-sigma modulator, for example when the sampling frequency Fc is greater than or equal to twice the sampling frequency Fs.
• the following examples are provided in a non-limiting manner:
• the LPFl low-pass filter is a first-order analog filter with a cut-off frequency of -3 dB of 200 kHz;
• the ADC converter is a PEM type converter (with Pulse Density Modulation), for example of commercial reference AD7720, having 1 output bit and comprising a delta-sigma converter of order 5, 6 or 7, clocked at a frequency Fc of 12 MHz in order to increase the signal-to-noise ratio SNR of the converter in the audio band, while the sampling frequency Fs of the delta-sigma modulator is 6 MHz;
• the digital filter (s) are Type II and 5, 6 or 7 Type II Chebyschev HR filters, including a 28 bit bus, providing a fairly wide bandpass frequency, for example 2 MHz, and a frequency stop-band at -8OdB which is preferably equal to or close to half of the operating frequency of the ADC converter, for example a frequency of the order of 3 to 4
• the digital filters DF1-DF3, DFC preferably used under the conditions specified above ensure, in addition to a quantization noise softening function of the ADC analog-to-digital converter, a signal nonlinearity correction function.
• the output signal OS present in the signal DFOS, before it is applied to the delta-sigma modulator 2, 3, 4, 5.
• a cutoff frequency too low or too high leads to instability of the modulator.
• the digital filters have a cut-off frequency at -3 dB at least 4 times greater than the cut-off frequency at -3 dB LPFl filter.
• the lower rank digital filter namely the filter DF1 of the amplifiers A2, A3, A4 or the common filter DFC used in the amplifier A5 may have a cut-off frequency at -3 dB of 500 kHz.
• the DF2 filter may have a cut-off frequency of -3 dB of 500 kHz (Fig. 2B, 2C) and the DF3 filter may have a cut-off frequency of -3 dB of 1.5 MHz (Fig. 2C).
• the digital filter of lower rank DF1 or DFC must moreover preferably have a band stop frequency at 120 dB of the order of half the bandwidth of the delta-sigma modulator, ie of the order of Fs / 2 here 2 MHz.
• their attenuation at the frequency Fs / 2 should preferably be greater than the signal / noise characteristic targeted, for example be at least equal to 100 dB. Mnsi, for example, an attenuation of 80 dB would not achieve a SNR of 100 dB.
• the digital filters DF2 and DF3 acting on second and third order delta-sigma stages are less critical for the stability and the performances of the modulator and can present at the frequency Fs / 2 an attenuation of the order of 80 dB and 60 dB, respectively, instead of 120 dB (Fig. 2B and 2C).
• the digital filters DF1-F3, DFC may also be high-pass filters, for example first-order high-pass filters intended to correct the pole introduced by the analog low-pass filter preceding the ADC converter.
• a combination of low-pass and high-pass digital filters may also be provided in order to provide better stability to the state loop.
• Embodiments which have just been described relate to a so-called "filterless" amplifier whose PA power circuit directly attacks the load LD.
• Embodiments of the invention may also relate to amplifiers whose PA power circuit drives the load through an output filter. In this case, it is not necessary to simulate the impedance of the load LD by means of the filter LPF1, since the filtered signal applied to the load is already an analog signal that the load is supposed to faithfully reproduce.
• FIGS. 3A, 3B, 3C show embodiments of amplifiers A6, A7, A8 which are connected to the load LD via a LPF2 low-pass filter.
• This filter is conventionally an LC filter comprising a large coil which is external to the semiconductor wafer receiving amplifier A6, A7 or A8.
• the various embodiments described here can also be realized with components discrete mounted on an interconnection circuit (printed circuit, thin film circuit, etc.).
• the amplifier A6 shown in Figure 3A has the same structure as the amplifier A2 shown in Figure 2A and will not be described in detail. It differs only from the amplifier A2 in that the state loop SL1 only comprises the ADC converter and the digital filter DF1, the LPF1 low-pass filter being suppressed. The analog signal FOS is taken directly at the output of the filter LPF2, ie at the terminals of the load LD, to be applied to the ADC converter.
• Amplifier A7 shown in FIG. 3B has the same structure as amplifier A3 shown in FIG. 2B. It differs only from the amplifier A3 in that the state loops SL1, SL2 include only the ADC converter and the digital filters DF1, DF2, the LPF1 low-pass filter being removed. The analog signal FOS is as previously taken at the output of the filter LPF2, across the load LD, to be applied to the ADC converter.
• the amplifier A8 shown in Fig. 3C has the same structure as the amplifier A4 shown in Fig. 2C. It differs only from the amplifier A4 in that the state loops SL1, SL2, SL3 comprise only the ADC converter and the digital filters DF1, DF2, DF3, and therefore do not include the LPF1 low-pass filter.
• the analog signal FOS is as previously taken at the output of the filter LPF2.
• the delta-sigma modulator used to carry out any of the amplifiers A2 to A8 previously described comprises non-linear stabilization means, in order to prevent the amplitude of the digital signal processed by the modulator reaches a saturation threshold.
• These non-linear stabilizing elements are arranged in all or part of the delta-sigma stages and are configured to prevent amplitude saturation of the modulator.
• each delta-sigma stage DS1, DS2, DS3, DS4, DS5 comprises a nonlinear stabilization means, respectively NLS1, NLS2, NLS3, NLS4, NLS5.
• Such stabilization means are in themselves known and described in the literature.
• a delta-sigma modulator behaves like a nonlinear system which is difficult to model accurately by equations from order 3.
• the stabilization of the modulator can only be done by means of stabilization techniques having a character experimental and using simulation software.
• the application of these techniques to an amplifier of the type just described advantageously makes it possible to produce an amplifier having a high order delta-sigma modulator while solving modulator stability problems.
• FIG 4 shows in more detail an embodiment of the amplifier A4 shown in Figure 2C.
• Each integrator IT1 to IT5 has inputs II, 12 and an output 01.
• the positive input of the adder S1 receives the input signal IS via the gain unit g11.
• the output of the summator S1 is applied to the input II of the integrator IT1 whose output Ol is connected to the positive input of the adder S2 via the gain unit g21.
• the output of the summator S2 is applied to the input II of the integrator IT2 whose output 01 is connected to the positive input of the summator S3 via the gain unit g31.
• the output of the summator S3 is applied to the input II of the integrator IT3 whose output 01 is connected to the positive input of the summator S4 via the gain unit g41.
• the output of the summator S4 is applied to the input II of the integrator IT4 whose output 01 is connected to the positive input of the summator S5 via the gain unit g51.
• the output of the summator S5 is applied to the input II of the integrator IT5 whose output 01 is connected to a positive input of an adder S6 whose output supplies the signal NSS applied to the quantizer QT1.
• Each integrator IT1 to IT5 comprises a summator S7 with two positive inputs, a delay circuit UD1 clocked by the frequency clock signal Fs and performing the function 1 / z in the domain z, and a multiplier M1 whose output forms the output 01 of the integrator.
• the input II is connected to an input of the adder S7 whose other input is connected to the output 01 of the integrator.
• the output of the summator is applied to the delay circuit UD1 whose output is applied to an input of the multiplier M1.
• the other input of the multiplier M is connected to the input 12 of the integrator.
• the highest-ranking integrator IT5 furthermore has an output 02 providing a signal / RST for resetting the lower-order integrators IT1 to IT4.
• the output of the delay circuit UD1 is applied to an ABS module whose output provides the absolute value
• ABS1 is applied to the input of a threshold detector RO1 produced here as a hysteresis relay.
• the output of the relay RO1 forms the output 02 of the integrator and supplies the signal / RST.
• the threshold detector RO1 sets the signal / RST to 0.
• the output 02 of the integrator IT5 is thus connected to the inputs 12 of the integrators IT1 to IT4 as well as to the own input 12 of the integrator IT5.
• the transition to 0 of the signal / RST causes the multipliers M1 present in the integrators IT1-IT4 to be zeroed (FIG.5A) and consequently resets the outputs 01 of the integrators.
• the integrators IT1-IT5 and the s ⁇ r ⁇ mados S1-S5 preferably work on a numerical scale of N2 bits greater than the number of bits N1 of the input signal IS, for example 24 bits if the input signal is encoded on 16 bits.
• the loops SZO comprise a gain unit SAO receiving the input signal IS and whose output sends the signal IS on a second positive input of the adder S6, on a second positive input of the adder S5, on a second positive input of the summator S4, on a positive input of a summator SS1 whose output is connected to a second positive input of the summator S3 and on a second positive input of the summator S2.
• the loop SZ1 comprises a gain unit SA1 whose input is connected to the output of the gain unit g51 and the output of which is connected to a second positive input of the adder SS1.
• the loop SZ2 comprises a gain unit SA2 whose output is connected to a second positive input of the summator S1.
• the ADC converter is clocked by a clock signal whose frequency Fc and at least twice the sampling frequency Fs.
• the digital filters are clocked by the same frequency clock signal Fc and their outputs are downsampled by means of sample-and-hold circuits SH1, SH2, SH3 ("Sample-Hold") operating at the frequency Fs.
• the quantizer QT1 can be a 1-bit quantizer conventionally providing an output signal of +1 or -1. According to an optional but advantageous aspect of the first improvement, the QT1 quantizer has several output levels and provides a quantized QS signal encoded on N3 bits. In this case, a driver circuit DCT1 is provided between the quantizer QT1 and the power circuit PA in order to supply the latter with appropriate control signals from the multilevel quantized signal.
• FIG. 5B An exemplary embodiment QTI1 of a multilevel quantizer is shown in FIG. 5B.
• the quantizer has 5 output levels -1, -0.5, 0, +0.5, +1 in positive and negative values, ie 2 different levels of 0 in absolute value, 0.5 and 1.
• the quantizer is asynchronous and has 4 threshold detectors R21, R22, R23, R24 in the form of hysteresis relays
• the inputs of the relays are connected to the input (IN) of the quantizer.
• the output of each relay goes to 1 when the signal received by the relay input (here the signal NSS) is greater than the value of its detection threshold.
• the outputs of the relays are applied to a four-input adder MS1 whose output is divided by 4 by means of a gain unit having a gain of 1/4, the output of the gain unit forming the output (OUT ) of the quantizer QTlI.
• the quantizer provides a thermometer code, encoded for example as follows:
• N3 the number of bits of the QS coding, is also equal to the number of quantization thresholds used (R21, R22, R23 and R24).
• the pilot circuit DCT1 which receives the quantized multi-level signal QS is an RTZ converter RM1 (RTZ being the acronym for "Return To Zero" used to designate a signal returning to zero).
• the converter RM1 provides a signal RTZS1 comprising pulses passing through zero and having a variable duty cycle which is a function of the value of the quantized signal.
• the converter RM1 receives on an input II the signal NSS supplied by the delta-sigma stage DS5 and on an input 12 the quantized signal QS.
• An embodiment RM1 of the converter RM1 is shown in FIG.
• This embodiment is intended to be associated with the output level quantizer shown in FIG. 5B.
• the converter RM10 comprises a threshold detector R02 in the form of a hysteresis relay, an absolute value module ABS2, a multiplexer MUX1, a decoder DECl, a signal generator RTZ RGEN1 receiving a signal of frequency 2Fs, and a multiplier MTO.
• the relay R02 here has a detection threshold equal to 0. Its input forms the input 12 of the converter RM10 and thus receives the signal NSS. Its output provides a SIGN signal applied to an input of the MTO multiplier. The signal SIGN is equal to +1 when the signal NSS is positive and -1 when the signal NSS is negative.
• the generator RGEN1 is a frequency divider logic which provides an RTZ RS signal (1/2) having a duty ratio of 0.5.
• the multiplexer MUX1 comprises three inputs receiving respectively the logic "0", the signal RS (1/2) and the logic "1".
• the logical "1" corresponds to an RTZ signal having a duty cycle of 1 (ie a signal continuously at 1) and the logical "0" corresponds to an RTZ signal having a zero duty cycle (being continuously 0).
• the output of the multiplexer MUX1 copies one of the inputs of the multiplexer and supplies an RS signal which is applied to a second input of the multiplier MT.
• the signal RS is an NRZ signal having a zero duty cycle if the logic 0 is selected by the multiplexer, a duty ratio of 0.5 if the signal RS (1/2) is selected, or 1 if the logic "1" is selected.
• the selection of the input of the multiplexer is ensured by the decoder DECl which receives the absolute value
• the duty ratio of the signal RS is a function of the value of
• the signal RTZS1 is identical to the signal RS with the polarity, and has a negative value when the signal SIGN is equal to -1.
• the signal RTZS1 has a zero duty cycle when
• the RTZS1 signal thus obtained whose cyclic ratio modulations reflect the different values of the multilevel quantized signal, is applied to the power circuit PA which is configured to transform the signal RTZS1 into a pulse width modulated OS output signal and presenting three voltage levels + Vcc and -Vcc and 0.
• FIG. 8A schematically represents an embodiment of the power circuit PA.
• the circuit PA here comprises a power circuit PA1 in a non-symmetrical configuration ("single ended"), generally called “half-bridge".
• the stage PA1 comprises for example two MOSFET power transistors in series, according to the so-called “totem pole” assembly, where the output node is sampled between the two transistors.
• These power transistors are generally oversized and occupy a large area in a semiconductor chip. They are controlled by signals SW1, SW2 provided by an adaptation logic circuit ADCT1 receiving the signal RTZS1.
• the conversion of the RTZS1 signal into an OS output signal is made according to the following table, which is also shown in FIG. 9A:
• This conversion is a conversion in voltage only (1 being converted into + Vcc and -1 to -Vcc) and the variation fronts of the output signal OS are identical to the variation edges of the signal RTZS1, so that the signal OS has the same value. same duty cycle as the RTZSl signal.
• FIG. 8B schematically shows another embodiment of the power circuit PA.
• the circuit PA here comprises two power stages PA1, PA2 arranged in symmetrical mode ("balanced"), this assembly being generally called “complete bridge”.
• Each power circuit PA1, PA2 comprises, for example, two MOSFET transistors in “pole totem”, and is driven by signals SW3, SW4, respectively SW5, SW6, provided by an adaptation logic circuit ADCT2 receiving the signal RTZS1.
• the stage PA1 provides an output signal OS1 at a first terminal of the load LD and the stage PA2 provides an output signal 0S2 at a second terminal of the load LD.
• the conversion of the RTZS1 signal into output signals OS1, 0S2 is made according to the following table, also shown in FIG. 9B:
• the variations of the output signal OS are the image of the variations of the signal RTZS1, so that the signal OS has the same variations in duty cycle as the signal RTZS1.
• the signal OS is symmetrical, that is to say formed by the difference between the two output signals OS1, 0S2
• the return of the signal OS in the state loop SL1 or in the state loops SL1 and SL2 or SL1, SL2 and SL3 of the delta-sigma modulator can be made by means of two filters LPFIa, LPFIb instead of the single filter LPF1 previously described, as shown in FIG. 8B.
• Each filter LPFIa, LPFIb is referenced to the ground of the circuitry and filters one of the output signals OS1, 0S2.
• the LPFIa, LPFIb filters provide analog signals FOSa, FOSb that are applied to an ADIF analog differential amplifier whose output provides the FOS signal applied to the ADC analog-to-digital converter.
• the RTZ modulation control of the power circuit PA offers the advantage of substantially improving its efficiency. It is thus possible to aim at a yield of the order of 95 to 99% instead of the 90% generally obtained with an output signal OS which varies between the two extremes + Vcc and -Vcc without presenting the zero value modulation plateau.
• the delta-sigma modulator can generally be designed to the order M with M at least equal to three, and the number of lower-order delta-sigma stages involved in the shaping of the non-idealities of the signal.
• OS output is not necessarily limited to 1, 2 or 3 delta-sigma stages. It is up to the designer, in light of the teaching that has been disclosed, to define the final architecture of the amplifier according to the specifications and performance targets.
• the multilevel quantizer can be made to the order "n", denoting by n the number of quantizer detection thresholds corresponding to the number of threshold detectors used in the embodiment shown in Fig. 5B.
• FIG. 10 represents a quantizer QT12 having "n” detection thresholds, "n” being here an even number (an odd number of thresholds can also be provided).
• the quantizer thus comprises “n” relays designated “R (threshold)” having respective switching thresholds of - (nl) / n, - (n-3) / n, ..., - 1 / n, 1 / n , ..., (n-3) / n, (nl) / n.
• a converter RTZ RM100 having n + 1 duty cycle is provided, as illustrated in FIG. 11.
• the converter RM100 is distinguished from the converter RM10 previously characterized in that it comprises a signal generator RGEN2 mounted as a frequency divider receiving a signal of frequency nFs / 2.
• the generator RGEN2 provides RTZ signals designated "RS (duty ratio)" in Fig. 11 and having duty ratios equal to 2 / n, 4 / n, 6 / n, ..., (n-2k) / n, ..., (n-2) / n.
• the multiplexer MDX1 is replaced by a multiplexer MUX2 having a sufficient number of inputs to select one of these various RTZ signals, and a decoder DEC2 to drive the multiplexer from the signal QS n + 1 levels.
• the multiplexer MUX2 receives the value 1, forming a duty ratio signal equal to 1, and the value 0, forming a zero duty cycle signal.
• Second improvement As has been indicated in the preamble, it is known to produce an audio codec comprising on the same semiconductor chip one or more amplifiers, analog-digital converters, and signal processing processors or DSPs for converting to amplifiable audio signals of digital audio data received or read in compressed or encoded form and vice versa.
• FIG 12 is a partial view of an exemplary embodiment of an audio codec AC1 comprising amplifier A4 previously described ( Figure 2C).
• the audio codec AC1 comprises, in addition to the amplifier A4, processors DSP1, DSP2, an analog multiplexer AMUX controlled by a selection signal C1 and having at least two inputs E1, E2 and an output S1, and a digital demultiplexer DMUX. controlled by a selection signal C2 and having an input El and at least two outputs S1, S2.
• the processor DSP1 supplies the signal IS to the amplifier A4 from an audio signal Rx, for example a signal received or read in a digital audio medium (MP3 file, CD, DVD, etc.).
• the input E1 of the multiplexer AMUX is connected to the output of the filter LPF1 of the amplifier A4 and thus receives the signal FOS when the amplifier is active.
• the input E2 of the AMUX multiplexer is connected to a source of an external audio signal ES via an anti-aliasing filter AAF.
• the source of the external audio signal ES is for example an MC microphone.
• the Sl output of the AMUX multiplexer is connected to the input of the analog-digital converter ADC and the output of the ADC converter is applied to the input E1 of the DMUX demultiplexer.
• the output Sl of the DMUX demultiplexer is applied to the input of the digital filters DF1, DF2, DF3 of the state loops SL1, SL2, SL3 of the amplifier A4.
• the output S2 of the demultiplexer DMUX is connected to a port of the processor DSP2.
• the selection signals C1, C2 make it possible to select the inputs E1, E2 of the multiplexer AMUX and the outputs S1, S2 of the demultiplexer DMUX as follows: 1) When the A4 amplifier is active, the input El of the AMUX multiplexer is selected and the output Sl of the EMOX demultiplexer is selected. The signal FOS is thus applied to the ADC converter and the digital signal DFOS supplied by the converter ADC is applied to the digital filters DF1, DF2, DF3 of the amplifier A4. This works as if the elements AMUX and DMDX were not present.
• the input E2 of the AMUX multiplexer is selected and the output S2 of the DMDX demultiplexer is selected.
• the signal ES is thus applied to the ADC converter which provides an external digitized signal DES, which is sent to the processor DSP2 for processing, for example compression or recording.
• the DSP2 processor may also send the DES signal to another amplifier embedded in the same semiconductor substrate (not shown).
• FIG. 12 is only a partial view of an audio codec that can be produced according to the second improvement of the invention.
• at least one analog-digital converter is available at each moment for digitizing an external signal and at least one amplifier for amplifying an internal audio signal or the audio signal. external digitized by the converter of another amplifier present in the audio codec.
• Fig. 13 is another example of an audio coding performed here with amplifier A8 previously described (Fig. 3C).
• the amplifier A8 differs from the amplifier A4 in that the LPF2 low-pass filter arranged between the power circuit is used as a low-pass filter in the state loops SL1, SL2, SL3 of the amplifier A8. .
• the filtered analog signal FOS as applied to the load LD is directly applied to the input E1 of the AMDX multiplexer.
• this second improvement according to the invention is, because of its very nature, independent of the first improvement. It can indeed be implemented with any type of amplifier including an analog-digital converter, for example the amplifier described by the patent 6,373,334.
• quantization noise is a constant that depends only on the quantization step g, called quantum. It comes that the report between the quantization noise and the signal is all the more important that the signal is weak.
• Non-linear quantization techniques such as semi-logarithmic quantization make it possible to vary the quantization step as a function of the intensity of the signal, the semi-logarithmic quantization step being all the smaller the lower the intensity of the signal. . Such techniques may however be complex to implement and it may be desired to decrease the signal-to-noise ratio in another way. It will be noted that this objective is independent of noise shaping by a delta-sigma modulator.
• the noise shaping considerably reduces the signal-to-noise ratio for a given quantization noise, but the result obtained nevertheless depends on the initial quantization noise.
• An idea on which this third improvement is based is to increase the amplitude of the signal when it is low, so that the ratio between this signal and the quantization noise is lower.
• 14A is the block diagram of a first-order elementary delta-sigma modulator comprising a summator SM receiving an input signal IS (X) of amplitude X on a positive input, an integrator IT of gain A and a quantizer QT1 providing an output signal OS '(Y) of amplitude Y.
• the quantizer QT1 is conventionally modeled as an adder receiving on a first positive input the signal supplied by the integrator IT and on a second positive input a noise N representing the quantization noise.
• the signal OS ' is sent back to a negative input of the summator SM by means of a state loop SL for shaping the quantization noise N. It is assumed here and conventionally that the gain A of the integrator IT is large (this gain can be generated by summing gain units, as previously described).
• the intrinsic value of the noise (i.e. without taking into account the noise shaping) is therefore equal to N / (14A), where N is a constant which is only a function of the quantization step.
• Fig. 14B shows the same elementary delta-sigma modulator, to which is added a gain unit B1 having a gain G, and a gain unit B2 having a gain 1 / G.
• the gain unit B1 is inserted between the point of application of the input signal IS (X) and the input of the summator SM.
• the gain unit B2 is arranged at the output of the quantizer QT1, after the feedback node where the state loop SL is connected.
• the signal on the feedback node is designated OS '(Y) and has an amplitude Y.
• the signal at the output of the gain unit B2 is designated OS "and has an amplitude Z.
• the amplitude Z of the signal OS "at the output of the unit B2 is therefore:
• FIG. 15 represents an embodiment of an amplifier AlO according to the third improvement.
• the amplifier AlO comprises from its input to its output a gain unit MTI1 receiving the input signal IS (X) of amplitude X, a digital modulator 10 clocked by the frequency sampling clock signal Fs As already described, a gain unit DCT2, the power circuit PA already described, providing here an output signal designated OS "(Z) with reference to Fig. 14B.
• the signal OS is applied to the load LD.
• the gain unit DCT2 is here a pilot circuit which controls the power circuit PA.
• the gain unit MTI1 and the pilot circuit DCT2 each comprise a control input C receiving a signal SEL having two possible values ON and OFF, for example 1 and 0.
• the signal SEL is supplied by an ADET circuit for monitoring the signal. amplitude of the input signal.
• the ADET circuit comprises, for example, an absolute value module ABS3 and a threshold detector R03 in the form of a hysteresis relay.
• the module ABS3 receives the signal IS (X) and supplies its absolute value to the detector R03.
• the detector R03 sets the signal SEL to 1 (ON) when the absolute value of the signal IS is less than a threshold TH representing for example 1/5 of the full scale of the input signal.
• the gain unit MTI1 transfers the input signal IS (X) to the modulator 10 without modifying its amplitude.
• the modulator 10 thus provides a digital modulated signal MS (X) of amplitude X.
• DCT2 receives the signal MS (X) and transfers it to the power circuit PA.
• the signal SEL goes to 1 (ON).
• the gain unit MT1I transfers to the modulator 10 the input signal IS by applying to it a gain G, and thus provides a signal whose amplitude is equal to GX.
• the modulator 10 thus provides a digital modulated signal MS (GX) of amplitude GX.
• the driver circuit DCT2 receives the signal MS (GX) and transfers it to the power circuit PA by dividing its amplitude GX by G, to restore the original amplitude X of the input signal.
• the noise N present in the output signal OS "supplied by the power circuit PA is then divided by G.
• the amplitude X of the digital modulated signal MS is not the amplitude of the signals which forms the signal MS but the amplitude of the signal IS (X) whose modulated signal MS represents the coded form.
• the modulator 10 may be one of the delta-sigma modulators 2, 3, 4, 5, 6, 7, 8 previously described in connection with FIGS. 2A to 4, or the conventional delta-sigma modulator 1 shown in FIG.
• the modulated signal MS is a quantized signal QS, ie a signal modulated by pulse density (PEM).
• the gain unit MTI1 is for example made by means of a multiplexer having an input ON1 receiving the input signal IS via a module having a gain G and an input 0N2. directly receiving the signal IS, the multiplexer being controlled by the signal SEL.
• the digital modulator 10 is a delta-sigma modulator providing the quantized signal QS (X)
• the driver circuit DCT2 is an RTZ converter RM2 which applies the gain 1 / G by providing the power circuit a signal RTZS2 whose duty cycle is decreased by G.
• the gain G is a low integer value, for example equal to 2, 3 or 4.
• Various embodiments of the RM2 converter can be considered.
• the quantized signal QS is a signal with two states +1 and -1.
• the converter RM2 is active when the signal SEL is equal to 1 (ON).
• the signal SEL is equal to 0 (OFF)
• the converter is transparent and transfers the quantized signal QS (X) to the power circuit PA.
• the converter comprises an input IN receiving the quantized signal QS, the input C receiving the signal SEL, an RTZ generator RGEN3, a multiplexer MUXS1, and a multiplier MT1 having an input connected to the input IN, an input connected to the output of the multiplexer MUXS1 and supplying the signal RTZS2.
• the generator RGEN3 is a frequency divider logic receiving a signal of frequency 2GFs and providing an RTZ signal RS (1 / G) having a duty ratio of 1 / G.
• the multiplexer MUXS1 receives the signal RS (1 / G) on one input and the logic value 1 on a second input.
• the multiplexer MUXS1 is controlled by the signal SEL and its output provides a signal RS 1 which is equal to 1 when SEL is equal to 0 (OFF) and equal to RS (1 / G) when SEL is equal to 1 (ON).
• the operation of the RM20 converter is illustrated by the timing diagrams of Figures 18A to 18C.
• Figure 18A shows variations of the QS signal, arbitrarily selected.
• the signal RTZS2 presents a report cyclic equal to 1 / G and thus vehicle in coded form (modulation by pulse width) a signal whose amplitude is divided by G relative to that of the signal conveyed in coded form by the quantized signal QS.
• the quantized signal QS is a multilevel signal.
• the converter RM2 converts the quantized signal QS (X) into RTZ signals having a variable duty cycle by associating with each value of QS a corresponding value having a duty ratio of between 0 and 1 , as has been previously described in relation to FIGS. 6 and 11.
• FIG. 19 An embodiment RM21 of the RM2 converter is shown in FIG. 19 in the case where the QS signal has 3 quantization levels in absolute value including the zero value, and 5 quantization levels in total.
• the converter RM21 comprises a threshold detector R04 in the form of a hysteresis relay, an absolute value module ABS4, two multiplexers MUXON, MUXOFF, a decoder DEC3, a multiplexer MUXS2, an RTZ signal generator RGEN4 receiving here a frequency signal 4Fs , and an MT2 multiplier.
• the relay R04 has a detection threshold equal to 0. Its input receives the signal QS or the NSS signal previously described, provided by the delta-sigma stage DS5. The output of the relay R04 provides the signal SIGN already described which is applied to an input of the multiplier MT2.
• the signal SIGN is equal to +1 when the signal QS is positive and -1 when the signal QS is negative.
• the generator RGEN4 is a frequency divider logic which provides RTZ RS (1/2) and RS (1/4) signals having a duty ratio of 0.5 and 0.25, respectively.
• the multiplexer MUXOFF has three inputs receiving respectively the logic "0", the signal RS (1/2) and the "1" logic.
• the MUXON multiplexer has three inputs receiving respectively the logical "0", the RS signal (1/4) and the RS signal (1/2).
• the multiplexer MUXOFF provides a signal RSa and the multiplexer MUXON provides a signal RSb.
• the signals RSa, RSb are applied to inputs of the multiplexer MUXS2 which selects the signal RSa or the signal RSb to apply it to a second input of the multiplier MT2.
• the two multiplexers MUXOFF and MUXON select one of the signals they receive on their inputs as a function of the value of the signal
• the signal RSa is an NRZ signal having a zero duty cycle if the logical 0 is selected by the multiplexer, a duty ratio of 0.5 if the signal RS (1/2) is selected or a duty cycle of 1 if the "1 "logic is selected.
• the signal RSb is an NRZ signal having a zero duty ratio if the logical 0 is selected by the multiplexer, 0.25 if the RS signal (1/4) is selected or 0.5 if the RS signal (1/2 ) is selected.
• Figure 20A is a timing diagram showing QS signal variations arbitrarily selected.
• the duty cycle of the RTZS2 signal is zero when I QS
• 0, equals 0.5 when
• FIG. 21 shows an embodiment RM200 extended to the order n, with n even, of the converter which has just been described, n being the number of detection thresholds of the quantizer.
• the converter RM200 converts into a signal RTZ, according to the signal SEL, a quantized signal QS having n + 1 levels provided by a quantizer such as that represented in FIG. 10.
• the multiplexers MUXOFF and MUXON are replaced by multiplexers MUXOFF 'and MUXON with multiple inputs which are controlled by a decoder DEC4 which replaces the decoder DEC3.
• An RGEN4 signal generator is provided to provide the multiplexer MUXOFF with RTZ signals having cyclic ratios of 2 / n, 4 / n, 6 / n, ..., (n-2k) / n, ..., ( n-2) / n from a signal of frequency nFs / 2.
• Multiplexer MUXOFF ' also receives the values 0 and 1 to provide duty cycle signals of 0 and 1, respectively.
• An RGEN5 signal generator is provided to provide the multiplexer MUXON 'with RTZ signals having cyclic ratios of (1 / G) (2 / n),
• FIG. 22 represents an amplifier AlI which implements the first improvement and a variant of the third improvement.
• the amplifier AI1 is in its general structure similar to the amplifier A4 which has been described above in relation with FIG. 4. It contains the elements LPF1, ADC, DF1 to DF3, SH1 to SH3, the quantizer QT1, and the delta-sigma stages DS1-DS5, represented here in the form of a block.
• the level detector ADET is provided for monitoring the input signal IS (X) and provide the signal SEL which activates the application of the gain G.
• the gain G is not applied here to the input signal by means of the gain unit MTI1 as in the embodiment shown in FIG. an MT12 gain unit having a gain of 1 / G is arranged in the highest rank status loops SL4, SL5.
• the gain unit MT12 receives the quantized signal QS and supplies the state loops SL4, SL5 with a quantized signal QS 'carrying in encoded form (PDM modulation) a feedback signal the amplitude of which is divided by G when the signal SEL is equal to 1
• the quantized signal QS is returned in the state loops SL4, SL5 by the gain unit MT12 without modification of its amplitude.
• the quantized signal QS vehicle in form a signal modulated by pulse density (the amplitude of the pulses can be multilevel type or not) a signal whose amplitude is equal to GX instead of X.
• the embodiments RM20, KM21, RM200 previously described in relation to FIGS. 17, 19 and 21 are applicable to the amplifier AI1, the choice of the appropriate embodiment being a function of the number of levels that the quantized signal QS exhibits.
• Embodiments of amplifiers according to the first or third improvements of the invention are moreover susceptible to various applications other than audio applications, for example the control of motors, the control of switches, and generally any application requiring using a digitally controlled power circuit providing an output signal having good characteristics in terms of SNR and THD.

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