EP2238675A1

EP2238675A1 - A power supply

Info

Publication number: EP2238675A1
Application number: EP08869624A
Authority: EP
Inventors: Eftal Sen
Original assignee: Arcelik AS
Current assignee: Arcelik AS
Priority date: 2007-12-31
Filing date: 2008-12-04
Publication date: 2010-10-13
Also published as: WO2009087506A1

Abstract

The present invention relates to a power supply (1) which ensures that the device to which it is connected consumes less energy in standby mode by making the standby mode SMPS output voltage (VL) have two levels.

Description

Description A POWER SUPPLY

[ 1 ] Field of the Invention

[2] The present invention relates to a power supply that can be operated in standby mode.

[3] Prior Art

[4] Switch Mode Power Supply (SMPS) circuits are power supply circuits which are used in devices that require high amounts of power, for controlling the power consumption of devices. When the device to which it is connected switches to standby mode, the SMPS circuit supplies power only to the processor, which is sufficient to be active in standby mode, and disconnects the supply to other circuits of the device. Thus, when the device is switched to standby mode, its power consumption will decrease compared to its normal operation mode. Additionally a regulator is used which regulates the voltage between the processor and the SMPS. Upon taking into account a certain safety margin against possible voltage drops, the SMPS output voltage (VL) in the standby mode is equal to the sum of processor supply voltage, the voltage drop on the voltage regulator and the safety margin.

[5] In existing applications, low voltage drop types can be used for the voltage regulator, but the safety margin can not be set below a certain value taking into account the voltage drops at the start-up. As a result of setting a large safety margin, the output voltage (VL) at the standby mode is kept high for as long as the period (T) in which the device is in standby mode and the power consumption in the standby mode increases (Figure 1).

[6] The USA patent document No. US6496390, an application in the state of the art, discloses an application for reduction of power consumption in SMPS circuits. In the circuit structure having a two level energy consumption option in addition to the normal operating mode, the energy consumption levels are set by the signals outputted from the microprocessor. The circuit used for obtaining different energy levels comprises a comparator that compares the voltage values and a power supply that provides the power required for the operation thereof.

[7] Summary of the Invention

[8] The objective of the present invention is to realize a power supply that reduces power consumption in standby mode in devices employing SMPS type power supply.

[9] Another objective of the invention is to realize a power supply with reduced cost and a simple structure.

[10] There are two embodiments of the power supply realized to fulfill the objective of the present invention and defined in Claim 1 and in its dependent claims. In both of the embodiments, two different levels (Vl, V2) are attained for the SMPS output voltage (VL). The voltage value (V2) at the second level is equal to the value at the standard embodiment. The voltage value (Vl) at the first level is lower than the output voltage at the second level. When the device is in standby mode, SMPS output voltage is maintained in the first level voltage (Vl); however it is passed onto the second level (V2) until a short time period (T2) to the moment (tθ) of leaving the standby mode. Thus, for the period (Tl) during which the output voltage is maintained in the first level, less energy is consumed and energy is saved (Figure X).

[11] In the first embodiment of the invention, the voltage (VL) at the SMPS output is maintained at a fixed value which is slightly greater than the minimum operation voltage of a voltage regulator connected to the SMPS output. In the said embodiment, the feedback circuit used for obtaining different output voltages comprises two diodes and two transistors. In the second embodiment, the feedback circuit changes the SMPS output voltage with the power supply received from the voltage regulator output, such that it will automatically change the voltage at the SMPS output. In the feedback circuit in the second embodiment, a transistor and a switch are used, which operate according to the signals received from the processor. In both embodiments, energy is saved when the device is in standby mode since a lower VL value than the normal value is achieved. Furthermore, advantages of ease of production and low cost are provided owing to the fact that the feedback circuits employed in attaining the said levels comprise much fewer components compared to the prior art applications.

[12] Detailed Description of the Invention

[13] The power supply realized to fulfill the objective of the present invention is illustrated in the accompanying figures in which,

[14] Figure 1 is the graphic view of change of the VL voltage by time in standby mode and normal operation in prior art applications.

[15] Figure 2 is the graphic view of change of the VL voltage by time in standby mode and normal operation in an embodiment of the invention.

[16] Figure 3 is the circuit diagram of an embodiment of the inventive power supply.

[17] Figure 4 is the circuit diagram of another embodiment of the inventive power supply.

[18] The components shown in the figures are numbered as follows:

[19] 1. Power supply

[20] 2. Power input circuit

[21] 3. Transformer

[22] 4. Voltage regulator

[23] 5. Processor

[24] 6. Feedback circuit

[25] 7. Controller [26] 8. Clamp circuit

[27] 9. Parallel regulator

[28] 10. 110, 210 Capacitor

[29] 11. I l l, 211, 311 Transistor

[30] 12. 112, 212, 312 Diode

[31] 13. 113, 213, 313, 413, 513 Resistor

[32] 14. Bridge

[33] 15. Switch

[34] 16. Optocoupler

[35] The inventive power supply (1) comprises a power input circuit (2) at the mains input, comprised of a bridge (14) and a capacitor (10); a transformer (3) to which input winding is supplied from the output of the power input circuit (2) and which comprises at least two output windings; at least two diodes (12, 112) and two capacitors (110, 210) which enable obtaining SMPS output voltages (VL, VH) from the voltages at the output windings of the transformer (3); a voltage regulator (4) which regulates VL voltage; a processor (5) which is supplied with power in standby mode and which enables the operation mode to be changed with the S 1 and S2 signals that it provides acquiring logic 1 and 0 values; a feedback circuit (6) which forms two different levels for the SMPS output voltage (VL) in the standby mode according to the signals it receives from the processor (5); a controller (7) which is supplied power by the feedback signal that it receives from the feedback circuit (6) and which controls the SMPS circuit; a clamp circuit (8) which is serially connected in between the high voltage output of the transformer (3) and the VL output and which is controlled by the S2 signal of the processor; and a transistor (11) connected in between the controller (7) and the input winding of the transformer (3).

[36] The power input circuit (2) transfers the mains voltage applied in between the A-B nodes to the input winding of the transformer (3). The diodes (12, 112) and the capacitors (110, 210) connected to the output of the transformer (3) form the DC voltages at the L and H nodes by rectifying the voltage at the output windings. The voltage (VL) at the L node is the voltage between the L node and the ground (G). VL is the voltage used for supplying power to the voltage regulator (4) and the processor (5) and it is the voltage of the power supply (1) in standby mode. Accordingly, the energy consumed in standby mode changes according to the value of the VL voltage. The voltage (VH) at the H node is the voltage between the H node and G node. VH is the output voltage of the power supply (1) in the normal operation mode.

[37] The voltage regulator (4) eliminates the irregularities occurring in the VL voltage.

Input of the voltage regulator (4) is connected to the output winding (L-G) of the transformer (3) providing low voltage, while the output (C) of the same is connected to the processor (5). The voltage (VLC) on the voltage regulator (4) is equal to the voltage between the L-C nodes.

[38] The processor (5) is connected to the output (C) of the voltage regulator (4) and the

G (ground) node, and it is supplied with the voltage (VC) at the C node. The processor (5) continues to draw power in standby mode. D output of the processor (5) is used for connection with the other circuits. Additionally, Sl and S2 signals are sent via at least one output of the processor (5). Sl and S2 signals, which have logic 1 and 0 values, provide switching between levels (1st level, 2nd level) and modes (standby, normal operation) by the adjustment of energy levels in standby mode. In normal operation mode, both Sl and S2 signals are at logic 1 value. In the 1st level of the standby mode, the values of Sl and S2 signals are logic 1. In the 2nd level of the standby mode, the value of Sl is 0 and the value of S2 is 1.

[39] While S 1 and S2 signals can be received from two different outputs of the processor

(5), it is also possible, after receiving Sl signal from a single output, to derive S2 signal from Sl signal using a separate delay circuit. Since during switching from standby mode to normal operation mode, S2 signal shows the same change as in S 1 signal after a certain period, use of S2 signal obtained by the delay circuit does not cause any change in operation of the power supply (1).

[40] S 1 output is connected to the feedback circuit (6) and S2 output is connected to the feedback circuit (6) and the clamp circuit (8). The clamp circuit (8) is turned on (conducting) by being triggered upon S2 signal acquiring logic 1 value in standby mode and connects the high voltage output of the transformer (3) to L node. Since logic value of S2 is 0 in normal operation mode, the clamp circuit (8) is not active and it is useless.

[41] The feedback circuit (6) is connected to Sl and S2 outputs of the processor (5) and L and H nodes. The feedback circuit (6) provides switching between the normal operation mode and standby mode and among the energy levels of the standby mode according to the changes in the logic values (1 or 0) of Sl and S2 signals. The output of the feedback circuit (6) is connected to the controller (7) and the feedback signal is transferred to the controller (7) via this connection. Output of the controller (7) is connected to a transistor (11) via G311 line and D311 end of the transistor (11) is connected with the input winding of the transformer (3) to complete the feedback line.

[42] The feedback circuit (6) comprises a resistor (13) whose one end is connected to the

H node; another resistor (113) whose one end is connected to the resistor (13) and the other to ground; a parallel regulator (9) which receives reference voltage from the node (E) in between the two resistors (13, 113) and whose anode end is connected to ground; a resistor (213) whose one end is connected to L node; and an optocoupler (16) whose input is connected in between the resistor (213) and the parallel regulator (9) and output is connected to the controller (7). The circuit comprised of two resistors (13, 113) and a parallel regulator (9), receives feedback from the output at the H node in normal operation mode and keeps VH voltage fixed by sending this information to the controller (7) via the optocoupler (16).

[43] The SMPS output voltage (VL) in standby mode is equal to the sum of the voltages on the voltage regulator (4), that is, the voltage (VCL) between the C and L nodes, and the voltage (VC) of the C node which is the operation voltage of the processor (5). Additionally VL value is obtained by taking into account a certain safety margin against possible voltage drops. For example, in the case that the operation voltage (VC) of the processor (5) is 3.3 V, the voltage drop (VCL) in the regulator is 1.2 V, and the safety margin is 4.3 V; SMPS output voltage will be 8.8 V (VL2) during the period (T) in which the power supply is in standby mode (Figure 1).

[44] The inventive power supply (1) provides a two level standby mode in order to reduce the energy consumption in standby mode. Although the output voltage (VL2) at the 2nd level is equal to the value in the present application, the output voltage (VLl) at the 1st level is adjusted to have a lower safety margin. This way, since VLl value is lower than VL2 value, energy is saved in standby mode. When the device to which the power supply is connected switches to standby mode, the power supply (1) operates in the 1st level (Tl). When the device will leave the standby mode, the power supply (1) switches to the 2nd level, which has the normal safety margin and before switching to the normal operation mode, it operates in the 2nd level for a short period of time (T2) and then switches to the normal operation mode.

[45] Controlling the safety margin in the first level such that it will be lower than the safety margin in the second level (in existing applications) can be performed in two different ways:

[46] a) By maintaining the voltage (VL) at the SMPS output fixed, such that the voltage

(VCL) on the voltage regulator (4) is slightly greater than the minimum operation voltage of the voltage regulator (4) (e.g. if the operation voltage of the processor (5) is 3.3 V and minimum operation voltage of the voltage regulator (4) is 1.2 V, then by maintaining VL value at 3.3+1.2 = 4.5V).

[47] b) By maintaining the voltage (VL) at the SMPS output at such a value which will supply the voltage regulator (4) with an amount lower than the minimum operation voltage and will supply the processor (5) with energy lower than the normal supply voltage but will not hinder operation thereof (e.g. in the case that the processor (5) is supplied with 3.1V and the voltage (VCL) on the voltage regulator (4) is 0.7V, by maintaining the VL value at 3.1+0.7=3.8 V).

[48] In one embodiment of the invention, the feedback circuit (6) comprises a transistor

(111) whose emitter (El 11) is connected to ground and base (Bl 11) is connected to S2 output of the processor; a zener diode (312) whose anode is connected to the collector (Cl 11) of the transistor (111); a transistor (211) whose emitter (E211) is connected to ground, base (B211) is connected to Sl output of the processor and the collector (C211) is connected to the cathode of zener diode (312); and a zener diode (212) whose anode is connected to the collector (C211) of the transistor (211) and cathode is connected to the cathode of the parallel regulator (9) (Figure 3).

[49] In this embodiment, when the power supply (1) switches to standby mode from normal operation mode, all functions of the device cease except the processor (5) which is supplied power from the SMPS output (L) and S 1 and S2 outputs of the processor (5) switch to logic 1 position. As S2 switches to logic 1 position, the clamp circuit (8) is triggered and turned on, and the anode of the diode (112) which is connected to the high voltage output winding of the transformer (3) is connected to the cathode of the diode (12) connected to the low voltage output. Additionally, due to the fact that Sl and S2 signals are logic 1, the transistors (211, 111) in the feedback circuit (6) are turned on. In this case, the parallel regulator (9) does not have an impact on the SMPS output voltage (VL) of the standby mode. The feedback circuit (6) is completed via the L node, resistor (213), optocoupler (16), zener diode (212), transistor (211) and ground line. Under these circumstances, (if the voltage drop on the resistor (213) is neglected) the output voltage (VL) is approximately the sum of the voltage drops at zener diode (212), transistor (211) and optocoupler (16). This voltage value is the 1st level voltage value (VLl) in standby mode of the power supply (1).

[50] For example, in the case that the operation voltage of the processor (5) is 3.3V, the minimum operation voltage on the voltage regulator (4) is 1.2V, the VL voltage should be at least 3.3 + 1.2 = 4.5V. In order to obtain a 1st level voltage of this value, considering that the sum of voltage drops on the transistor (211) and optocoupler (16) is IV, the voltage on the zener diode (212) should be approximately 4.5 - 1 = 3.5V.

[51] In this embodiment, when the power supply (1) is going to switch from standby mode to normal operation mode, firstly Sl output of the processor (5) switches to logic 0 position. As a result of this, the transistor (211) connected to the Sl output turns off and the feedback circuit is completed via the L node, resistor (213), optocoupler (16), zener diodes (212, 312), transistor (111) and ground line. Under these conditions, (if the voltage drop on the resistor (213) is neglected) the output voltage (VL) is approximately the sum of the voltage drops at zener diode (212, 312), transistor (111) and optocoupler (16). This voltage value is more than the 1st level voltage value (VLl) in standby mode of the power supply (1) by an amount of the voltage on the zener diode (312). Accordingly, the required safety margin voltage during leaving the standby mode will be as much as the voltage on the zener diode (312) to be used. This voltage value is the value of the 2nd level voltage (VL2) in standby mode of the power supply (1).

[52] For example if the zener diode (312) used is a zener diode of 4.3V, in this case, VL output voltage, which is 4,.5V in the 1st level in standby mode, first rises to 4.5 + 4.3 = 8.8V upon Sl signal switching from logic 1 to 0 position.

[53] During switching to normal operation mode, a short period of time after the power supply (1) switches to 2nd level, S2 output of the processor (5) also switches to logic 0 position and turns off (nonconducting) the clamp circuit (8) and upon activating the other functions of the device, it enables switching to the normal operation mode.

[54] In another embodiment of the invention, the feedback circuit (6) comprises a resistor

(513) whose one end is connected to L node; a switch (15) having a, b and c ends, wherein a end is connected to C node, b end is connected to the end of the resistor (513) which is not connected to the L node, which switch (15) changes position between a and b ends, and provides conduction between a - c ends when Sl signal is in 1 position, and between b - c ends when Sl signal is in 0 position; two resistors (313, 413) serially connected to each other between the c end of the switch and the ground; and a transistor (311) whose source (S311) is connected in between the two resistors (413, 133), drain (D311) is connected to the E node, and gate (G311) is connected to S2 output of the processor (Figure 4).

[55] In this embodiment, the feedback is received from the output of the voltage regulator

(4) (from the C node) and VL voltage is adjusted by the switch (15) via the serially connected resistors (313, 413). Thus, in the case that a voltage regulator (4) is used, which can operate at a lower value than it is foreseen, VL voltage is not unnecessarily kept high.

[56] In this embodiment, when the power supply (1) switches from normal operation to standby mode, as it is in the previous embodiment, all functions of the device cease except the processor (5) which is supplied power from the SMPS output (L) and Sl and S2 outputs of the processor (5) switch to logic 1 position. As S2 switches to logic 1 position, the clamp circuit (8) is triggered and turned on, and the anode of the diode (112) which is connected to the high voltage output winding of the transformer (3) is connected to the cathode of the diode (12) connected to the low voltage output. Additionally, due to the fact that Sl and S2 signals are logic 1, the switch (15) connected to Sl output switches to a-c position and the transistor (311) connected to S2 output is turned on. Values of the resistors (113, 313, 413) are selected such that the voltage at the C node (VC) is brought to a value which is slightly lower than the normal operation voltage of the processor (5). In this case, the voltage regulator (4) is supplied and operated with a voltage at a lower level than the minimum operation voltage and the processor (5) is supplied and operated with a voltage, which is lower than the normal supply voltage which will not hinder its operation thereof, and a lower SMPS voltage (VL) is achieved. Under these conditions, the output voltage (VL) is the sum of the voltage that is supplied to the processor (5) and the voltage drop (VCL) on the voltage regulator (4). This voltage value is the 1st level voltage value (VLl) of the power supply (1) in standby mode.

[57] For example, when a processor (6) with a nominal operation voltage of 3.3V is supplied with 3.1V and the minimum voltage drop on the voltage regulator (4) is selected to be 0.7V, VL voltage should be at least 3.1 + 0.7 = 3.8V.

[58] In this embodiment, when the power supply (1) is going to switch from standby mode to normal operation mode, at first Sl output of the processor (5) switches to logic 0 position. As a result of this, the switch (15) connected to the Sl output switches to b-c position and the feedback circuit is completed via the L node, the resistor (513) connected to this node, the switch (15), the resistor (413) connected to the c end, two resistors (113, 313) connected to each other in parallel and the ground line. Thus, VL voltage increases depending on the value of the resistor (513) connected to the L node and takes its new value before leaving the standby mode. This voltage value is the 2nd level voltage value (VL2) in standby mode of the power supply (1).

[59] During switching to normal operation mode, a short period of time after the power supply (1) switches to 2nd level, S2 output of the processor (5) also switches to logic 0 position and turns off the clamp circuit (8) and the transistor (311) and upon activating other functions of the device, it enables switching to the normal operation mode.

[60] The inventive power supply (1) enables energy saving by reducing the SMPS output voltage (VL) in the standby mode and thus the energy consumption in the connected device. The output voltage (VL) in standby mode is set to a value (Vl) lower than the voltage (V2) in the existing application when the device to which the power supply (1) is connected is switched to standby mode, and it is brought to a value near the voltage (V2) in the existing applications a shortly before switching from the standby mode to normal operation mode. This way, energy consumption is reduced by using a two level output voltage (VL) during standby mode. Additionally, the feedback circuit (6) used for achieving the said levels comprises much fewer components compared to the applications in the state of the art, and this provides advantages of ease of production and low cost.

[61] Within the scope of this basic concept, it is possible to develop a wide variety of embodiments of the power supply (1). The invention is essentially according to the claims and it can not be limited to the examples explained herein.

Claims

[ 1 ] A power supply ( 1 ) comprising

- a power input circuit (2),

- a transformer (3),

- a voltage regulator (4),

- a processor (5) which is supplied with power in the standby mode and which enables the operation mode to be changed with the at least one signal (Sl, S2) that provides acquiring a logic 1 or 0 value;

- a feedback circuit (6) which forms two different levels for the SMPS output voltage (VL) in the standby mode according to the signals it receives from the processor (5), and which comprises a resistor (13) whose one end is connected to the H node; another resistor (113) whose one end is connected to the resistor (13) and the other to ground; a parallel regulator (9) which receives reference voltage from the node (E) in between the two resistors (13, 113) and whose anode end is connected to ground; a resistor (213) whose one end is connected to L node; and an optocoupler (16) whose input is connected in between the resistor (213) and the parallel regulator (9) and whose output is connected to the controller (7),

- a controller (7),

- a clamp circuit (8),

- a transistor (11),

- at least two diodes (12, 112),

- at least two capacitors (110, 210), characterized by a feedback circuit (6) which provides a two level standby mode, operates in the 1st level for Tl period when the device to which it is connected switches to standby mode, switches to the 2nd level that has the normal safety margin when the device is going to leave the standby mode, and switches to normal operation mode after operating in the 2nd level for a short period of time (T2), wherein the value of the output voltage (VLl) in the 1st level is lower than the value of the output voltage (VL2) in the 2nd level.

[2] A power supply (1) according to Claim 1, characterized by a feedback circuit (6) which comprises

- a transistor (111) whose emitter (El 11) is connected to ground and base (Bi l l) is connected to S2 output of the processor (5),

- a zener diode (312) whose anode is connected to the collector (Cl 11) of the transistor (111)

- a transistor (211) whose emitter (E211) is connected to ground, base (B211) is connected to Sl output of the processor and the collector (C211) is connected to the cathode of zener diode (312)

- and a zener diode (212) whose anode is connected to the collector (C211) of the transistor (211) and cathode is connected to the cathode end of the parallel regulator (9), and whose transistors (211, 111) are turned on and which produces 1st level voltage (Vl) at the L node upon Sl and S2 signals acquiring logic 1 value, and whose one transistor (211) is turned off and which produces 2nd level voltage (V2) at the L node upon S 1 signal acquiring 0 value.

[3] A power supply (1) according to Claim 1, characterized by a feedback circuit (6) which comprises

- a resistor (513) whose one end is connected to L node,

- a switch (15) having a, b and c ends, wherein a end is connected to C node, b end is connected to the end of the resistor (513) which is not connected to the L node, which switch (15) changes position between a and b ends, and provides conduction between a - c ends when S 1 signal is in 1 position, and between b - c ends when S 1 signal is in 0 position,

- two resistors (313, 413) serially connected to each other between the c end of the switch and the ground,

- a transistor (311) whose source (S311) is connected in between the two resistors (413, 133), drain (D311) is connected to the E node, and gate (G311) is connected to S2 output of the processor, and whose switch (15) connected to the Sl output switches to a-c position, whose transistor (311) connected to the S2 output is turned on and which produces a 1st level voltage (Vl) at the L node, upon Sl and S2 signals acquiring logic 1 value; and whose switch (15) connected to the Sl output switches to b-c position, and which produces a 1st level voltage (Vl) at the L node, upon Sl and S2 signals acquiring logic 0 value.

[4] A power supply (1) according to any of the preceding claims characterized by a delay circuit, which enables deriving S2 signal from S 1 signal, which it receives from a single output of the processor (5).