EP2191410A2 - Identification of devices using physically unclonable functions - Google Patents

Identification of devices using physically unclonable functions

Info

Publication number
EP2191410A2
EP2191410A2 EP08807343A EP08807343A EP2191410A2 EP 2191410 A2 EP2191410 A2 EP 2191410A2 EP 08807343 A EP08807343 A EP 08807343A EP 08807343 A EP08807343 A EP 08807343A EP 2191410 A2 EP2191410 A2 EP 2191410A2
Authority
EP
European Patent Office
Prior art keywords
response
memory
data
physically unclonable
unclonable function
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP08807343A
Other languages
German (de)
French (fr)
Other versions
EP2191410B1 (en
Inventor
Jorge Guajardo Merchan
Shankaran S. Kumar
Pim T. Tuyls
Geert J. Schrijen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intrinsic ID BV
Original Assignee
Intrinsic ID BV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intrinsic ID BV filed Critical Intrinsic ID BV
Priority to EP08807343.2A priority Critical patent/EP2191410B1/en
Publication of EP2191410A2 publication Critical patent/EP2191410A2/en
Application granted granted Critical
Publication of EP2191410B1 publication Critical patent/EP2191410B1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/73—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information by creating or determining hardware identification, e.g. serial numbers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F21/70—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer
    • G06F21/71—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information
    • G06F21/76—Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer to assure secure computing or processing of information in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/58—Random or pseudo-random number generators
    • G06F7/588—Random number generators, i.e. based on natural stochastic processes
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/24—Memory cell safety or protection circuits, e.g. arrangements for preventing inadvertent reading or writing; Status cells; Test cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/16—Multiple access memory array, e.g. addressing one storage element via at least two independent addressing line groups
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/544—Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L9/00—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols
    • H04L9/32—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials
    • H04L9/3271—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using challenge-response
    • H04L9/3278—Cryptographic mechanisms or cryptographic arrangements for secret or secure communications; Network security protocols including means for verifying the identity or authority of a user of the system or for message authentication, e.g. authorization, entity authentication, data integrity or data verification, non-repudiation, key authentication or verification of credentials using challenge-response using physically unclonable functions [PUF]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2221/00—Indexing scheme relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/21—Indexing scheme relating to G06F21/00 and subgroups addressing additional information or applications relating to security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
    • G06F2221/2129—Authenticate client device independently of the user
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54433—Marks applied to semiconductor devices or parts containing identification or tracking information
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2223/00—Details relating to semiconductor or other solid state devices covered by the group H01L23/00
    • H01L2223/544—Marks applied to semiconductor devices or parts
    • H01L2223/54433—Marks applied to semiconductor devices or parts containing identification or tracking information
    • H01L2223/5444—Marks applied to semiconductor devices or parts containing identification or tracking information for electrical read out
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making

Definitions

  • This invention relates to a technique for generating a response to a physically unclonable function (PUF), particularly for use in identification of devices having challengeable memory and especially, but not necessarily exclusively, suitable for use in preventing cloning of such devices.
  • PAF physically unclonable function
  • Physically unclonable functions are essentially random functions bound to a physical device in such a way that it is computationally and physically infeasible to predict the output of the function without actually evaluating it using the physical device.
  • a Physically Unclonable Function is realized by a physical system, such that the function is relatively easy to evaluate but the physical system is hard to characterize and hard to clone. Since a PUF cannot be copied or modeled, a device equipped with a PUF becomes unclonable. Physical systems that are produced by an uncontrolled production process (i.e. one that contains some randomness) are good candidates for PUFs.
  • a PUF computes its output by exploiting the inherent variability of wire delays and gate delays in manufactured circuits. These delays in turn depend on highly unpredictable factors, such as manufacturing variations, quantum mechanical fluctuations, thermal gradients, electromigration effects, parasitics, noise, etc.
  • a good PUF is therefore not likely to be modeled succinctly, nor be predicted or replicated, even using identical hardware (which will still have different random manufacturing variations and associated delays, and thus yield an implemented function different from the first).
  • Field configurable devices such as field programmable gate arrays (FPGAs) are typically configured using data, usually called a configuration bitstream or simply a bitstream, that is supplied to the device after the device is deployed in an application.
  • the configuration data may be provided to the device when the device is powered on.
  • Significant revenue is lost due to issues such as cloning of such devices and/or unreported over-production thereof.
  • a PUF is known as a Coating PUF which is created by covering an IC with a coating that is doped with random dielectric particles.
  • the top metal layer of the IC contains a matrix of sensor structures, which enables the local capacitance values at several positions on the coating to be measured and capacitance measurements at several coating locations (i.e. different challenges) can be used to derive a cryptographic key that can be used by the IC (internally) for several cryptographic purposes.
  • the PUF' s physical system is designed such that it interacts in a particular way with stimuli (challenges) and leads to unique but unpredictable responses.
  • a PUF challenge and the corresponding response are together called a Challenge-Response pair.
  • US Patent Application Publication No. US 2006/0209584 Al describes a field programmable gate array (FPGA) having a PUF module.
  • the PUF module has a PUF circuit configured to generate a PUF response to a challenge signal.
  • the module is designed such that when deployed in the field, the response for a particular challenge is difficult to determine from the device.
  • Configuration data encrypted by the providing party using a secret key, is provided to the device in the field together with a challenge code and an access code derived from a combination of the secret key and the respective PUF response for an authorized device.
  • the challenge code is used by the PUF circuit to generate a PUF response and this response is used, together with the access code, to reconstruct the secret key which, if the device is an authorized device, will enable the configuration data to be decrypted and the device to be configured.
  • a method of generating a response to a physically unclonable function said response being uniquely representative of the identity of a device having challengeable memory, the memory comprising a plurality of logical locations each having at least two possible logical states, the method comprising applying a challenge signal to an input of said memory so as to cause each of said logical locations to enter one of said two possible logical states and thereby generate a response pattern of logical states, said response pattern being dependent on said physically unclonable function which is defined by the physical characteristics of said memory, the method further comprising reading out said response pattern.
  • said memory has at least two access ports, the method comprising accessing said plurality of logical storage locations via said at least two access ports so as to create a contention, and using resulting response data read from said logical locations to generate said response to said physically unclonable function.
  • the memory comprises an array of components having an unstable state and at least two stable states, the method comprising applying an excitation signal to each of said components so as to drive each of said components into a respective one of said at least two stable states, and generating output data comprised of the resultant response data comprised of the resultant response data comprised of the combination of respective states of said components to generate said response to said physically unclonable function.
  • data in the form of a challenge pattern may be written to at least one of the at least two access ports, and the resulting response pattern stored in said memory is read out and used to generate said response to said physically unclonable function.
  • a respective challenge pattern may be written via each of said at least two access ports simultaneously to said memory to create said contention.
  • a challenge pattern may be written to said memory via one of said at least two access ports and data is simultaneously read from said memory via another of said at least two access ports.
  • the challenge pattern may be applied to one or both of the at least two access ports and may, for example, comprise one of all O's, all 1 's or a predefined or random pattern of 1 's and O's.
  • the memory may, for example, comprise a dual port memory.
  • each of said components may comprise a cross-coupled loop having an unstable state and at least two stable states.
  • each cross coupled loop may comprise a pair of latches, each latch having an input terminal and an output terminal, said latches being cross-coupled such that the output of a first latch is applied to the input terminal of a second latch and the output of the second latch is applied to the input terminal of the first latch, the excitation signal being applied to a clear input of one of the latches and a preset input of the other latch.
  • the cross- coupled loop could be arranged and configured such that it is in said unstable state when said excitation signal is high and, when said excitation signal goes low, said cross-coupled loop is driven to output one of said at least two stable states.
  • the present invention extends to a system including hardware and/or software arranged and configured to perform the method defined above.
  • a method of providing identification data in respect of a device having challengeable memory comprising the steps of generating a response to a physically unclonable function in respect of said device by means of the method defined above, associating a verification key with said device and generating helper data that maps said response to said physically unclonable function for said device onto said associated verification key.
  • an electronic component comprising an electronic device and means for storing identification data generated by performing the method defined above in respect of said electronic device.
  • the means for storing said identification data may comprise non- volatile memory means.
  • the present invention extends to a method of manufacturing a group of electronic components as defined above, the method comprising manufacturing a plurality of electronic devices, generating a response to a respective physically unclonable function in respect of each of said electronic devices by means of the method as defined above, providing identification data in respect of each of said devices by means of the method defined above, and storing identification data for each of said devices in association with the respective device.
  • the invention extends further to an electronic storage device on which is stored configuration data for configuring a field programmable electronic component as defined above, said configuration data including data representative of said one or more challenge signals used to generate said response to said physically unclonable function according to the method defined above.
  • the invention extends still further to a method of verifying the identity of a device having challengeable memory, the method comprising the steps of generating a response to a physically unclonable function in respect of said device by means of the method defined above, retrieving identification data generated according to the method defined above, performing a key extraction algorithm using said response and the helper data included in said retrieved identification data to extract a key in respect of said electronic device and comparing said extracted key with said verification key associated with said device.
  • the verification key could, for example, be one used for a symmetric key encryption algorithm, a secret key for a public key algorithm, or a secret key for an identification protocol.
  • the present invention is not, however, intended to be limited in this regard.
  • a method of generating a response to a plurality of physically unclonable functions each response being uniquely representative of the identity of a respective device of a plurality of such devices of the same design, each device having challengeable memory, the method comprising applying the same one or more input signals to each memory of said plurality of devices, reading the resulting output data from each said memory, and using said output data from each said memory to generate a respective unique response.
  • each said memory comprises a plurality of logical locations each having at least two possible logical states or values, the method comprising applying said one or more input signals to said plurality of logical locations so as to cause each logical location to occupy one of said at least two states, and reading the resultant output data comprised of the states or values held by said plurality of logical locations as a result of application of said one or more input signals thereto.
  • a method of providing identification data in respect of a plurality of devices of the same design, each device having challengeable memory comprising the steps of generating a respective response to a physically unclonable function in respect of each device by means of the method defined above, associating a unique verification key with each said device and generating helper data that maps the respective response to a physically unclonable function for each said device onto said associated verification key.
  • a method of manufacturing a group of electronic components as defined above comprising manufacturing a plurality of electronic devices, generating a respective response to a physically unclonable function in respect of each of said electronic devices by means of the method defined above, providing identification data in respect of each of said devices by means of the method defined above, and storing identification data for each of said devices in association with the device.
  • the present invention makes use of the fact that the response of several, otherwise identical, programmable electronic devices to the application of the same challenge signal will vary due to the physical characteristics of the device, which vary due to factors such as the production process or age of the device. This variation determines the physically unclonable function for each device.
  • Fig. 1 is a schematic block diagram illustrating the principal steps of a method according to an exemplary embodiment of the present invention for providing identification data in respect of an electronic device (enrolment procedure);
  • Fig. Ia is a schematic block diagram illustrating the principal steps of a method according to an exemplary embodiment of the present invention for verifying the identity of an electronic device having identification data associated therewith (authentication phase);
  • Fig. 2 is a schematic block diagram illustrating a simple dual port memory
  • Fig. 3 is a schematic block diagram illustrating a true dual port memory
  • Fig. 4 is a schematic diagram illustrating a contention in a TDPRAM caused by a simultaneous read via one port from a memory location while writing data to the same memory location from the other port;
  • Fig. 5 is a schematic diagram illustrating a contention in a TDPRAM caused by writing of data to the same memory location simultaneously via the two ports;
  • Fig. 6 is illustrative of a response pattern which may result due to a contention in a TDPRAM caused by writing two fixed challenge patterns to the same memory location simultaneously via the two ports;
  • Fig. 7 is illustrative of a response pattern which may result due to a contention in a TDPRAM caused by writing two different challenge patterns to the same memory location simultaneously via the two ports;
  • Fig. 8 is a schematic circuit diagram illustrating a cross-coupled inverters latch circuit;
  • Fig. 9 illustrates graphically the operating point of the latch of Fig. 8.
  • Fig. 10 is a schematic circuit diagram illustrating a butterfly latch structure, suitable for use in an exemplary embodiment of the present invention.
  • Figs. 11 and 12 show the inter-class hamming distance (variation in hamming distance for measurements performed on the same FPGA) and the inter-class Hamming distance (hamming distance variations for measurements performed on different FPGAs) respectively obtained by experimentation in respect of an exemplary embodiment of the present invention.
  • Dual Port Random Access Memory (DPRAM) cells are widely used as interconnects for two asynchronous processes. They are found, for example, in modern computer systems, video cards and field programmable gate arrays (FPGAs). Furthermore, they are increasingly used as dedicated building blocks in consumer products. DPRAM allow the memory to be accessed simultaneously from two different ports and hence enable multiple systems to access the same data. However, reading and writing to the same memory location from the two ports can lead to a contention which has to be dealt with using arbitration logic. Indeed a person skilled in the art will be aware of other components and devices in which similar contention events can occur for which arbitration logic may be required.
  • arbitration logic in the device hardware is expensive and inflexible. Therefore, most DPRAMs and other devices in which contention is an issue do not implement any arbitration logic in hardware, instead placing the onus on the software to be executed thereby to deal with contention.
  • the inventors have determined that contention results in components and devices of the above- mentioned type vary between individual, otherwise identical devices, based on their respective physical characteristics which vary due to the production process or age of the device.
  • FPGAs Field programmable gate arrays
  • ASICs application-specific integrated circuits
  • FPGA FPGA
  • SRAM static random access memory
  • FPGA Flash
  • PROM programmable Read-Only memory
  • TDPRAM blocks Such TDPRAM blocks tend not to have any built-in arbitration logic to deal with contention events caused by reading and/or writing simultaneously to the same memory location. Thus, such blocks typically demonstrate contention behavior, as will be described in more detail below.
  • the present invention provides a relatively inexpensive technique for protecting the configuration bitstream against pure cloning and, at least to a certain extent, against reverse engineering.
  • the underlying principal of the present invention enables the bitstream to be bound to the particular FPGA it is intended to configure.
  • the present invention has the additional advantage that all of the FPGAs still use the same bitstream (in other words, and in contrast to the prior art, the PUF for each FPGA is generated using the same challenge or input signal/data), which gives a significant cost/compiling benefit.
  • the invention can be implemented without any change to the FPGA hardware.
  • a design d is translated according to the invention into a design d' which has the same functionality as design d but performs some checks on the FPGA on which it is loaded.
  • the bitstream b corresponding to design d is translated, according to the invention, into a bitstream b ' corresponding to design d' (which has the same functionality but performs some additional checks during execution).
  • These checks are intended to determine whether or not the configuration is running on the correct FPGA.
  • the PUF response for each FPGA 2 is obtained (step 102). This step may be repeated one or more times to ensure consistency.
  • the enrolment phase 100 can be performed by the manufacturer at the time of production but can, alternatively, be performed at a later point in time by a trusted third party.
  • the PUF data is derived from the memory response pattern generated due to contention by writing two challenge patterns to the two ports simultaneously, as will now be described in more detail.
  • Dual port memories which are used in different systems vary in the writing and reading capabilities on the two ports.
  • a simple dual port memory 1 allows writing only on one port and reading from two different ports.
  • Dual port memories that are used to interface two processors which have to exchange data require true dual port memories (TDPRAMs).
  • TDPRAMs true dual port memories
  • a TDPRAM 2 has two independent ports for writing and reading data to the same memory location. This enables simultaneous reading from and writing into the memory from two ports. However, as explained above, reading and writing to the same memory location from the two ports can lead to a contention which has to be managed, typically by arbitration logic included in the software running on the systems.
  • contention There are two types of contention that arise in TDPRAMs in the absence of arbitration logic. Firstly, when one port writes to a memory location and the second port reads from the same memory location simultaneously, as illustrated schematically in Figure 4. In this case, the data read out is not predictable although the data is written safely and stored into the specified memory location.
  • the second type of contention arises when both ports attempt to write to the same memory location simultaneously, as illustrated schematically in Figure 5 of the drawings. If different data is being written to the same memory location via two respective ports, then the data actually stored in that memory location will be unpredictable.
  • the unpredictability in both of the above-mentioned types of contention arises due to small differences in timing, capacitance or driving capacities of the internal logic at different memory locations. Such minor differences arise in CMOS gates due to gate delays which are caused by factors such as the unpredictability of the production process or the age of the device.
  • a first challenge pattern A is applied to a first port of a TDPRAM (i) 2 in the form of Data INA and a second challenge pattern B is applied to the second port of the TDPRAM (i) 2 in the form of Data lN ⁇ , the two sets of data being simultaneously written to the same memory location.
  • Data INA comprises all 1 's
  • Data lN ⁇ comprises all O's.
  • other data patterns can be used, as will be described below, and this exemplary embodiment is not intended to be limited in this regard.
  • the data r,(z) stored in the specified memory location as a result of the above- described simultaneous write is then read out and, as shown, the pattern thus read out is very different to both of the data sets written to the memory.
  • the resultant pattern is unpredictable and varies between TDPRAMs due to small differences in timing, capacitance or driving capacities of the internal logic at different memory locations. As explained above, such minor differences arise in CMOS gates due to gate delays which are caused by factors such as the unpredictability of the production process or the age of the device. Thus, contention results tend to be unique for each TDPRAM due to individual device characteristics, and it is this feature which can be exploited in the present invention to enable a PUF to be generated that is inseparably bound to the respective chip and to enable unique chip identification.
  • PUF response data is derived for each SRAM block of an FPGA i from the response pattern (R) generated by contention by writing two challenge patterns to the two ports simultaneously.
  • R response pattern
  • all (or a subset (1,2,3,...n) in any order or combination) of the dual ported SRAM blocks 1 to n of the FPGA are written with different data to the same memory location simultaneously and the resultant data written to that memory location is read out, as shown schematically in Figure 7. It is possible to define 2 2n different patterns for this purpose, where n is the bit size of the respective memory.
  • These patterns could be fixed or random, and may comprise one of the following:
  • Random pattern on port A bitwise inversion of the same pattern on port B Random pattern on port A, random pattern on port B
  • the enrolment phase 100 (and PUF response (R) generation step 102) is performed in respect of all FPGAs in the group.
  • the public helper data H is considered to be public data and should, in this case, be chosen uniformly at random from a large set so as to map the response R to a random code word or verification key. This procedure of choosing a random H and choosing the appropriate verification key happens in a secure environment during the so-called enrolment procedure.
  • a number of verification keys Kj, ...,K n are defined, one for each SRAM block (at step 104), by a trusted third party (TTP) or certification authority, which comprises a company providing the service of protecting bitstreams loaded onto the FPGAs.
  • TTP trusted third party
  • the verification keys each comprise an algorithmic pattern which, in this exemplary embodiment of the present invention, is embedded in the configuration data stored in the non- volatile memory associated with the device to be configured.
  • the concept of a key here is intended to signify the unique pattern K 1 derived from the SRAM block. In practice, one or more cryptographic keys can be derived from this pattern K 1 . In addition, this will be application dependent.
  • main helper data Wi(i),...,W n (i) is computed for each SRAM block 1 to n of every FPGA i.
  • Each item of helper data W ⁇ ⁇ ) is calculated such that the output r y (z) read from SRAM blocky of FPGA i leads, together with the public helper data H, to the respective verification key K 1 .
  • main helper data W 1 indicating, for example, which memory locations or block(s) of RAM are under consideration, or how many bits of each RAM are being considered.
  • the helper data Wi(i),...,W n (i) for SRAM blocks 1 to n is stored on the non- volatile memory that contains the design (i.e. configuration bitstream) for FPGA i.
  • the design d i.e. the unmodified configuration bitstream for FPGA ⁇
  • the bitstream d has some additional instructions added thereto which, when loaded onto the FPGA i, perform the verification checks that will now be described with reference to Figure Ia.
  • the FPGA i in response to receipt of d', the FPGA i simultaneously writes the respective challenge patterns A and B (provided in d') to both ports simultaneously of each SRAM block 1 to n (or a subset of these SRAM blocks), and reads the written data so as to obtain the respective PUF response (R') (at step 110) for FPGA i.
  • This is preferably done by reading the TDPRAM data from random locations in the memory, details of which random locations would need to be hidden in the final bitstream. Alternatively, the random locations can be included in the helper data.
  • the appropriate helper data Wi(i),...,W n (i) is loaded from the non-volatile memory (at step 112) and a key extraction algorithm is run at step 114 (based on the PUF output and the helper data), which leads to a verification key K 1
  • a fuzzy extractor/helper data algorithm could be used to derive the verification key. Going back to this illustrative example, if the number of errors is within the error correcting capabilities of the error correcting code, then a decoding procedure can be used to obtain C.
  • a check is performed on the validity of the extracted key K 1 ' at step 116.
  • One method of performing the above-mentioned check on the extracted key K 1 ' in respect of this exemplary embodiment is as follows. As stated above, in this case, the original key K 1 is embedded in the configuration code and is the same for all of the FPGAs (thus, the design is always the same). A check is performed to determine whether or not the extracted key K 1 ' is the same as the embedded key K 1 . If so, the program continues. If not, some other appropriate measure can be taken.
  • Such measures include, but are by no means limited to: resetting the entire FPGA; resetting certain areas of the memory; stopping the controller and forcing it into a so-called 'dead' state (from which it cannot return); - disabling certain parts of the main design, thereby offering a solution with less functionality; producing random outputs that are completely uncorrelated to the operations performed by the main design; erasing the contents of the non- volatile memories, where the original configuration file for the FPGA is stored and then rest; any combination of the above procedures.
  • the check could be more sophisticated by checking another function F of the extracted key and embedded keys.
  • a function F could be a cryptographic function such as a one-way or encryption function using K as a key and a standard message m as plain text.
  • Cross-coupled circuits are widely used in electronic circuits to implement storage elements like latches, flip-flops and SRAM memory.
  • a cross-coupled circuit when constructed properly can create a positive- feedback loop to store a desired bit value.
  • Such circuits are used in all kinds of devices like FPGAs, ASICs and other embedded devices.
  • a cross-coupled circuit is a basic building block for almost all kinds of storage elements in electronic circuits like latches, flip-flops and SRAM memories.
  • a cross-coupled circuit is constructed such that it provides a positive-feedback to store the required bit value within the loop.
  • An example of such a circuit is a simple latch built using two cross-coupled inverters as shown in Figure 8.
  • cross-coupled circuits have two different stable operating points (to store the bit value) and an unstable operating point as shown in Figure 9.
  • the circuit can be relatively easily driven from the unstable state to a stable state by an external signal on the input or due to slight differences in the elements used to build the circuit (here inverters).
  • This fact can be used in accordance with a second exemplary embodiment of the invention to build a PUF where the circuit is initially at the unstable operating point and let to attain one of the two stable operating points without any external excitation.
  • Different cross-coupled devices can be built using different elements like NOR gates or NAND gates.
  • a cross-coupled combinational loop can be simulated using latches present in the FPGA.
  • a butterfly structure may be created using the latches that allows for an unstable state by an excite signal and settles down to one of the two stable states after some time.
  • the structure of the circuit is as shown in Figure 10. It consists of two latches, each with preset PRE (set Q to 1 on high) and clear CLR (set Q to 0 on high) input. The data D is transferred on the output Q when the CLK is high.
  • the PRE of Latch 1 and CLR of Latch 2 are always set to low.
  • the excite signal is connected to CLR of Latch 1 and PRE of Latch 2.
  • the outputs of the latch are cross-coupled and we set CLK to both latches to high always effectively simulating a combinational loop.
  • the output out is either one of the stable states 0 or 1.
  • the configuration bitstream may be encrypted and, once K 1 ' has been extracted and verified, it may be used to decrypt the bitstream.
  • K 1 ' has been extracted and verified
  • the resulting bitstream may be used to reconfigure the device on which it was originally loaded or part of the device.
  • the key generated/extracted from the PUF is used to encrypt some program instructions to a computer program for a processor configured on the device.
  • the key generated/extracted from the PUF is used to encrypt or decrypt data generated by other circuitry configured on the device and later used as the output of another operation.
  • a Message Authentication Code (MAC) or digital signature derived from a public-key signature algorithm may be computed in respect of the key extracted using the PUF or just the PUF data during the enrolment phase.
  • This MAC or digital signature can be stored on a memory external to the device and later compared with a value that is computed during bitstream authentication.
  • the private or secret key can be stored within the configuration file of the FPGA.
  • the methods of PUF generation and verification are used in relation to preventing clonability of field programmable logic devices.
  • the PUF data generated according to a method of the present invention may be used as a seed to a pseudo-random number generator or as the key for a private or public key encryption algorithm.
  • the present invention could also be used for tracking purposes as each device has its own identifiable PUF.
  • the method of generating a PUF according to the first exemplary embodiment of the invention is not limited to the use of dual ported RAM but can be used in any device where contention results are based on the physical characteristics of the device which vary due to factors such as the production process or age of the device; and the method of generating a PUF according to the second exemplary embodiment of the invention is not limited to the described butterfly latch structures but can employ any cross-coupled loops which have an unstable state and two stable states.
  • any reference signs placed in parentheses shall not be construed as limiting the claims.
  • the word “comprising” and “comprises”, and the like, does not exclude the presence of elements or steps other than those listed in any claim or the specification as a whole.
  • the singular reference of an element does not exclude the plural reference of such elements and vice-versa.
  • the invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In a device claim enumerating several means, several of these means may be embodied by one and the same item of hardware.
  • the mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Security & Cryptography (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Mathematical Physics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Pure & Applied Mathematics (AREA)
  • Mathematical Optimization (AREA)
  • Power Engineering (AREA)
  • Mathematical Analysis (AREA)
  • Computational Mathematics (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Storage Device Security (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

A method of generating a response to a physically unclonable function, said response being uniquely representative of the identity of a device (2) having challengeable memory, the memory comprising a plurality of logical locations each having at least two possible logical states, the method comprising applying a challenge signal (A,B) to an input of said memory so as to cause each of said logical locations to enter one of said two possible logical states and thereby generate a response pattern of logical states, said response pattern (R) being dependent on said physically unclonable function which is defined by, the physical characteristics of said memory, the method further comprising reading out said response pattern (R).

Description

Identification of devices using physically unclonable functions
FIELD OF THE INVENTION
This invention relates to a technique for generating a response to a physically unclonable function (PUF), particularly for use in identification of devices having challengeable memory and especially, but not necessarily exclusively, suitable for use in preventing cloning of such devices.
BACKGROUND OF THE INVENTION
Physically unclonable functions (PUFs) are essentially random functions bound to a physical device in such a way that it is computationally and physically infeasible to predict the output of the function without actually evaluating it using the physical device. In other words, a Physically Unclonable Function (PUF) is realized by a physical system, such that the function is relatively easy to evaluate but the physical system is hard to characterize and hard to clone. Since a PUF cannot be copied or modeled, a device equipped with a PUF becomes unclonable. Physical systems that are produced by an uncontrolled production process (i.e. one that contains some randomness) are good candidates for PUFs. In this case, for example, a PUF computes its output by exploiting the inherent variability of wire delays and gate delays in manufactured circuits. These delays in turn depend on highly unpredictable factors, such as manufacturing variations, quantum mechanical fluctuations, thermal gradients, electromigration effects, parasitics, noise, etc. A good PUF is therefore not likely to be modeled succinctly, nor be predicted or replicated, even using identical hardware (which will still have different random manufacturing variations and associated delays, and thus yield an implemented function different from the first).
Field configurable devices, such as field programmable gate arrays (FPGAs), are typically configured using data, usually called a configuration bitstream or simply a bitstream, that is supplied to the device after the device is deployed in an application. For example, the configuration data may be provided to the device when the device is powered on. Significant revenue is lost due to issues such as cloning of such devices and/or unreported over-production thereof. As such, it is highly desirable to be able to uniquely identify a particular device and/or prevent configuration thereof with unauthorized configuration data. One example of a PUF is known as a Coating PUF which is created by covering an IC with a coating that is doped with random dielectric particles. These particles have different dielectric constants (related to their chemistry) and have random sizes and shapes due to the production process. The top metal layer of the IC contains a matrix of sensor structures, which enables the local capacitance values at several positions on the coating to be measured and capacitance measurements at several coating locations (i.e. different challenges) can be used to derive a cryptographic key that can be used by the IC (internally) for several cryptographic purposes.
The PUF' s physical system is designed such that it interacts in a particular way with stimuli (challenges) and leads to unique but unpredictable responses. A PUF challenge and the corresponding response are together called a Challenge-Response pair. US Patent Application Publication No. US 2006/0209584 Al describes a field programmable gate array (FPGA) having a PUF module. The PUF module has a PUF circuit configured to generate a PUF response to a challenge signal. The module is designed such that when deployed in the field, the response for a particular challenge is difficult to determine from the device.
Configuration data, encrypted by the providing party using a secret key, is provided to the device in the field together with a challenge code and an access code derived from a combination of the secret key and the respective PUF response for an authorized device. The challenge code is used by the PUF circuit to generate a PUF response and this response is used, together with the access code, to reconstruct the secret key which, if the device is an authorized device, will enable the configuration data to be decrypted and the device to be configured.
However, this requires the creation of a unique bitstream to each FPGA in order to ensure that the correct response is achieved therefrom. This can be a complex process and has adverse cost implications.
Thus, it is one object of the present invention to provide an improved method for generating a unique response to a physically unclonable function in respect of each of a group of electronic devices having challengeable memory, using the same challenge signal, such that the configuration data (including data representative of the challenge signal) used to configure the electronic devices in the field can be the same for all of the devices.
SUMMARY OF THE INVENTION
In accordance with the present invention there is provided a method of generating a response to a physically unclonable function, said response being uniquely representative of the identity of a device having challengeable memory, the memory comprising a plurality of logical locations each having at least two possible logical states, the method comprising applying a challenge signal to an input of said memory so as to cause each of said logical locations to enter one of said two possible logical states and thereby generate a response pattern of logical states, said response pattern being dependent on said physically unclonable function which is defined by the physical characteristics of said memory, the method further comprising reading out said response pattern.
In a first exemplary embodiment, said memory has at least two access ports, the method comprising accessing said plurality of logical storage locations via said at least two access ports so as to create a contention, and using resulting response data read from said logical locations to generate said response to said physically unclonable function.
In a second exemplary embodiment, the memory comprises an array of components having an unstable state and at least two stable states, the method comprising applying an excitation signal to each of said components so as to drive each of said components into a respective one of said at least two stable states, and generating output data comprised of the resultant response data comprised of the resultant response data comprised of the combination of respective states of said components to generate said response to said physically unclonable function. In accordance with the first exemplary embodiment, data in the form of a challenge pattern may be written to at least one of the at least two access ports, and the resulting response pattern stored in said memory is read out and used to generate said response to said physically unclonable function. In this case, a respective challenge pattern may be written via each of said at least two access ports simultaneously to said memory to create said contention. Alternatively, a challenge pattern may be written to said memory via one of said at least two access ports and data is simultaneously read from said memory via another of said at least two access ports. The challenge pattern may be applied to one or both of the at least two access ports and may, for example, comprise one of all O's, all 1 's or a predefined or random pattern of 1 's and O's. The memory may, for example, comprise a dual port memory.
In accordance with the second exemplary embodiment, each of said components may comprise a cross-coupled loop having an unstable state and at least two stable states. In this case, each cross coupled loop may comprise a pair of latches, each latch having an input terminal and an output terminal, said latches being cross-coupled such that the output of a first latch is applied to the input terminal of a second latch and the output of the second latch is applied to the input terminal of the first latch, the excitation signal being applied to a clear input of one of the latches and a preset input of the other latch. The cross- coupled loop could be arranged and configured such that it is in said unstable state when said excitation signal is high and, when said excitation signal goes low, said cross-coupled loop is driven to output one of said at least two stable states.
The present invention extends to a system including hardware and/or software arranged and configured to perform the method defined above.
Also, in accordance with the present invention, there is provided a method of providing identification data in respect of a device having challengeable memory, comprising the steps of generating a response to a physically unclonable function in respect of said device by means of the method defined above, associating a verification key with said device and generating helper data that maps said response to said physically unclonable function for said device onto said associated verification key. Further, in accordance with the present invention, there is provided an electronic component comprising an electronic device and means for storing identification data generated by performing the method defined above in respect of said electronic device. The means for storing said identification data may comprise non- volatile memory means. The present invention extends to a method of manufacturing a group of electronic components as defined above, the method comprising manufacturing a plurality of electronic devices, generating a response to a respective physically unclonable function in respect of each of said electronic devices by means of the method as defined above, providing identification data in respect of each of said devices by means of the method defined above, and storing identification data for each of said devices in association with the respective device.
The invention extends further to an electronic storage device on which is stored configuration data for configuring a field programmable electronic component as defined above, said configuration data including data representative of said one or more challenge signals used to generate said response to said physically unclonable function according to the method defined above.
The invention extends still further to a method of verifying the identity of a device having challengeable memory, the method comprising the steps of generating a response to a physically unclonable function in respect of said device by means of the method defined above, retrieving identification data generated according to the method defined above, performing a key extraction algorithm using said response and the helper data included in said retrieved identification data to extract a key in respect of said electronic device and comparing said extracted key with said verification key associated with said device. The verification key could, for example, be one used for a symmetric key encryption algorithm, a secret key for a public key algorithm, or a secret key for an identification protocol. The present invention is not, however, intended to be limited in this regard.
Also, in accordance with the present invention, there is provided a method of generating a response to a plurality of physically unclonable functions, each response being uniquely representative of the identity of a respective device of a plurality of such devices of the same design, each device having challengeable memory, the method comprising applying the same one or more input signals to each memory of said plurality of devices, reading the resulting output data from each said memory, and using said output data from each said memory to generate a respective unique response.
Preferably, each said memory comprises a plurality of logical locations each having at least two possible logical states or values, the method comprising applying said one or more input signals to said plurality of logical locations so as to cause each logical location to occupy one of said at least two states, and reading the resultant output data comprised of the states or values held by said plurality of logical locations as a result of application of said one or more input signals thereto.
Also, in accordance with the present invention, there is provided a method of providing identification data in respect of a plurality of devices of the same design, each device having challengeable memory, the method comprising the steps of generating a respective response to a physically unclonable function in respect of each device by means of the method defined above, associating a unique verification key with each said device and generating helper data that maps the respective response to a physically unclonable function for each said device onto said associated verification key.
Also, in accordance with the present invention, there is provided a method of manufacturing a group of electronic components as defined above, the method comprising manufacturing a plurality of electronic devices, generating a respective response to a physically unclonable function in respect of each of said electronic devices by means of the method defined above, providing identification data in respect of each of said devices by means of the method defined above, and storing identification data for each of said devices in association with the device.
Thus, in general, the present invention makes use of the fact that the response of several, otherwise identical, programmable electronic devices to the application of the same challenge signal will vary due to the physical characteristics of the device, which vary due to factors such as the production process or age of the device. This variation determines the physically unclonable function for each device.
These and other aspects of the present invention will be apparent from, and elucidated with reference to, the embodiments described herein.
BRIEF DESCRIPTION OF THE DRAWINGS
Embodiments of the present invention will now be described by way of examples only and with reference to the accompanying drawings, in which:
Fig. 1 is a schematic block diagram illustrating the principal steps of a method according to an exemplary embodiment of the present invention for providing identification data in respect of an electronic device (enrolment procedure);
Fig. Ia is a schematic block diagram illustrating the principal steps of a method according to an exemplary embodiment of the present invention for verifying the identity of an electronic device having identification data associated therewith (authentication phase);
Fig. 2 is a schematic block diagram illustrating a simple dual port memory; Fig. 3 is a schematic block diagram illustrating a true dual port memory; Fig. 4 is a schematic diagram illustrating a contention in a TDPRAM caused by a simultaneous read via one port from a memory location while writing data to the same memory location from the other port;
Fig. 5 is a schematic diagram illustrating a contention in a TDPRAM caused by writing of data to the same memory location simultaneously via the two ports;
Fig. 6 is illustrative of a response pattern which may result due to a contention in a TDPRAM caused by writing two fixed challenge patterns to the same memory location simultaneously via the two ports;
Fig. 7 is illustrative of a response pattern which may result due to a contention in a TDPRAM caused by writing two different challenge patterns to the same memory location simultaneously via the two ports; Fig. 8 is a schematic circuit diagram illustrating a cross-coupled inverters latch circuit;
Fig. 9 illustrates graphically the operating point of the latch of Fig. 8;
Fig. 10 is a schematic circuit diagram illustrating a butterfly latch structure, suitable for use in an exemplary embodiment of the present invention;
Figs. 11 and 12 show the inter-class hamming distance (variation in hamming distance for measurements performed on the same FPGA) and the inter-class Hamming distance (hamming distance variations for measurements performed on different FPGAs) respectively obtained by experimentation in respect of an exemplary embodiment of the present invention.
DETAILED DESCRIPTION
In the following, reference is made to dual port random access memory devices and true dual port random access memory devices (DPRAMs and TDPRAMs respectively). It will, however, be appreciated that the present invention is equally applicable to the unique identification (and/or prevention of cloning) of any logic device including a component in which contention may occur, where contention results are based on the physical characteristics of the device which vary due to the inherent variability in wire delays and gate delays caused by factors such as the production process or the age of the device, and the present invention is not intended to be limited in this regard.
Dual Port Random Access Memory (DPRAM) cells are widely used as interconnects for two asynchronous processes. They are found, for example, in modern computer systems, video cards and field programmable gate arrays (FPGAs). Furthermore, they are increasingly used as dedicated building blocks in consumer products. DPRAM allow the memory to be accessed simultaneously from two different ports and hence enable multiple systems to access the same data. However, reading and writing to the same memory location from the two ports can lead to a contention which has to be dealt with using arbitration logic. Indeed a person skilled in the art will be aware of other components and devices in which similar contention events can occur for which arbitration logic may be required.
Implementing arbitration logic in the device hardware is expensive and inflexible. Therefore, most DPRAMs and other devices in which contention is an issue do not implement any arbitration logic in hardware, instead placing the onus on the software to be executed thereby to deal with contention. In accordance with a first exemplary embodiment of the invention, the inventors have determined that contention results in components and devices of the above- mentioned type vary between individual, otherwise identical devices, based on their respective physical characteristics which vary due to the production process or age of the device.
Field programmable gate arrays (FPGAs) are widely used for prototyping of electronic designs and algorithms. Furthermore, they are increasingly used as dedicated electronic building blocks in consumer products. Their main advantage compared with ASICs (application-specific integrated circuits) is their flexibility, as they can be reconfigured in the field.
A popular type of FPGA is the SRAM based FPGA. This type of FPGA chip has only volatile memory on board and hence loses its configuration when the power is switched off. On power-up, the FPGA is configured by means of a bit stream that is loaded from an external non-volatile memory (e.g. programmable Read-Only memory(PROM), Flash, etc). These FPGAs now also have embedded true dual-ported SRAM blocks in different amounts and configurations. Such TDPRAM blocks tend not to have any built-in arbitration logic to deal with contention events caused by reading and/or writing simultaneously to the same memory location. Thus, such blocks typically demonstrate contention behavior, as will be described in more detail below. The present invention provides a relatively inexpensive technique for protecting the configuration bitstream against pure cloning and, at least to a certain extent, against reverse engineering. The underlying principal of the present invention enables the bitstream to be bound to the particular FPGA it is intended to configure. The present invention has the additional advantage that all of the FPGAs still use the same bitstream (in other words, and in contrast to the prior art, the PUF for each FPGA is generated using the same challenge or input signal/data), which gives a significant cost/compiling benefit. Furthermore, the invention can be implemented without any change to the FPGA hardware.
In summary, a design d is translated according to the invention into a design d' which has the same functionality as design d but performs some checks on the FPGA on which it is loaded. This implies that the bitstream b corresponding to design d is translated, according to the invention, into a bitstream b ' corresponding to design d' (which has the same functionality but performs some additional checks during execution). These checks are intended to determine whether or not the configuration is running on the correct FPGA. Referring to Figure 1 of the drawings, in a method according to an exemplary embodiment of the present invention, during an enrolment phase 100, the PUF response for each FPGA2 is obtained (step 102). This step may be repeated one or more times to ensure consistency. The enrolment phase 100 can be performed by the manufacturer at the time of production but can, alternatively, be performed at a later point in time by a trusted third party. The PUF data is derived from the memory response pattern generated due to contention by writing two challenge patterns to the two ports simultaneously, as will now be described in more detail.
Dual port memories which are used in different systems vary in the writing and reading capabilities on the two ports. Referring to Figure 2 of the drawings, a simple dual port memory 1 allows writing only on one port and reading from two different ports. Dual port memories that are used to interface two processors which have to exchange data require true dual port memories (TDPRAMs). Referring to Figure 3, a TDPRAM 2 has two independent ports for writing and reading data to the same memory location. This enables simultaneous reading from and writing into the memory from two ports. However, as explained above, reading and writing to the same memory location from the two ports can lead to a contention which has to be managed, typically by arbitration logic included in the software running on the systems.
There are two types of contention that arise in TDPRAMs in the absence of arbitration logic. Firstly, when one port writes to a memory location and the second port reads from the same memory location simultaneously, as illustrated schematically in Figure 4. In this case, the data read out is not predictable although the data is written safely and stored into the specified memory location. The second type of contention arises when both ports attempt to write to the same memory location simultaneously, as illustrated schematically in Figure 5 of the drawings. If different data is being written to the same memory location via two respective ports, then the data actually stored in that memory location will be unpredictable. The unpredictability in both of the above-mentioned types of contention arises due to small differences in timing, capacitance or driving capacities of the internal logic at different memory locations. Such minor differences arise in CMOS gates due to gate delays which are caused by factors such as the unpredictability of the production process or the age of the device.
In the following description, the contention caused by writing different data to the same memory location via the two ports (Figure 5) will be described in more detail. However, it will be appreciated that the type of contention illustrated and described with reference to Figure 4 is equally applicable to this exemplary embodiment of the present invention.
Referring to Figure 6 of the drawings, a first challenge pattern A is applied to a first port of a TDPRAM (i) 2 in the form of Data INA and a second challenge pattern B is applied to the second port of the TDPRAM (i) 2 in the form of Data lNβ, the two sets of data being simultaneously written to the same memory location. In the example shown, Data INA comprises all 1 's and Data lNβ comprises all O's. However, other data patterns can be used, as will be described below, and this exemplary embodiment is not intended to be limited in this regard. The data r,(z) stored in the specified memory location as a result of the above- described simultaneous write is then read out and, as shown, the pattern thus read out is very different to both of the data sets written to the memory. The resultant pattern is unpredictable and varies between TDPRAMs due to small differences in timing, capacitance or driving capacities of the internal logic at different memory locations. As explained above, such minor differences arise in CMOS gates due to gate delays which are caused by factors such as the unpredictability of the production process or the age of the device. Thus, contention results tend to be unique for each TDPRAM due to individual device characteristics, and it is this feature which can be exploited in the present invention to enable a PUF to be generated that is inseparably bound to the respective chip and to enable unique chip identification. Returning now to Figure 1, during the enrolment phase 100, PUF response data is derived for each SRAM block of an FPGA i from the response pattern (R) generated by contention by writing two challenge patterns to the two ports simultaneously. In other words, all (or a subset (1,2,3,...n) in any order or combination) of the dual ported SRAM blocks 1 to n of the FPGA are written with different data to the same memory location simultaneously and the resultant data written to that memory location is read out, as shown schematically in Figure 7. It is possible to define 22n different patterns for this purpose, where n is the bit size of the respective memory. These patterns could be fixed or random, and may comprise one of the following:
All O's port A, all I ' s port B - All 1 's port A, all O's port B (as in the example illustrated in Figure 6)
Random pattern on port A, bitwise inversion of the same pattern on port B Random pattern on port A, random pattern on port B
First store a fixed or random value in the memory location and then perform any one of the above combinations. However, it will be appreciated that this list of possibilities is not exhaustive and other options will be apparent to a person skilled in the art.
The enrolment phase 100 (and PUF response (R) generation step 102) is performed in respect of all FPGAs in the group. After obtaining the contention response R from each PUF, respective public helper data H is selected such that C = R XOR H, where C is the code word of an error correcting code (i.e. a verification key). The public helper data H is considered to be public data and should, in this case, be chosen uniformly at random from a large set so as to map the response R to a random code word or verification key. This procedure of choosing a random H and choosing the appropriate verification key happens in a secure environment during the so-called enrolment procedure. A number of verification keys Kj, ...,Kn are defined, one for each SRAM block (at step 104), by a trusted third party (TTP) or certification authority, which comprises a company providing the service of protecting bitstreams loaded onto the FPGAs. As will be well known to a person skilled in the art, the verification keys each comprise an algorithmic pattern which, in this exemplary embodiment of the present invention, is embedded in the configuration data stored in the non- volatile memory associated with the device to be configured. The concept of a key here is intended to signify the unique pattern K1 derived from the SRAM block. In practice, one or more cryptographic keys can be derived from this pattern K1. In addition, this will be application dependent. Finally, main helper data Wi(i),...,Wn(i) is computed for each SRAM block 1 to n of every FPGA i. Each item of helper data W}{ϊ) is calculated such that the output ry(z) read from SRAM blocky of FPGA i leads, together with the public helper data H, to the respective verification key K1.
The general concept of computing helper data for this purpose is known to persons skilled in the art and alternative methods and implementations thereof are described more fully in, for example, J.P. Linnartz, P. Tuyls, 'New Shielding Functions to Enhance Privacy and Prevent Misuse of Biometric Templates', In J. Kittler and M. Nixon, editors, Proceedings of the 3rd Conference on Audio and Video Based Person Authentication, volume 2688 of Lecture Notes in Computer Science, pages 238-250, Springer- Verlag, 2003 and Y. Dodis et al, 'Fuzzy extractors: How to generate strong keys from biometrics and other noisy data', Advances in cryptology - Eurocrypt 2004, Ser. LNCS, C.Cahin and J. Camenisch, Eds., vol.3027. Springer- Verlag, 2004, pp. 523-540. In practice, other information can be included in the main helper data W1 indicating, for example, which memory locations or block(s) of RAM are under consideration, or how many bits of each RAM are being considered.
The helper data Wi(i),...,Wn(i) for SRAM blocks 1 to n is stored on the non- volatile memory that contains the design (i.e. configuration bitstream) for FPGA i.
In a next step, the design d (i.e. the unmodified configuration bitstream for FPGA ϊ) is converted into a modified design d' by adding some verification checks. In more detail, the bitstream d has some additional instructions added thereto which, when loaded onto the FPGA i, perform the verification checks that will now be described with reference to Figure Ia.
Referring to Figure Ia, during the authentication phase, in response to receipt of d', the FPGA i simultaneously writes the respective challenge patterns A and B (provided in d') to both ports simultaneously of each SRAM block 1 to n (or a subset of these SRAM blocks), and reads the written data so as to obtain the respective PUF response (R') (at step 110) for FPGA i. This is preferably done by reading the TDPRAM data from random locations in the memory, details of which random locations would need to be hidden in the final bitstream. Alternatively, the random locations can be included in the helper data. Next, the appropriate helper data Wi(i),...,Wn(i) is loaded from the non-volatile memory (at step 112) and a key extraction algorithm is run at step 114 (based on the PUF output and the helper data), which leads to a verification key K1 For the case identified above, this involves 'XORing' the response R' with the helper data H to obtain a code word C. It will be appreciated here that alternative methods of obtaining C are possible. For example, a fuzzy extractor/helper data algorithm could be used to derive the verification key. Going back to this illustrative example, if the number of errors is within the error correcting capabilities of the error correcting code, then a decoding procedure can be used to obtain C. Otherwise, if there are too many errors, then the decoding procedure of the error correcting code returns an invalid/error signal and stops. 'Thus, in this final step, a check is performed on the validity of the extracted key K1 ' at step 116. One method of performing the above-mentioned check on the extracted key K1' in respect of this exemplary embodiment is as follows. As stated above, in this case, the original key K1 is embedded in the configuration code and is the same for all of the FPGAs (thus, the design is always the same). A check is performed to determine whether or not the extracted key K1 ' is the same as the embedded key K1. If so, the program continues. If not, some other appropriate measure can be taken. Such measures include, but are by no means limited to: resetting the entire FPGA; resetting certain areas of the memory; stopping the controller and forcing it into a so-called 'dead' state (from which it cannot return); - disabling certain parts of the main design, thereby offering a solution with less functionality; producing random outputs that are completely uncorrelated to the operations performed by the main design; erasing the contents of the non- volatile memories, where the original configuration file for the FPGA is stored and then rest; any combination of the above procedures.
In an alternative embodiment, although the method for verifying the extracted key involves a check that K1 '=KP an alternative method might involve checking that d(Kj \Kj)<=t where d is an appropriate distance function (e.g. Hamming distance) and t some predefined thresho Id.
Although relatively straightforward methods of verifying the extracted key are envisaged and mentioned above, other methods of verifying the validity of the extracted key will be apparent to a person skilled in the art, and the present invention is not intended to be limited in this regard. For example, the check could be more sophisticated by checking another function F of the extracted key and embedded keys. Such a function F could be a cryptographic function such as a one-way or encryption function using K as a key and a standard message m as plain text.
It will be further appreciated that, while the present invention has been described above in terms of combining the creation of a configuration bitstream with the PUF extraction algorithm, this is not essential. Applications are envisaged whereby the PUF extraction algorithm is performed without the configuration bitstream.
Cross-coupled circuits are widely used in electronic circuits to implement storage elements like latches, flip-flops and SRAM memory. A cross-coupled circuit when constructed properly can create a positive- feedback loop to store a desired bit value. Such circuits are used in all kinds of devices like FPGAs, ASICs and other embedded devices.
A cross-coupled circuit is a basic building block for almost all kinds of storage elements in electronic circuits like latches, flip-flops and SRAM memories. A cross-coupled circuit is constructed such that it provides a positive-feedback to store the required bit value within the loop. An example of such a circuit is a simple latch built using two cross-coupled inverters as shown in Figure 8.
However, such cross-coupled circuits have two different stable operating points (to store the bit value) and an unstable operating point as shown in Figure 9. The circuit can be relatively easily driven from the unstable state to a stable state by an external signal on the input or due to slight differences in the elements used to build the circuit (here inverters). This fact can be used in accordance with a second exemplary embodiment of the invention to build a PUF where the circuit is initially at the unstable operating point and let to attain one of the two stable operating points without any external excitation. We find that with a high probability the circuit goes more to one of the operating points based on small differences in the wire delays and the voltage transfer characteristics of the cross-coupled element (in this case an inverter). Different cross-coupled devices can be built using different elements like NOR gates or NAND gates.
Implementing a cross-coupled element using combinational logic on FPGA is not necessarily straightforward due to the inability to create combinational loops. To overcome this problem, a cross-coupled combinational loop can be simulated using latches present in the FPGA. In one exemplary embodiment, a butterfly structure may be created using the latches that allows for an unstable state by an excite signal and settles down to one of the two stable states after some time. The structure of the circuit is as shown in Figure 10. It consists of two latches, each with preset PRE (set Q to 1 on high) and clear CLR (set Q to 0 on high) input. The data D is transferred on the output Q when the CLK is high. The PRE of Latch 1 and CLR of Latch 2 are always set to low. The excite signal is connected to CLR of Latch 1 and PRE of Latch 2. The outputs of the latch are cross-coupled and we set CLK to both latches to high always effectively simulating a combinational loop. When excite goes high, the circuit is in an unstable operating point and after excite goes to low, the output out is either one of the stable states 0 or 1.
By the construction of an array of 128 butterfly structures on a Spartan-3e Xilinx FPGA, experimental results show that for the same FPGA the hamming distance is at most 9% and for different FPGA (done with 5 FPGAs) is at least 23%. This can be seen from Figures 11 and 12, which show both the intra-class hamming distance (variation in hamming distance for measurements performed on the same FPGA) and the inter-class Hamming distance (hamming distance variations for measurements performed on different FPGAs). As a result, by applying the same challenge signal to the cross-coupled loops of each array, a unique PUF (made up of the combination of resultant states of each loop) representative of the respective FPGA can be generated.
Once the PUF has been generated in this manner, the remainder of the enrolment phase and the authentication phase for preventing clonability of FPGAs can be the same as that described in relation to Figures 1 and Ia.
It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be capable of designing many alternative embodiments without departing from the scope of the invention as defined by the appended claims.
For example, before the configuration bitstream is stored in the non- volatile memory of the device, it may be encrypted and, once K1' has been extracted and verified, it may be used to decrypt the bitstream. In one exemplary embodiment, once a device has been configured by a bitstream, it may be used to configure a second device. In an alternative embodiment, the resulting bitstream may be used to reconfigure the device on which it was originally loaded or part of the device. In another exemplary embodiment, the key generated/extracted from the PUF is used to encrypt some program instructions to a computer program for a processor configured on the device. In another exemplary embodiment, the key generated/extracted from the PUF is used to encrypt or decrypt data generated by other circuitry configured on the device and later used as the output of another operation. In yet another exemplary embodiment, a Message Authentication Code (MAC) or digital signature derived from a public-key signature algorithm may be computed in respect of the key extracted using the PUF or just the PUF data during the enrolment phase. This MAC or digital signature can be stored on a memory external to the device and later compared with a value that is computed during bitstream authentication. In the case of a MAC, the private or secret key can be stored within the configuration file of the FPGA.
In the exemplary embodiments described in detail above, the methods of PUF generation and verification are used in relation to preventing clonability of field programmable logic devices. However, a much broader scope of potential applications is envisaged. For example, the PUF data generated according to a method of the present invention may be used as a seed to a pseudo-random number generator or as the key for a private or public key encryption algorithm. The present invention could also be used for tracking purposes as each device has its own identifiable PUF. Finally, the method of generating a PUF according to the first exemplary embodiment of the invention is not limited to the use of dual ported RAM but can be used in any device where contention results are based on the physical characteristics of the device which vary due to factors such as the production process or age of the device; and the method of generating a PUF according to the second exemplary embodiment of the invention is not limited to the described butterfly latch structures but can employ any cross-coupled loops which have an unstable state and two stable states.
In the claims, any reference signs placed in parentheses shall not be construed as limiting the claims. The word "comprising" and "comprises", and the like, does not exclude the presence of elements or steps other than those listed in any claim or the specification as a whole. The singular reference of an element does not exclude the plural reference of such elements and vice-versa. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed computer. In a device claim enumerating several means, several of these means may be embodied by one and the same item of hardware. The mere fact that certain measures are recited in mutually different dependent claims does not indicate that a combination of these measures cannot be used to advantage.

Claims

CLAIMS:
1. A method of generating a response to a physically unclonable function, said response being uniquely representative of the identity of a device having challengeable memory, the memory comprising a plurality of logical locations each having at least two possible logical states, the method comprising applying a challenge signal to an input of said electronic device so as to cause each of said logical locations to enter one of said two possible logical states and thereby generate a response pattern of logical states, said response pattern being dependent on, and defined by, the physical characteristics of said memory, the method further comprising reading out said response pattern.
2. A method according to claim 1, wherein said memory has at least two access ports, the method comprising accessing said plurality of logical locations of said memory via said at least two access ports simultaneously so as to create a contention, and using resultant response data read from said logical locations to generate said response to said physically unclonable function.
3. A method according to claim 1, wherein said memory comprises an array of components each having an unstable state and at least two stable states, the method comprising applying an excitation signal to each of said components so as to drive each of said components into a respective one of said at least two stable states, and using resulting response data comprised of the combination of respective states of said components to generate said response to said physically unclonable function.
4. A method according to claim 2, wherein data in the form of a challenge pattern is written to at least one of the at least two access ports, and the resulting response pattern stored in said memory is read out and used to generate said response to said physically unclonable function.
5. A method according to claim 4, wherein a respective challenge pattern is written via each of said at least two access ports simultaneously to said memory to create said contention.
6. A method according to claim 4, wherein a challenge pattern is written to said memory via one of said at least two access ports and data is simultaneously read from said memory via another of said at least two access ports.
7. A method according to claim 4, wherein the challenge pattern applied to one or both of the at least two access ports comprises one of all O's, all 1 's or a predefined or random pattern of 1 's and O's.
8. A method according to claim 2, wherein said memory comprises a dual port memory 2.
9. A method according to claim 3, wherein each of said components comprises a cross-coupled loop having an unstable state and at least two stable states.
10. A method according to claim 9, wherein each cross coupled loop comprises a pair of latches, each latch having an input terminal and an output terminal, said latches being cross-coupled such that the output of a first latch is applied to the input terminal of a second latch and the output of the second latch is applied to the input terminal of the first latch, the excitation signal being applied to a clear input of one of the latches and a preset input of the other latch.
11. A method according to claim 10, wherein said cross-coupled loop is arranged and configured such that it is in said unstable state when said excitation signal is high and, when said excitation signal goes low, said cross-coupled loop is driven to output one of said at least two stable states.
12. A system including a hardware and/or software arranged and configured to perform the method of claim 1.
13. A method of providing identification data in respect of a device having challengeable memory, comprising the steps of generating a response to a physically unclonable function in respect of said device by means of the method of claim 1, associating a unique verification key with said device and generating helper data that maps the respective response to said physically unclonable function for said device onto said associated verification key.
14. An electronic component comprising an electronic device and means for storing identification data generated by performing the method of claim 13 in respect of said electronic device.
15. An electronic component according to claim 14, wherein said means for storing said identification data comprises non- volatile memory means.
16. A method of manufacturing an electronic component according to claim 14, the method comprising manufacturing an electronic device, generating a respective response to a physically unclonable function in respect of each of said electronic devices by means of the method of claim 1 , providing identification data in respect of said devices by means of the method of claim 13, and storing identification data for said device in association with the device.
17. An electronic storage device on which is stored configuration data for configuring a field programmable electronic component according to claim 14, said configuration data including data representative of said challenge signal used to generate said response to said physically unclonable function according to the method of claim 1.
18. A method of verifying the identity of a device having challengeable memory, the method comprising the steps of generating a response to a physically unclonable function in respect of said device by means of the method of claim 1, retrieving identification data generated according to the method of claim 13, performing a key extraction algorithm using said generated physically unclonable function and the helper data included in said retrieved identification data to extract a key in respect of said electronic device and comparing said extracted key with said verification key associated with said device.
19. A method of generating a plurality of responses to respective physically unclonable functions, each response being uniquely representative of the identity of a respective device of a plurality of such devices of the same design, each device having challengeable memory, the method comprising applying the same one or more challenge signals to the memory of each of said plurality of devices, and reading the resulting response data from the memory of each of said plurality of devices.
20. A method according to claim 19, wherein each memory comprises a plurality of logical locations each having at least two possible logical states or values, the method comprising applying said one or more challenge signals to said plurality of logical locations so as to cause each logical location to occupy one of said at least two states, and reading the resulting response data comprised of the states or values held by said plurality of logical locations as a result of application of said one or more challenge signals thereto.
21. A method of providing identification data in respect of a plurality o f electronic devices of the same design, comprising the steps of generating a respective response to a physically unclonable function in respect of each device by means of the method of claim 20, associating a unique verification key with each said device and generating helper data that maps the respective response to the physically unclonable function for each said device onto said associated verification.
22. A method of manufacturing a group of electronic components according to claim 14, the method comprising manufacturing a plurality of electronic devices, generating a respective response to a physically unclonable function in respect of each of said electronic devices by means of the method of claim 20, providing identification data in respect of each of said devices by means of the method of claim 13, and storing identification data for each of said devices in association with the device.
EP08807343.2A 2007-08-22 2008-08-18 Identification of devices using physically unclonable functions Active EP2191410B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP08807343.2A EP2191410B1 (en) 2007-08-22 2008-08-18 Identification of devices using physically unclonable functions

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP07114732 2007-08-22
PCT/IB2008/053299 WO2009024913A2 (en) 2007-08-22 2008-08-18 Identification of devices using physically unclonable functions
EP08807343.2A EP2191410B1 (en) 2007-08-22 2008-08-18 Identification of devices using physically unclonable functions

Publications (2)

Publication Number Publication Date
EP2191410A2 true EP2191410A2 (en) 2010-06-02
EP2191410B1 EP2191410B1 (en) 2014-10-08

Family

ID=40210762

Family Applications (1)

Application Number Title Priority Date Filing Date
EP08807343.2A Active EP2191410B1 (en) 2007-08-22 2008-08-18 Identification of devices using physically unclonable functions

Country Status (4)

Country Link
US (1) US20110215829A1 (en)
EP (1) EP2191410B1 (en)
TW (1) TW200917085A (en)
WO (1) WO2009024913A2 (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170040294A (en) * 2014-08-29 2017-04-12 내셔날 인스티튜트 오브 어드밴스드 인더스트리얼 사이언스 앤드 테크놀로지 Method for controlling error rate of Device-Specific Information, and Program for Controlling error rate of Device-Specific Information
US11258597B2 (en) 2017-07-10 2022-02-22 Intrinsic Id B.V. Key derivation from PUFs
US11429624B2 (en) 2015-11-20 2022-08-30 Intrinsic Id B.V. Assigning device

Families Citing this family (105)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1842203A4 (en) * 2004-11-12 2011-03-23 Verayo Inc Volatile device keys and applications thereof
EP2269133B1 (en) * 2008-04-17 2016-05-11 Intrinsic ID B.V. Method of reducing the occurrence of burn-in due to negative bias temperature instability
EP2359520B1 (en) * 2008-11-17 2019-08-14 Intrinsic ID B.V. Distributed puf
EP2230794A3 (en) * 2009-03-16 2011-10-05 Technische Universität München Towards Electrical, Integrated Implementations of SIMPL Systems
EP2230793A3 (en) * 2009-03-16 2011-09-07 Technische Universität München On-Chip Electric Waves: An Analog Circuit Approach to Physical Uncloneable Functions: PUF
FR2948793B1 (en) * 2009-07-28 2014-10-31 Thales Sa SECURE METHOD OF RECONSTRUCTING A REFERENCE MEASUREMENT OF CONFIDENTIAL DATA FROM A BRUTE MEASUREMENT OF THIS DATA, IN PARTICULAR FOR THE GENERATION OF CRYPTOGRAPHIC KEYS
US8694856B2 (en) 2009-08-14 2014-04-08 Intrinsic Id B.V. Physically unclonable function with tamper prevention and anti-aging system
US8387071B2 (en) 2009-08-28 2013-02-26 Empire Technology Development, Llc Controlling integrated circuits including remote activation or deactivation
US8819409B2 (en) * 2009-10-21 2014-08-26 Intrinsic Id B.V. Distribution system and method for distributing digital information
KR101727130B1 (en) * 2010-01-20 2017-04-14 인트린직 아이디 비브이 Device and method for obtaining a cryptographic key
US8347092B2 (en) 2010-04-05 2013-01-01 Kelce Wilson Subsystem authenticity and integrity verification (SAIV)
DE102010024622B4 (en) * 2010-06-22 2012-12-13 Infineon Technologies Ag Identification circuit and method for generating an identification bit
US8667265B1 (en) * 2010-07-28 2014-03-04 Sandia Corporation Hardware device binding and mutual authentication
US8848905B1 (en) * 2010-07-28 2014-09-30 Sandia Corporation Deterrence of device counterfeiting, cloning, and subversion by substitution using hardware fingerprinting
FR2964278A1 (en) 2010-08-31 2012-03-02 St Microelectronics Rousset KEY EXTRACTION IN AN INTEGRATED CIRCUIT
GB2484268A (en) 2010-09-16 2012-04-11 Uniloc Usa Inc Psychographic profiling of users of computing devices
US8583710B2 (en) 2010-09-17 2013-11-12 Infineon Technologies Ag Identification circuit and method for generating an identification bit using physical unclonable functions
WO2012045627A1 (en) 2010-10-04 2012-04-12 Intrinsic Id B.V. Physical unclonable function with improved start-up behavior
US8694778B2 (en) * 2010-11-19 2014-04-08 Nxp B.V. Enrollment of physically unclonable functions
EP2643750B1 (en) * 2010-11-24 2015-01-07 Intrinsic ID B.V. Physical unclonable function
KR101118826B1 (en) 2011-02-15 2012-04-20 한양대학교 산학협력단 Encryption apparatus and method for preventing physical attack
US8274306B1 (en) * 2011-03-31 2012-09-25 The United States Of America As Represented By The Secretary Of The Navy Electronic logic circuit with physically unclonable function characteristics
AU2011101296B4 (en) 2011-09-15 2012-06-28 Uniloc Usa, Inc. Hardware identification through cookies
US8590010B2 (en) 2011-11-22 2013-11-19 International Business Machines Corporation Retention based intrinsic fingerprint identification featuring a fuzzy algorithm and a dynamic key
US8700916B2 (en) * 2011-12-02 2014-04-15 Cisco Technology, Inc. Utilizing physically unclonable functions to derive device specific keying material for protection of information
CN104521177B (en) * 2011-12-06 2018-03-06 本质Id有限责任公司 It is used for the soft-decision error correction of the PUF based on memory using single sign
JP5857726B2 (en) * 2011-12-20 2016-02-10 富士通株式会社 Temperature sensor, encryption device, encryption method, and individual information generation device
CN104025500B (en) 2011-12-29 2017-07-25 英特尔公司 Secure key storage using physically unclonable functions
US20130212642A1 (en) * 2012-02-12 2013-08-15 John J. Walsh Resilient Device Authentication System
FR2992452B1 (en) * 2012-06-21 2015-07-03 Thales Sa METHOD FOR TESTING PUFS OPERATION
FR2992451B1 (en) * 2012-06-21 2015-12-25 Thales Sa METHOD FOR TESTING THE FUNCITATION OF PUFS FROM SECURE SKETCH
US9258129B2 (en) 2012-07-18 2016-02-09 Sypris Electronics, Llc Resilient device authentication system
US9996480B2 (en) 2012-07-18 2018-06-12 Analog Devices, Inc. Resilient device authentication system with metadata binding
US9093128B2 (en) 2012-11-05 2015-07-28 Infineon Technologies Ag Electronic device with a plurality of memory cells and with physically unclonable function
US9038133B2 (en) 2012-12-07 2015-05-19 International Business Machines Corporation Self-authenticating of chip based on intrinsic features
US9449153B2 (en) 2012-12-20 2016-09-20 Qualcomm Incorporated Unique and unclonable platform identifiers using data-dependent circuit path responses
US8938792B2 (en) 2012-12-28 2015-01-20 Intel Corporation Device authentication using a physically unclonable functions based key generation system
US9048834B2 (en) 2013-01-16 2015-06-02 Intel Corporation Grouping of physically unclonable functions
US8803328B1 (en) 2013-01-22 2014-08-12 International Business Machines Corporation Random coded integrated circuit structures and methods of making random coded integrated circuit structures
US9197422B2 (en) * 2013-01-24 2015-11-24 Raytheon Company System and method for differential encryption
AU2013100802B4 (en) 2013-04-11 2013-11-14 Uniloc Luxembourg S.A. Device authentication using inter-person message metadata
US8695068B1 (en) 2013-04-25 2014-04-08 Uniloc Luxembourg, S.A. Device authentication using display device irregularity
CA2922701C (en) 2013-08-28 2021-05-04 Stc.Unm Systems and methods for leveraging path delay variations in a circuit and generating error-tolerant bitstrings
US9298946B2 (en) * 2013-09-09 2016-03-29 Qualcomm Incorporated Physically unclonable function based on breakdown voltage of metal-insulator-metal device
US20150071432A1 (en) * 2013-09-09 2015-03-12 Qualcomm Incorporated Physically unclonable function based on resistivity of magnetoresistive random-access memory magnetic tunnel junctions
US9343135B2 (en) * 2013-09-09 2016-05-17 Qualcomm Incorporated Physically unclonable function based on programming voltage of magnetoresistive random-access memory
US9230630B2 (en) * 2013-09-09 2016-01-05 Qualcomm Incorporated Physically unclonable function based on the initial logical state of magnetoresistive random-access memory
JP6224401B2 (en) * 2013-10-04 2017-11-01 ルネサスエレクトロニクス株式会社 Semiconductor memory
US20150134966A1 (en) 2013-11-10 2015-05-14 Sypris Electronics, Llc Authentication System
US9577637B2 (en) * 2014-02-19 2017-02-21 Altera Corporation Stability-enhanced physically unclonable function circuitry
EP2911086A1 (en) * 2014-02-19 2015-08-26 Renesas Electronics Europe GmbH Integrated circuit with parts activated based on intrinsic features
DE102015002367A1 (en) 2014-03-02 2015-09-03 Gabriele Trinkel Secure data transfer and scaling, cloud over-load protection and cloud computing
US9946858B2 (en) 2014-05-05 2018-04-17 Analog Devices, Inc. Authentication system and device including physical unclonable function and threshold cryptography
US9672342B2 (en) 2014-05-05 2017-06-06 Analog Devices, Inc. System and device binding metadata with hardware intrinsic properties
US10432409B2 (en) 2014-05-05 2019-10-01 Analog Devices, Inc. Authentication system and device including physical unclonable function and threshold cryptography
US10382962B2 (en) 2014-05-22 2019-08-13 Analog Devices, Inc. Network authentication system with dynamic key generation
US9483664B2 (en) 2014-09-15 2016-11-01 Arm Limited Address dependent data encryption
EP3202041A1 (en) 2014-10-01 2017-08-09 Universita' Degli Studi di Udine Integrated device for implementing a physical unclonable function and a physical unclonable constant
CN107004380B (en) 2014-10-13 2020-11-13 本质Id有限责任公司 Encryption device comprising a physical unclonable function
US9640228B2 (en) 2014-12-12 2017-05-02 Globalfoundries Inc. CMOS device with reading circuit
US9501664B1 (en) 2014-12-15 2016-11-22 Sandia Corporation Method, apparatus and system to compensate for drift by physically unclonable function circuitry
EP3046096B1 (en) * 2015-01-15 2022-03-30 Siemens Aktiengesellschaft A protection method of writting encrypted data to a memory device and reading decrypted data from the memory device using the power up of a PUF
CN104658601B (en) * 2015-01-22 2017-12-29 北京大学 PUF authentication methods based on the distribution of STT ram memory cells error rate
DE102015103640A1 (en) * 2015-03-12 2016-09-15 Universität Rostock Device comprising logical elements
US10177922B1 (en) * 2015-03-25 2019-01-08 National Technology & Engineering Solutions Of Sandia, Llc Repeatable masking of sensitive data
US9722774B2 (en) 2015-04-29 2017-08-01 Samsung Electronics Co., Ltd. Non-leaky helper data: extracting unique cryptographic key from noisy F-PUF fingerprint
US10135615B2 (en) 2015-05-11 2018-11-20 The Trustees Of Columbia University In The City Of New York Voltage and temperature compensated device for physically unclonable function
FR3038416B1 (en) * 2015-06-30 2017-07-21 Maxim Integrated Products AUTHENTICATION DEVICES AND METHODS BASED ON PHYSICALLY NON-CLONABLE FUNCTIONS
US9971566B2 (en) 2015-08-13 2018-05-15 Arizona Board Of Regents Acting For And On Behalf Of Northern Arizona University Random number generating systems and related methods
US9985791B2 (en) 2015-08-13 2018-05-29 Arizona Board Of Regents Acting For And On Behalf Of Northern Arizona University Physically unclonable function generating systems and related methods
US20170288885A1 (en) * 2016-03-31 2017-10-05 Intel Corporation System, Apparatus And Method For Providing A Physically Unclonable Function (PUF) Based On A Memory Technology
US10235517B2 (en) * 2016-05-13 2019-03-19 Regents Of The University Of Minnesota Robust device authentication
US10146464B2 (en) * 2016-06-30 2018-12-04 Nxp B.V. Method for performing multiple enrollments of a physically uncloneable function
CN106201352B (en) * 2016-07-07 2019-11-29 广东高云半导体科技股份有限公司 The secrecy system and decryption method of non-volatile FPGA on piece data streaming file
CN106297863B (en) * 2016-08-09 2020-07-28 复旦大学 PUF memory capable of double pre-charging and password generation method thereof
US11095461B2 (en) * 2016-11-04 2021-08-17 Stc.Unm System and methods for entropy and statistical quality metrics in physical unclonable function generated bitstrings
US11146410B2 (en) * 2016-12-30 2021-10-12 Robert Bosch Gmbh Pseudo-random generation of matrices for a computational fuzzy extractor and method for authentication
WO2018183572A1 (en) * 2017-03-29 2018-10-04 Board Of Regents, The University Of Texas System Reducing amount of helper data in silicon physical unclonable functions via lossy compression without production-time error characterization
US10579339B2 (en) * 2017-04-05 2020-03-03 Intel Corporation Random number generator that includes physically unclonable circuits
DE102017205818A1 (en) * 2017-04-05 2018-10-11 Robert Bosch Gmbh Adjustable physical unclonable function
US10425235B2 (en) 2017-06-02 2019-09-24 Analog Devices, Inc. Device and system with global tamper resistance
US10958452B2 (en) 2017-06-06 2021-03-23 Analog Devices, Inc. System and device including reconfigurable physical unclonable functions and threshold cryptography
US10643006B2 (en) 2017-06-14 2020-05-05 International Business Machines Corporation Semiconductor chip including integrated security circuit
US10056905B1 (en) * 2017-07-28 2018-08-21 Bae Systems Information And Electronic Systems Integration Inc. Nanomaterial-based physically unclonable function device
US10521616B2 (en) 2017-11-08 2019-12-31 Analog Devices, Inc. Remote re-enrollment of physical unclonable functions
US10812277B2 (en) * 2017-11-28 2020-10-20 Taiwan Semiconductor Manufacturing Company Ltd. Method and system for secure key exchange using physically unclonable function (PUF)-based keys
WO2019212849A1 (en) * 2018-05-01 2019-11-07 Analog Devices, Inc. Device authentication based on analog characteristics without error correction
US10749694B2 (en) 2018-05-01 2020-08-18 Analog Devices, Inc. Device authentication based on analog characteristics without error correction
US11044107B2 (en) 2018-05-01 2021-06-22 Analog Devices, Inc. Device authentication based on analog characteristics without error correction
EP3594926B1 (en) * 2018-07-11 2022-06-22 Secure-IC SAS Connected synthetic physically unclonable function
US11152313B1 (en) 2018-07-31 2021-10-19 Synopsys, Inc. Using threading dislocations in GaN/Si systems to generate physically unclonable functions
US11151290B2 (en) 2018-09-17 2021-10-19 Analog Devices, Inc. Tamper-resistant component networks
US11205015B2 (en) 2019-02-28 2021-12-21 International Business Machines Corporation Magnetic tunnel junction (MTJ) for multi-key encryption
US11245680B2 (en) 2019-03-01 2022-02-08 Analog Devices, Inc. Garbled circuit for device authentication
EP3771140B1 (en) * 2019-07-23 2021-08-25 Nokia Technologies Oy Securing a provable resource possession
US11271732B2 (en) * 2019-11-12 2022-03-08 Nxp B.V. Robust repeatable entropy extraction from noisy source
US11468220B2 (en) * 2020-07-24 2022-10-11 Gowin Semiconductor Corporation Method and system for enhancing programmability of a field-programmable gate array via a dual-mode port
US11662923B2 (en) 2020-07-24 2023-05-30 Gowin Semiconductor Corporation Method and system for enhancing programmability of a field-programmable gate array
CN112152816B (en) * 2020-09-24 2022-07-26 南京航灵信息科技有限公司 Credible mechanism of Internet of things security chip
CN112905506B (en) * 2021-03-17 2024-06-28 清华大学无锡应用技术研究院 Reconfigurable system based on multivalue APUF
US11985259B2 (en) 2021-06-24 2024-05-14 Raytheon Company Unified multi-die physical unclonable function
US12095933B2 (en) * 2021-08-02 2024-09-17 Arizona Board Of Regents On Behalf Of Northern Arizona University PUF-protected pseudo-homomorphic methods to generate session keys
WO2023046476A1 (en) 2021-09-23 2023-03-30 Intrinsic Id B.V. Random number generation using sparse noise source
US11889002B2 (en) 2021-09-23 2024-01-30 Rockwell Automation Technologies, Inc. Use of physical unclonable functions to prevent counterfeiting of industrial control products
WO2023186414A1 (en) 2022-03-28 2023-10-05 Intrinsic Id B.V. Hamming distance based matching for puf strings

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4813015A (en) 1986-03-12 1989-03-14 Advanced Micro Devices, Inc. Fracturable x-y storage array using a ram cell with bidirectional shift
US6738294B2 (en) * 2002-09-30 2004-05-18 Agere Systems Inc. Electronic fingerprinting of semiconductor integrated circuits
ATE426968T1 (en) * 2005-11-29 2009-04-15 Koninkl Philips Electronics Nv PHYSICALLY DISTRIBUTING SECRETS AND CLOSE PROOF USING PUFS

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO2009024913A2 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20170040294A (en) * 2014-08-29 2017-04-12 내셔날 인스티튜트 오브 어드밴스드 인더스트리얼 사이언스 앤드 테크놀로지 Method for controlling error rate of Device-Specific Information, and Program for Controlling error rate of Device-Specific Information
US10402248B2 (en) 2014-08-29 2019-09-03 National Institute Of Advanced Industrial Science And Technology Method for controlling error rate of device-specific information and program for controlling error rate of device-specific information
US11429624B2 (en) 2015-11-20 2022-08-30 Intrinsic Id B.V. Assigning device
US11258597B2 (en) 2017-07-10 2022-02-22 Intrinsic Id B.V. Key derivation from PUFs

Also Published As

Publication number Publication date
EP2191410B1 (en) 2014-10-08
WO2009024913A9 (en) 2010-06-03
WO2009024913A3 (en) 2009-11-19
WO2009024913A2 (en) 2009-02-26
US20110215829A1 (en) 2011-09-08
TW200917085A (en) 2009-04-16
WO2009024913A4 (en) 2010-03-18

Similar Documents

Publication Publication Date Title
EP2191410B1 (en) Identification of devices using physically unclonable functions
Chang et al. A retrospective and a look forward: Fifteen years of physical unclonable function advancement
JP5586628B2 (en) Distributed PUF
Joshi et al. Everything you wanted to know about PUFs
KR101852115B1 (en) Physical unclonable function with improved start―up behavior
KR102709350B1 (en) Reliability enhancement methods for physically unclonable function bitstring generation
Bhargava et al. An efficient reliable PUF-based cryptographic key generator in 65nm CMOS
Merli et al. Improving the quality of ring oscillator PUFs on FPGAs
Eichhorn et al. Logically reconfigurable PUFs: Memory-based secure key storage
Rosenblatt et al. A self-authenticating chip architecture using an intrinsic fingerprint of embedded DRAM
Yamamoto et al. Variety enhancement of PUF responses using the locations of random outputting RS latches
Jia et al. Extracting robust keys from NAND flash physical unclonable functions
US11528135B2 (en) Integrated circuit (IC) signatures with random number generator and one-time programmable device
US11962693B2 (en) Integrated circuit (IC) signatures with random number generator and one-time programmable device
JP2010266417A (en) Semiconductor integrated circuit, information processing apparatus and method, and program
TWI781544B (en) Integrated circuit device and method and system of generating a security key for an integrated circuit device
US20240056316A1 (en) Encrypted physically unclonable function circuit helper data
Usmani Applications Of Physical Unclonable Functions on ASICS and FPGAs
Karri et al. Physical unclonable functions and intellectual property protection techniques
US20240348435A1 (en) Integrated circuit (ic) signatures with random number generator and one-time programmable device
Li et al. Enhancing tpm security by integrating sram pufs technology
Mandadi Remote Integrity Checking using Multiple PUF based Component Identifiers
Srivathsa Secure and energy efficient physical unclonable functions
Stochino Design and Development of a Strong Physical Unclonable Function for FPGA devices
Maes et al. Process variations for security: Pufs

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20100222

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MT NL NO PL PT RO SE SI SK TR

AX Request for extension of the european patent

Extension state: AL BA MK RS

17Q First examination report despatched

Effective date: 20101025

DAX Request for extension of the european patent (deleted)
RIN1 Information on inventor provided before grant (corrected)

Inventor name: SCHRIJEN, GEERT, JAN

Inventor name: TUYLS, PIM, THEO

Inventor name: KUMAR, SHANKARAN, S.

Inventor name: GUAJARDO MERCHAN, JORGE

REG Reference to a national code

Ref country code: DE

Ref legal event code: R079

Ref document number: 602008034812

Country of ref document: DE

Free format text: PREVIOUS MAIN CLASS: G06F0021020000

Ipc: G06F0021730000

GRAJ Information related to disapproval of communication of intention to grant by the applicant or resumption of examination proceedings by the epo deleted

Free format text: ORIGINAL CODE: EPIDOSDIGR1

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

RIC1 Information provided on ipc code assigned before grant

Ipc: H04L 9/32 20060101ALI20131202BHEP

Ipc: G06F 21/76 20130101ALI20131202BHEP

Ipc: G06F 21/73 20130101AFI20131202BHEP

Ipc: G06F 7/58 20060101ALI20131202BHEP

INTG Intention to grant announced

Effective date: 20131219

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAJ Information related to disapproval of communication of intention to grant by the applicant or resumption of examination proceedings by the epo deleted

Free format text: ORIGINAL CODE: EPIDOSDIGR1

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

INTG Intention to grant announced

Effective date: 20140522

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MT NL NO PL PT RO SE SI SK TR

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

REG Reference to a national code

Ref country code: AT

Ref legal event code: REF

Ref document number: 690975

Country of ref document: AT

Kind code of ref document: T

Effective date: 20141015

Ref country code: CH

Ref legal event code: EP

REG Reference to a national code

Ref country code: IE

Ref legal event code: FG4D

REG Reference to a national code

Ref country code: DE

Ref legal event code: R096

Ref document number: 602008034812

Country of ref document: DE

Effective date: 20141120

REG Reference to a national code

Ref country code: NL

Ref legal event code: T3

REG Reference to a national code

Ref country code: AT

Ref legal event code: MK05

Ref document number: 690975

Country of ref document: AT

Kind code of ref document: T

Effective date: 20141008

REG Reference to a national code

Ref country code: LT

Ref legal event code: MG4D

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: ES

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20141008

Ref country code: NO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150108

Ref country code: FI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20141008

Ref country code: LT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20141008

Ref country code: IS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150208

Ref country code: PT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150209

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: PL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20141008

Ref country code: AT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20141008

Ref country code: GR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150109

Ref country code: LV

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20141008

Ref country code: HR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20141008

Ref country code: SE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20141008

Ref country code: CY

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20141008

REG Reference to a national code

Ref country code: DE

Ref legal event code: R097

Ref document number: 602008034812

Country of ref document: DE

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: EE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20141008

Ref country code: CZ

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20141008

Ref country code: SK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20141008

Ref country code: DK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20141008

Ref country code: RO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20141008

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 8

26N No opposition filed

Effective date: 20150709

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20141008

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MC

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20141008

Ref country code: LU

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20150818

REG Reference to a national code

Ref country code: CH

Ref legal event code: PL

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LI

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20150831

Ref country code: CH

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20150831

REG Reference to a national code

Ref country code: IE

Ref legal event code: MM4A

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20150818

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 9

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20141008

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: BG

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20141008

Ref country code: HU

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT; INVALID AB INITIO

Effective date: 20080818

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 10

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: TR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20141008

PLAA Information modified related to event that no opposition was filed

Free format text: ORIGINAL CODE: 0009299DELT

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

REG Reference to a national code

Ref country code: FR

Ref legal event code: PLFP

Year of fee payment: 11

R26N No opposition filed (corrected)

Effective date: 20150709

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: IT

Payment date: 20230822

Year of fee payment: 16

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: NL

Payment date: 20240723

Year of fee payment: 17

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20240723

Year of fee payment: 17

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20240723

Year of fee payment: 17

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: BE

Payment date: 20240723

Year of fee payment: 17

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20240723

Year of fee payment: 17