EP2160670A1 - Processeur et procédé de commande de celui-ci - Google Patents

Processeur et procédé de commande de celui-ci

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Publication number
EP2160670A1
EP2160670A1 EP08760556A EP08760556A EP2160670A1 EP 2160670 A1 EP2160670 A1 EP 2160670A1 EP 08760556 A EP08760556 A EP 08760556A EP 08760556 A EP08760556 A EP 08760556A EP 2160670 A1 EP2160670 A1 EP 2160670A1
Authority
EP
European Patent Office
Prior art keywords
time
arithmetic
processing
processor
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP08760556A
Other languages
German (de)
English (en)
Inventor
Christian Siemers
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fachhochschule Nordhausen
Original Assignee
Fachhochschule Nordhausen
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fachhochschule Nordhausen filed Critical Fachhochschule Nordhausen
Publication of EP2160670A1 publication Critical patent/EP2160670A1/fr
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/14—Time supervision arrangements, e.g. real time clock
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3409—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment
    • G06F11/3419—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment for performance assessment by assessing time
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3466—Performance evaluation by tracing or monitoring
    • G06F11/348—Circuit details, i.e. tracer hardware
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/86—Event-based monitoring
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/865—Monitoring of software

Definitions

  • the invention relates to a processor for a computing machine, the power stroke is regulated, and a method for controlling a processor clock and a data processing program for processing on a processor. Furthermore, the invention relates to a processor and a method by which a monitoring of times for the execution of arithmetic instructions is made possible. Finally, the invention relates to a multiprocessor system and a method for distributing computational instructions to processors of the multiprocessor system.
  • DE 100 34 459 A1 describes a method and a device for measuring the running time of a task (task to be performed) in a real-time system.
  • a timer is started at the beginning of the task whose runtime is to be determined.
  • the timer is stopped in the event of an interruption and the state of the timer is stored. After completion of the interruption, the timer is restarted.
  • the timer is started at the beginning of each task and its status is stored every time the priority level is changed.
  • time management unit for Real-time Processors
  • the time management unit is part of the computer architecture and implemented in hardware absolute time and an event time compared to each other, whereby the result of the comparison, an interrupt to the processor can be triggered.A further description of the effects on the processor is not given in this document.
  • US 2006/0288194 A1 discloses a real-time processor with a clock counter, a command analyzer and a time comparator, by which the command execution can be controlled.
  • this control allows a blockade of the command to be processed, so that the next command can be executed. This simple tax However, this mechanism can only be used for selected real-time applications.
  • UML 2.0 Infrastructure Specification PTC / 03-09-15 Unified Modeling Language is a software modeling language that uses sequential diagrams or activity diagrams to correlate individual routines with one another. However, estimates must be used for this, so that statements about the functionality of the system are only possible if the estimates are correct. Basically, it is only partially possible to check the temporal function of an entire computing system in all variations in order to be able to estimate the time sequences. For this purpose, strongly limiting boundary conditions must be defined. For example, the calculation of the maximum runtime of a program part, i. H. the execution time, which must not be exceeded, in the case that a microprocessor with cache is used, very high estimates. The reason for this is the inability to predict the behavior of the cache for all source conditions, so it must be assumed that a value is never in the cache. Therefore, software-based concepts such as UML, which take into account the temporal processes, quickly reach their limits.
  • the object of the invention starting from software-based concepts such as UML, is to bring the processing of computational instructions by a processor into better agreement with the actual time sequences.
  • a subtask is also to improve this timing even within a programmable unit or within a multiprocessor system.
  • the processor according to the invention initially has a control unit for providing a sequence of arithmetic instructions.
  • a control unit is also referred to as a tail unit or control unit (CU) and is often the core of a microprocessor.
  • the processor according to the invention has an arithmetic unit for processing the arithmetic instructions.
  • Such an arithmetic unit is also referred to as a central processing unit, as a data processor or as an arithmetic logic unit (ALU).
  • the processor according to the invention has a controllable processor clock for providing a processor clock.
  • This processor clock may include an internal oscillator, such as a quartz oscillator, or may be powered by an external clock.
  • the controllable processor clock has to offer the possibility of controllably providing the processor clock, ie the clock with which the arithmetic unit is operating.
  • the processor according to the invention further comprises a time management unit, which is also referred to as Time Management Unit (TMU).
  • TMU Time Management Unit
  • the time management unit includes a clock for providing a clock.
  • the time management unit furthermore comprises a comparator for comparing a previously defined value for a permissible time duration for executing a computation instruction to be processed in the arithmetic unit with a value for an elapsed time defined by the clock since the execution of the arithmetic unit instruction to be processed Period of time.
  • the processor comprises a coupling of the time management unit with the controllable processor clock generator. By means of this coupling, it is possible to adapt the processor clock to the time actually required by the arithmetic unit for processing the arithmetic instructions located there. Thus, a control loop can be formed in which the processor clock represents the controlled variable. If the comparison of the time values reveals that the permissible time duration has been exceeded for executing a calculation instruction to be processed in the arithmetic unit, the processor clock cycle must be increased. Otherwise, the processor clock can remain constant or reduced.
  • the processor according to the invention has the advantage that the time sequences during the processing of the arithmetic instructions are no longer bound to limited exact estimates. Another advantage is that during those times in which no or only a few computational instructions are processed, the processor clock is significantly reduced, whereby a significant energy savings is possible. This also has a detrimental effect on the effective heat loss performance, whereby cooling systems can possibly be dimensioned smaller.
  • Another processor initially also has a control unit for providing a sequence of arithmetic instructions and an arithmetic unit for processing the arithmetic instructions.
  • the processor further comprises a time management unit with a clock for providing a Time clock.
  • the time management unit further comprises a comparator for comparing a predetermined value for a permissible time duration for processing a computation instruction to be processed in the arithmetic unit with a value for a time period defined by the time clock since the processing of the arithmetic unit to be processed arithmetic operation elapsed time duration.
  • the time management unit has an event control memory for storing values for the time required to execute a calculation instruction in the arithmetic unit.
  • the values stored in the event control memory can be understood as a memory list (Event Memory List).
  • Event Memory List allows monitoring of the time required for processing the arithmetic commands in the arithmetic unit. This is particularly advantageous for the developer of software, since he can determine the time actually required for processing the individual arithmetic instructions.
  • the clock generator is formed by the detection of an external system clock.
  • the clock is implemented as a real time clock.
  • the real-time clock outputs a time, for example in the format hh: mm: ss: ms: ⁇ s or also with date.
  • the time clock in the form of a simple system clock or a real time is absolute, d. H. regardless of the processor clock.
  • the time management unit preferably has an event memory for storing the previously defined values for the respective permissible time duration of the arithmetic unit instructions to be processed.
  • the contents of this event memory can be construed as an event list containing relative times.
  • the event memory allows To provide the comparator with the specified values for the respectively permissible time duration of the arithmetic instructions to be processed in the arithmetic unit.
  • the time management unit of a processor according to the invention with a controllable processor clock generator preferably also has an event control memory for storing values for the time duration required for processing a calculation instruction in the arithmetic unit.
  • the time management unit of the processors according to the invention preferably also has an interface for outputting hardware signals to the control unit. This makes it possible to use the exceeding of definable time values for generating a hardware signal. These hardware signals generate, for example, an interrupt request (IRQ) at the processor, which is treated as an exception. This exception signals to the processor that the program's timing has been violated, for which the system designer can provide appropriate response capabilities.
  • IRQ interrupt request
  • the controllable processor clock preferably comprises a voltage controlled oscillator.
  • the processor cycle can be controlled with little effort depending on the applied operating voltage.
  • the coupling of the time management unit with the controllable processor clock can, for example, via a control unit in which the control algorithm is implemented, and via an analog output of the control unit, which controls the voltage controlled oscillator occur.
  • the method according to the invention for controlling a cycle of a processor initially comprises a provisioning step a sequence of computational instructions that are executed in the processor. Furthermore, a time clock is to be provided.
  • the method according to the invention provides for a repeated comparison, in which a previously defined value for a permissible time duration for executing a calculation instruction to be processed is compared with a value for a time period defined by the time interval since the processing of the arithmetic instruction to be processed has elapsed.
  • a result of the comparison is to be provided accordingly and serves to control the clock of the processor, which is done in response to this result.
  • an adaptation of the processor clock to the time required by the arithmetic unit for processing the respective arithmetic command can take place.
  • the inventive method is largely independent of the computer architecture to be used and may be partially or completely implemented in the processor.
  • the inventive method allows the formation of a control loop in which the clock of the processor represents the controlled variable.
  • the method according to the invention for monitoring times for the execution of arithmetic instructions in a processor initially comprises a step for providing a sequence of arithmetic instructions which are executed in the processor. Furthermore, a time clock is to be provided. Finally, a time period defined by the time clock is stored in total for the processing of the arithmetic command to be processed. This happens when a called program command requests this, which corresponds to a manual monitoring, or if the total time required for the processing of the arithmetic command to be processed by the time clock is greater than a permissible time for processing this arithmetic command, which corresponds to an automatic monitoring.
  • the stored value can be wise be read by the developer of a software to draw conclusions about the timing of the execution of the program. However, the stored value can also be read out by a program command in order to influence the further execution of the program as a function of this value.
  • the inventive method is largely independent of the computer architecture to be used and may be partially or completely implemented in the processor.
  • the time clock is provided as real time, whereby extended comparison possibilities are given.
  • a variable before processing a calculation instruction, a variable assumes the value for the permissible time duration for processing the calculation instruction.
  • the variable is decremented during execution of the arithmetic command with the timing.
  • the repeated comparison is that the variable is repeatedly compared to zero.
  • a time duration defined by the clock cycle is generally stored in total for the processing of the arithmetic command to be processed. This happens when a called program command requests this, which corresponds to a manual monitoring, or if the total time defined by the clock cycle is required for processing the computational command to be processed. Taken time period is greater than the permissible time for processing this arithmetic command, which corresponds to an automatic monitoring.
  • a hardware-based interrupt signal is triggered when the value for the time period defined by the time clock previously required for processing the arithmetic command exceeds a predetermined value. This makes it easier for a software developer to provide appropriate program instructions in case of such exceeding of the specified period of time. It can be used several interrupt signals that can be masked accordingly.
  • a variable for counting the timing is defined by a program instruction.
  • a command "settim Rx" may be set that sets the variable for counting the clock by the contents of the register Rx. If the clock is represented by a real time, the contents of the register Rx must be in real-time format.
  • the value of the variable for counting the time clock is stored in a specified memory area when a program command invoked requests it.
  • a command "gettim Rx" can be defined, with which the value of the variable for counting the time clock is copied into the register Rx or the following registers. If the time clock is represented by a real time, the value in the corresponding format becomes copied the register.
  • the previously defined values for the respective permissible time duration for processing the arithmetic commands to be processed are preferably stored in a defined memory area. These values can be understood as an event list.
  • the size of a variable is preferably defined by a maximum number of values for the respective permissible time duration for processing the arithmetical commands to be processed, which can be stored in the memory area specified for this purpose, when a program command invoked requests this.
  • This maximum number is understandable as the number of possible entries in the event list. For example, an instruction "ldnelm Rx" can be defined, which copies the variable with the value of this number into the register Rx.
  • a mode value is used.
  • the mode value is stored in the designated memory area at each of the set values for the respective allowable period of time for processing the arithmetic instructions to be processed.
  • the respective permissible time duration and the mode value provided for each arithmetic command are stored.
  • the mode value defines at which signal from a group of predetermined signals the determination of the time duration defined by the time clock to process the arithmetic command begins. Thus, for example, it can be determined by which interrupt request an activation can take place.
  • a variable is defined by the mode value when a called program command prompts.
  • the mode value is defined by the value of a variable when prompted by another invoked program command.
  • a command "stemc Rx, Ry, Rz" are defined by which a configuration is stored in the element of the event list [Rx], the configuration value in Ry and the mode value in Rz.
  • the mode value for example, the following equivalents can be defined: If bit 7 is 1, a one shot mode is set, whereas a continuous mode with auto reload is set if bit 7 is 0. If bit 6 is equal to 1, the activation takes place via an active interrupt request, whereas an immediate activation takes place when bit 6 is equal to 0. Bits 5 to 0 correspond to the number of the interrupt request if bit 6 is equal to 1.
  • “Stemc #tim, #value, #mode” is prompted to store a configuration in the tim element of the event list, the configuration value in value, and the mode value in mode. for example due to the high number of bits to be coded in the constants.
  • a control mode value is used.
  • One control mode value is stored for each of the specified values for the respective permissible time duration for processing the arithmetic commands to be processed.
  • a mode value is defined as to whether the total time required for processing the arithmetic command to be processed is stored, and whether a hardware-based interrupt signal is triggered when the permissible time for processing the arithmetic command to be processed has been exceeded.
  • the control mode value allows the type of response to be set when the time allowed for a calculation command is exceeded.
  • a variable is defined by the control mode value when prompted by a called program command.
  • the control mode value is defined by the value of a variable when prompted by another invoked program command.
  • a program command "strcm Rx, Ry" may be defined by which the control mode value [Ry] is configured for the element [Rx]
  • the control mode value may have the following correspondence: If bit 1 is equal to 1, the total is to be processed Arithmetic instructions store the required amount of time in the event storage list whereas no storage occurs when bit 1 equals 0.
  • a program command "strcm Rx, #react_mode" can be defined by which the control mode value react_mode is configured for the element [Rx].
  • ldmv, ldnmv, and monit commands can be defined to manage the event store list, and the ldmv Rx program command loads the number of events stored in the event store list.
  • This list can be constructed as a first-in-first-out memory in ring buffer form. But other forms of organization are conceivable.
  • the command “ldnmv Rx" causes the next event to be loaded into register Rx, which could, for example, be the oldest stored event that has not yet been read, decrementing the number of available entries by 1.
  • the command "monit causes the current value of the clock to be written to the event log. This allows you to place marks in this list.
  • the program-controlled unit has at least several arithmetic units for processing arithmetic instructions and a control unit for providing a sequence of arithmetic instructions.
  • the control unit also serves to distribute the computation commands to the arithmetic units.
  • the program-controlled unit furthermore has a time clock for providing a time clock.
  • Each arithmetic unit of the program-controlled unit is a comparator for comparing a predetermined value for a permissible period of time for processing a to be processed Arithmetic commands associated with a value for a defined by the time clock since the beginning of the processing of the processing arithmetic command elapsed time allocated.
  • the comparators are linked to the control unit.
  • the program-controlled unit according to the invention permits the formation of a control loop in which the distribution of the arithmetic commands to the arithmetic units is regulated.
  • the arithmetic units are designed as complete processors. It is a stand-alone processor system, so the programmable unit is a multiprocessor system.
  • the time management units associated with the processors are integrated into the processors.
  • This multiprocessor system allows the formation of a control loop in which the distribution of the arithmetic commands to the processors is controlled.
  • the principle of such a distribution can be given by a space-time mapping method in which the execution dimension Time (time sequence) can be switched to Space (configuration of computing elements for maximum parallelism).
  • the execution in the room binds much more resources and is thus largely avoided. But it has a much higher acceleration potential.
  • the control unit may be partially or completely formed by the processors themselves.
  • the latter furthermore has a controllable processor clock generator for providing a processor clock, wherein this processor clock generator is coupled to at least one of the comparators.
  • a regulation Both the distribution of the arithmetic instructions to the processors and a control of the processor clock of one or more processors possible. This allows the multiprocessor system to be adapted to the amount of computation instructions to be processed in a very wide dynamic range.
  • a method for distributing arithmetic instructions to arithmetic units of a program-controlled unit which first provides for a provision of a sequence of arithmetic instructions which are executed in the arithmetic units. Furthermore, a time clock is provided. There is a repeated comparison of a predetermined value for a permissible period of time for processing a computational command to be processed with a value for a defined by the time clock since the start of processing of this arithmetic command elapsed time duration. The results of the comparisons are provided and serve to determine the division of the arithmetic commands to be processed into the arithmetic units, which subsequently takes place as a function of these results. Thus, the distribution of the arithmetic commands can be adapted to the arithmetic units to the time required by the arithmetic units for processing the respective arithmetic command.
  • the inventive method can also be used for the distribution of arithmetic instructions on processors of a multiprocessor system.
  • the inventive method is applicable regardless of the architecture of the multiprocessor system. Likewise, it is largely independent of the architecture of the individual processors of the multiprocessor system. These may be formed for example by microprocessors.
  • the steps of the method of controlling a clock of a processor may be combined with steps of the method of distributing the arithmetic instructions within a multiprocessor system, whereby a multiprocessor system can be adapted in a large variability to the amount and type of arithmetic instructions to be processed.
  • program instructions mentioned above are preferably to be encoded in an assembly language. This allows them to be translated directly into machine language, allowing low-level and efficient programming.
  • program instructions which in particular control the behavior of the time management unit, can be defined.
  • a further aspect of the invention can be seen in a program which is coded in a high-level language, for example in an imperative language such as C, and after its translation (compilation) is provided for execution on a processor according to the invention.
  • the program has at least one program command encoded in the high-level language in which various machine commands for managing the time management unit are combined.
  • the program commands can be included in the source text as "essential comments" or in the form of conditional compilation.This does not cause any compatibility problems at the source code level.
  • the conditional compilation can be done in C as follows:
  • a basic function can be:
  • the return value of this function is the number of the item in the event list.
  • This basic function starts a permanent process of time monitoring at this point.
  • the return value of this function is the number of the element in the event list.
  • a basic function can be:
  • a basic function can be: void switch_off_timer (elemNumber)
  • the basic functions can be implemented as function calls or as macros.
  • high-level language element is:
  • definable which refers to a loop at the level of which it is defined. This element can be called as follows:
  • element_number start_continuous_timemonitoring (confValue, timeValue); ⁇ Condition>; ⁇ update>, reset_timer (element_number))
  • Another exemplary high level language element is:
  • Fig. 1 is a block diagram of a preferred embodiment of the processor according to the invention.
  • FIG. 2 is a block diagram of a time management unit shown in FIG.
  • Fig. 1 shows a block diagram of a preferred embodiment of the processor according to the invention, including its periphery.
  • the block diagram reflects the architecture of an extended Von Neumann model.
  • the architecture first shows the components of a Von Neumann model.
  • This includes a main processor Ol, which is also referred to as a central processing unit (CPU), and a control unit 02, which is also referred to as a control unit (CU), and an arithmetic unit 03, which is also called the Arithmetical Logical Unit (ALU).
  • the Von Neumann model includes a storage device 04, which is also referred to as memory (MEM), and an input / output device 06, which is also referred to as input / output (I / O).
  • the inventive extension of the von Neumann model consists in that the main processor 01 further comprises a time management unit 08, which is also referred to as a Time Management Unit (TMU).
  • TMU Time Management Unit
  • the time management unit 08 has the task of continuously time, d. H. in the context of a counter, to measure and to secure by program certain or configured time values in a specially designed memory within the time management unit 08.
  • the time management unit 08 is assigned the task of triggering events in the main processor 01 when configured time values are exceeded.
  • FIG. 2 shows a block diagram of the time management unit 08 shown in FIG. 1.
  • the time administration unit 08 initially comprises a central state machine 09, which is also referred to as a central state machine (CSM).
  • a central time unit 11 is coupled.
  • the central time unit 11 permanently outputs the result of the time measurement to the central state machine 09.
  • the central time unit 11 comprises a real-time clock, it transfers its result in the format of a time to the central state machine 09.
  • the time management unit 08 further includes an event memory 12 for storing previously defined values for the respective permissible time duration of a computing instruction to be processed in the arithmetic unit 03.
  • the event memory 12 contains an event list.
  • the event list contains relative times which, if the element of the event list is active, are decremented. When the value reaches zero, an action is triggered.
  • the time management unit 08 further comprises an event control memory 13 for storing values for the time required to execute a calculation instruction in the arithmetic unit 08.
  • the event control memory 13 contains a memory list (Event Memory List), which can be used for manual or automatic monitoring of the time values. During manual monitoring, the storage of the current time value of the central time unit 11 in the event control memory 13 is initiated by a program command. The automatic monitoring can be set up such that an entry into the memory list of the event control memory 13 takes place whenever a set time value is exceeded. This entry contains the respectively valid absolute time of the central time unit 11.
  • the memory list of the event control memory 13 can be read out by the central state machine 09.
  • the time management unit 08 further comprises an interface 14 to the control unit 02.
  • This interface 14 may also be referred to as Interface to CU (I / CU).
  • hardware signals for signaling events can be transmitted to the control unit 02. For example, exceeding this results in configured time values in the event list for generating a hardware signal, if so configured.
  • These hardware signals generate an interrupt request to the main processor Ol, which is called an exception because it is not a wanted interruption or an external signal.
  • This exception signals to the processor that the program's timing has been violated and allows the system designer to respond.
  • the resetting of time values, for example in the event list, to avoid the triggering of an exception can be done by the main processor O1 during a program.
  • the functionality of the time management unit 08 corresponds approximately to the behavior of a watchdog circuit, which triggers a general reset on a timeout.
  • the time management unit 08 monitors the time structure very finely and the handling of the exceptions can also contain very balanced reactions and is the responsibility of the software development.
  • the control of the time management unit 08 is also carried out by the control unit 02, for which the control unit 02 must support new program commands.
  • These program instructions are used, for example, to read in and read out the event memory 12 and the event control memory 13.
  • the program instructions required for controlling the time management unit 08 have little or no relation to the arithmetic unit 03, so that the arithmetic unit 03 compared to a conventional arithmetic unit according to the Von Neumann model does not need to be extended.
  • the integration of the new program instructions can be done, for example, by using a corresponding execution time in the program. This is possible if there is still space in the coding format, so not all variants for coding a command have been exhausted are.
  • the advantage of such integration is universal applicability.
  • the integration of the further program instructions can also be done by being integrated into other commands. This is possible if the commands used so far also have room for additional information, ie unused bits in the code.
  • Such an integration of the new program instructions has the advantage that no additional runtime is required.
  • the central state machine 09 is a finite state machine.
  • the central state machine 09 is not executed as a simple finite state machine, but in a cooperative manner.
  • One possibility of implementation is a small microprocessor with a processing width of, for example, 8 bits, which makes the inputs from the controller 02 and the comparisons between the time values output by the central time unit 11 and the values in the event list 12 and initiates corresponding actions.
  • the use of a microprocessor for implementing the time management unit 08 has the advantage that the time management unit 08 is very flexible, since it is itself programmable.
  • the time management unit 08 is to be implemented in existing hardware, for example as an integral part of a microprocessor.
  • the architecture of the extended von Neumann model of the invention may serve as a basis for implementing an adaptive system.
  • response times for interrupt requests can be monitored.
  • Such a reaction time ie the difference between the occurrence of an interrupt request and the final reaction, can occur at Real time systems are a significant size, the exceeding of a given limit is not allowed.
  • the measurement of such a reaction time shows in each case the real-time capability of the system.
  • cycle times in systems with a cyclic design can also be determined. In timed systems, cycle times are often the size that determines the real-time capability of the system.
  • single run times can also be determined in systems in a non-cyclic design, which can be used to evaluate real-time capability.
  • time measurements referred to have only a very small possible influence on the actual calculation in the time management unit 08.
  • the processor-based time management unit 08 can also be in the microsecond range and below be used. This feature allows the use of the main processor 01 according to the invention, for example in the field of embedded systems, where very short reaction times are required.

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Abstract

L'invention concerne un processeur (01) destiné à un calculateur dont la cadence de travail peut être régulée. Ledit processeur (01) comporte une unité de commande (02), une unité de calcul (03) pour traiter les instructions de calcul, et une horloge de processeur commandable pour fournir une cadence de processeur. Le processeur (01) comporte par ailleurs une unité de gestion de temps (08) présentant une horloge (11) pour fournir une impulsion d'horloge. L'unité de gestion de temps (08) comporte par ailleurs un comparateur pour comparer une valeur définie au préalable d'un intervalle admissible destiné au traitement d'une instruction de calcul à traiter dans l'unité de calcul (03), à une valeur d'un intervalle défini par l'impulsion d'horloge, écoulé depuis le début du traitement de l'instruction de calcul à traiter dans l'unité de calcul (03). Le processeur (01) comporte par ailleurs un couplage de l'unité de gestion de temps (08) avec l'horloge de processeur commandable. Le couplage permet de former une boucle de régulation dans laquelle la cadence de processeur représente la grandeur régulée. L'invention concerne également un procédé de régulation d'une cadence de processeur et un programme de traitement dans le processeur, ainsi qu'un système multiprocesseurs et un procédé de répartition d'instructions de commande sur des processeurs du système multiprocesseurs.
EP08760556A 2007-06-07 2008-06-05 Processeur et procédé de commande de celui-ci Withdrawn EP2160670A1 (fr)

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EP3537293A1 (fr) 2018-03-09 2019-09-11 Till I.D. GmbH Microprocesseur à déterminisme temporel et microcontrôleur s

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JP2520544B2 (ja) * 1991-09-26 1996-07-31 インターナショナル・ビジネス・マシーンズ・コーポレイション タスクのオ―バ―ラン状態を監視する方法及びタスク実行サイクルのオ―バ―ランを検出する装置
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DE102007026982A1 (de) 2008-12-11
WO2008148838A1 (fr) 2008-12-11

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