EP2140735B1 - Circuit configuration for starting and operating at least one discharge lamp - Google Patents

Abstract

A circuit arrangement for starting and operating at least one discharge lamp is provided.

Description

Technical area

The present invention relates to a circuit arrangement for igniting and operating at least one discharge lamp having a first and a second input terminal for connecting a supply voltage, an inverter comprising at least a first and a second main transistor in a half-bridge arrangement, which is coupled in series between the first and the second input terminal a first and a second output terminal for connecting the at least one discharge lamp, at least one lamp inductor coupled in series with the first output terminal, at least one output capacitor coupled in parallel with the first and second output terminals, a transformer having a primary winding and a first one and a second secondary winding, wherein a series circuit comprising the primary winding and the at least one lamp inductor is coupled between the half-bridge center and a reference potential; and a first control circuit for driving the first main transistor and a second control circuit for driving the second main transistor, wherein each control circuit has an input and an output, wherein the output of the first control circuit to the control electrode of the first main transistor and the output of the second control circuit to the control electrode the second main transistor is coupled, wherein the input of the first control circuit to the first secondary winding and the input of the second control circuit is coupled to the second secondary winding, each control circuit having a timing whose time constant varies in response to the voltage applied to the input of the respective control circuit, each timing circuit having at least a first auxiliary transistor, the working electrode of the first auxiliary transistor is coupled to the control electrode of the associated main transistor and the reference electrode of the first auxiliary transistor to a reference potential, wherein the control electrode of the first auxiliary transistor is coupled to the center of a frequency-dependent voltage divider which is coupled on the one hand to the respective secondary winding, on the other hand to the respective reference potential.

State of the art

Such a circuit arrangement is known from the EP 0 093 469 A1 , In this case, the frequency-dependent voltage divider of each time circuit comprises an ohmic resistance and a capacitor, wherein the voltage dropping across the capacitor is coupled to the control path of the first auxiliary transistor. Furthermore, Zener diodes are provided which are used as relatively accurate thresholds for generating the blanking voltage for the discharge lamp, ie the voltage available across the lamp for ignition.

From the Scriptures WO00 / 24233 a ballast for a discharge lamp is known in which by means of a drive circuit for a half-bridge, the output voltage is limited at non-firing discharge lamp. Disadvantages of the solution according to the cited document are the considerable control losses, since accurate Z diodes with low dynamic resistance, which are required for this solution, are available only above about 7 V, and the voltage generated by a current measuring resistor in the lamp operation in this Magnitude is. A more detailed consideration of the above solution shows that a reduction of the ohmic resistance of the frequency-dependent voltage divider must be compensated by an enlargement of the capacitor of the frequency-dependent voltage divider. Since the dynamic resistance of a zener diode with a lower zener diode voltage, which would be necessary for a reduction in the voltage at the secondary winding to reduce the control losses, increases, this results in a larger time constant. The delay of the voltage at the control electrode of the first auxiliary transistor with respect to the current in the control electrode of the main transistor is thereby undefined. This also results in a large undesirable scattering range. A reduction of the voltage drop across the respective secondary winding to lower the control losses thus results in an increase of the tolerances.

The current-limiting effect of the lamp choke is due to a possible saturation back, whereby the main transistors of the inverter can be destroyed. It should be noted, however, that operation of the lamp choke with light saturation is desirable because this results in low losses. Exactly at the point makes an increase in tolerances then negatively noticeable, since thereby the danger the saturation of the lamp choke is created. As a result, this would result in a reduction of the control losses in a greater dimensioning of the components of the circuit arrangement and thus in higher costs.

Presentation of the invention

The present invention is therefore based on the object, the above-mentioned circuit arrangement such that a reduction of tax losses without risk of destruction of the main transistors of the inverter or without necessity, the main transistors of the inverter is more strongly dimensioned.

This object is achieved by a circuit arrangement having the features of patent claim 1.

The present invention is based on the finding that a disadvantage of the prior art is that the capacitor of the frequency-dependent voltage divider is also problematic because it acts as an energy store at the control electrode of the first auxiliary transistor and thus by its charge and discharge an undesirable delay the voltage at the control electrode of the first auxiliary transistor relative to the current in the control electrode of the main transistor is formed. On the basis of this finding, the frequency-dependent voltage divider is realized in an inventive circuit arrangement by an inductor and a resistor, wherein the voltage dropping across the ohmic resistor is coupled to the control path of the first auxiliary transistor. By this measure, the control electrode of the first auxiliary transistor is no longer undesirably coupled to an energy storage, eliminating unwanted delays. As a second measure, the Z-diodes affected by the above-mentioned disadvantages are replaced by a second Auxiliary transistor is connected in parallel with the inductance of the frequency-dependent voltage divider, wherein the second auxiliary transistor comprises a drive circuit which is designed to bridge the associated inductance in dependence on the voltage at the associated secondary winding by the second auxiliary transistor. It should be noted that transistors used for the second auxiliary transistor usually switch at a voltage of 0.6 to 0.7V on the control path, that is, at such a voltage between the control and reference electrodes, whereas the already mentioned above Z-diode voltages by a factor of 10 over.

By virtue of the configuration according to the invention, good reproducibility of the empty voltage and the operating parameters can be achieved with a few, very inexpensive standard components. H. ensure the parameter for the continuous operation of the discharge lamp, at the same time significantly reduced control losses. In a realized embodiment, the tax losses could be reduced by about 80%.

A preferred embodiment is characterized in that the second mentioned measure according to the invention, ie the measure which provides a second auxiliary transistor, which is connected in parallel with the associated inductance, is provided only in one of the two time circuits. This is particularly possible in load circuits of low operating quality, in which the difference between the ignition frequency and operating frequency is low and in which the lamp inductor is operated only slightly saturated when ignited.

In a preferred embodiment, the at least one second auxiliary transistor comprises a control electrode, a working electrode and a reference electrode, wherein the working electrode is coupled to the point of the associated voltage divider, at which the inductance is coupled to the ohmic resistance, wherein the reference electrode with the associated second Secondary winding is coupled. By this interconnection is ensured in a simple manner that the inductance of the frequency-dependent voltage divider can be bypassed by the second auxiliary transistor, provided that the second auxiliary transistor is turned on.

Furthermore, it is preferred that the at least one timing circuit further comprises a current measuring resistor which is serially coupled between the associated secondary winding and the output of the associated timing circuit, wherein the voltage dropping across the current sensing resistor is coupled to the control electrode of the associated second auxiliary transistor. As a result, the voltage which switches the second auxiliary transistor on and off is made dependent on the current in the control electrode of the respective main transistor. This makes it possible to achieve that a bridging of the inductance of the frequency-dependent voltage divider is very closely linked to the time profile of the current in the control electrode of the respective main transistor, which in turn is an image of the load circuit current due to the design of the transformer as a current transformer. Undesirable time tolerances as in the prior art, which could cause accidental saturation of the lamp inductor are thus reliably excluded.

Preferably, it is further provided that between the working electrode of the at least one second auxiliary transistor and the point of the associated voltage divider, at which the inductance is coupled to the ohmic resistance, a first further ohmic resistance is coupled. An ohmic resistor provided at this point acts as a current limiting resistor and thus ensures that the current driven by the transformer continues to flow essentially through the current measuring resistor and thus keeps the second auxiliary transistor safely open.

Preferably, it is further provided that between the point at which the inductance of the respective voltage divider is coupled to the respective secondary winding, and the respective inductance, a capacitor is coupled. By this measure, a saturation of the inductance of the frequency-dependent voltage divider is reliably prevented for the case in which the voltage fed by the associated secondary winding into the control circuit voltage has a DC component. It is important to ensure that the capacitor is chosen large enough, so that the fixed by the ohmic resistance and the inductance of the frequency-dependent voltage divider time constant is not changed.

Finally, it is further preferred that a second further ohmic resistance is coupled between the current measuring resistor and the output of the associated timing circuit. By this measure, sufficient voltage drops again at both resistors in the lamp operation, thus also at the resistance of the frequency-dependent voltage divider, the base-emitter-forward voltage of the first auxiliary transistor safely achieved and the feedback is sufficiently large.

Further advantageous embodiments will become apparent from the dependent claims.

Short description of the drawing (s)

In the following, an embodiment of a circuit arrangement according to the invention will now be described in more detail with reference to the accompanying drawing, which shows a schematic representation of an embodiment of a circuit arrangement according to the invention.

Preferred embodiment of the invention

The figure shows a circuit arrangement according to the invention and a supply arrangement for this circuit arrangement and two lamps which are ignited or fed by means of this circuit arrangement. The supply arrangement comprises two input terminals 1 and 2, which are intended for connection to an AC voltage source. To these terminals 1 and 2, a rectifier bridge 3 with four diodes (4 to 7 inclusive) is connected. Further, for example, a filter between the input terminals 1 and 2 on the one hand, and the rectifier bridge 3 on the other hand, may be provided. An output terminal of the rectifier bridge 3 is connected to a first input terminal A of the circuit arrangement. A second output terminal of the rectifier bridge 3 is connected to an input terminal B of the circuit arrangement.

This circuit will now be described. The terminals A and B are connected by a capacitor 10 and also by a series connection of a first main transistor 11, a primary winding 12 of a current transformer and a load circuit 13, the details of which are listed below, and a capacitor 14. The load circuit 13 comprises two substantially equal, parallel branches. Each of these branches comprises a discharge lamp 15 or 15 ', connected in series with a lamp choke 16 or 16'. Each of the lamps 15, 15 'has two preheatable electrodes. Belonging to a lamp 15, 15 'remote from a supply source electrode ends are connected by an output capacitor 17 and 17' to each other. Each of these output capacitors 17, 17 'therefore represents a circuit element connected in parallel with the relevant lamp 15, 15'.

The series connection of the primary winding 12 of the transformer, the load circuit 13 and the capacitor 14 is connected in parallel with a second main transistor 20. Each of the two main transistors 11 and 20 is of the NPN type. In the circuit, the collector of the main transistor 11 is connected to the positive input terminal A of the circuit arrangement. The emitter of this main transistor 11 is connected to the collector of the main transistor 20. The emitter of this main transistor 20 is connected to the negative input terminal B of the circuit arrangement. Optionally, current negative feedback resistors, in particular emitter resistors, may be provided for the main transistors 11 and 20. By the main transistors 11 and 20 in half-bridge arrangement is defines a half-bridge center HM. The current transformer having the primary winding 12 has two secondary windings 30 and 31, respectively. The secondary winding 30 is connected to a control circuit of the main transistor 11. The secondary winding 31 is connected to a control circuit of the main transistor 20. The control circuits are substantially similar to each other.

The ends of the secondary winding 30 are connected to each other via a diode 40 and a timing circuit comprising a series circuit of a capacitor 32, an inductor 33 and an ohmic resistor 34. The timing circuit further comprises a first auxiliary transistor 35 whose base is connected to the connection point between the capacitor 32 and the inductor 33 on the one hand and the ohmic resistor 34 on the other. Furthermore, a second auxiliary transistor 38 is provided, whose collector-emitter path is connected in parallel with a series resistor ohmic resistance 39 of the series circuit of capacitor 32 and inductance 33 arranged in parallel therewith. Between the base and the emitter of the second auxiliary transistor 38, an ohmic resistor 36 is connected, which serves as a current measuring resistor. A second further ohmic resistor 37 is connected in series between the ohmic resistor 36 and the base of the main transistor 11.

A corresponding timing circuit 32 'to 40' connects the ends of the secondary winding 31 with each other. A diode 50 is connected in anti-parallel to the main transistor 11. A diode 50 'is connected in anti-parallel to the main transistor 20. Parallel to the main transistor 11 is still an ohmic resistor 51 and a capacitor 52 connected.

Finally, a circuit for starting the circuit is provided. This circuit comprises inter alia a series connection of a resistor 60 and a capacitor 61, which is connected in parallel with the capacitor 10. A connection point between the resistor 60 and the capacitor 61 is connected to a bi-directional threshold element 62, in the present case a DIAC. The other side of this threshold element 62 is connected via a resistor 63 to a point between the resistor 36 'and the diode 40' of the control circuit of the main transistor 20. The node between the resistor 60 and the capacitor 61 is also connected to a diode 64. The other side of this diode 64 is connected via a resistor 65 to the collector of the main transistor 20.

The circuit described operates as follows: The terminals 1 and 2 are connected to an AC voltage of, for example, 230 V, 50 Hz. As a result, a DC voltage is applied through the rectifier bridge 3 between the terminals A and B of the circuit arrangement. Consequently, current first flows from A through resistor 51, primary winding 12 of the current transformer, load circuit 13, and capacitor 14 to terminal B, causing the output capacitors 17, 17 'and capacitor 14 to charge. In addition, the capacitor 61 is charged via the resistor 60. When the threshold voltage of the threshold element 62 is then reached, the capacitor 61 becomes, inter alia, via the resistors 63, 36 ', 37' and the base-emitter junction of the main transistor 20 discharged. This discharge process ensures that the main transistor 20 becomes conductive for the first time. As a result, the capacitor 14 in the circuit 14, 13, 12, 20, 14 is discharged. Since this discharge current also flows through the primary winding 12 of the current transformer, voltages in the two secondary windings 30 and 31 are induced. The induced voltage in the winding 31 has a sense of direction holding the main transistor 20 in a conducting state. The elements 32 ', 33', 34 'of the timing circuit turn on the first auxiliary transistor 35' after elapse of a predetermined period of time. As a result, the main transistor 20 becomes non-conductive. The current of the load circuit 13 then flows through the combination of the diode 50 and the capacitor 52 and through the capacitor 10 back to the capacitor 14. The actual value of this current decreases and near its zero crossing, the main transistor 11 through the winding 30, the diode 40 and the resistors 36 and 37 conductive. In the same way as described for the switching operation of the main transistor 20, the transistor 11 then becomes non-conductive again after a while. The circuit is now in operation. The main transistors 11 and 20 are alternately turned on. The circuit 64, 65 then ensures that the starting capacitor 61 is no longer charged to the breakdown voltage of the threshold element 62.

The lamps 15, 15 'are then not ignited. The load circuit 13 in this case comprises a parallel connection of two practically identical branches, each of which consists of a series connection of a lamp inductor 16 and an output capacitor 17 (or 16 'and 17'). This circuit is not attenuated by the lamps 15, 15 '. Without the presence of the second auxiliary transistors 38 and 38 'in the timing circuits, the frequency of the current flowing through the load circuit 13 would be set practically at the resonant frequency of that circuit. As a result, such great voltages would be applied to the lamps 15 and 15 'that they would ignite with cold cathodes. In the case of defective lamps, this could also lead to an electrically inadmissible situation in the circuit 13 due to very high currents.

However, as the currents in the primary winding 12 of the transformer increase, a current is now induced in the secondary windings 30 and 31 which results in a voltage drop across the respective current sensing resistor 36, 36 'sufficient to conduct the associated second auxiliary transistor 38, 38' turn. Thus, the time constant of the timing is influenced, in this case, by the fact that the series circuit of capacitor 32 and inductor 33 and 32 'and 33' is bridged by the ohmic resistor 39. As a result, the voltage across the ohmic resistor 34 or 34 'more quickly reaches the value at which the auxiliary transistor 35 or 35' becomes conductive, with the result that the associated main transistor 11 or 20 becomes nonconductive more rapidly. This causes the frequency of the circuit arrangement to reach a higher value. This higher frequency leads to a higher voltage at the lamp inductor 16 or 16 'and therefore to a lower voltage at the lamp 15 or 15'. This allows the lamps to pass through their electrodes Preheat output capacitor 17 or 17 '. Consequently, there is no risk of the lamps igniting with too cold electrodes. Only when the electrodes are sufficiently preheated, the voltage present on the lamps is sufficient to ignite them. The current flowing through the load circuit and thus the primary winding 12 of the current transformer must then no longer assume a high value, since now the attenuation of the lamps 15 or 15 'is reached. This has the result that the current flowing through the windings 30 and 31 will be comparatively low, so that the switching threshold of the second auxiliary transistor 38 or 38 'is no longer reached by the voltage dropping across the current measuring resistor 36 or 36'. This means that it takes a longer time until the input of the first auxiliary transistor 35 or 35 ', a voltage applied, which turns on this transistor. This in turn has the result that the associated main transistor 11 or 20 becomes conductive at a later time. This means that the frequency at which the circuit arrangement then operates is lower than that during the ignition process of the lamps 15 or 15 '.

Claims (6)

1. Circuit arrangement for starting and operating at least one discharge lamp (15, 15') with

   - a first input terminal (A) and a second input terminal (B) for connecting a supply voltage;

   - an inverter, which comprises at least one first main transistor (11) and one second main transistor (20) in a half-bridge arrangement, which main transistors are coupled in series between the first input terminal (A) and the second input terminal (B);

   - a first output terminal and a second output terminal for connecting the at least one discharge lamp (15, 15');

   - at least one lamp inductor (16, 16'), which is coupled in series with the first output terminal;

   - at least one output capacitor (17, 17'), which is coupled in parallel with the first output terminal and the second output terminal;

   - a transformer with a primary winding (12) and a first secondary winding (30) and a second secondary winding (31), a series circuit comprising the primary winding (12) and the at least one lamp inductor (16, 16') being coupled between the half-bridge centre point (HM) and a reference potential; and

   - a first control circuit for driving the first main transistor (11) and a second control circuit for driving the second main transistor (20), each control circuit having an input and an output, the output of the first control circuit being coupled to the control electrode of the first main transistor (11), and the output of the second control circuit being coupled to the control electrode of the second main transistor (20), with the input of the first control circuit being coupled to the first secondary winding (30) and the input of the second control circuit being coupled to the second secondary winding (31), each control circuit having a timing circuit (32 to 40; 32' to 40'), whose time constant varies as a function of the voltage across the input of the respective control circuit, each timing circuit (32 to 40; 32' to 40') having at least one first auxiliary transistor (35; 35'), the working electrode of the first auxiliary transistor (35; 35') being coupled to the control electrode of the associated main transistor (11; 20) and the reference electrode of the first auxiliary transistor (35; 35') being coupled to a reference potential, the control electrode of the first auxiliary transistor (35; 35') being coupled to the centre point of a frequency-dependent voltage divider, which is coupled firstly to the respective secondary winding (30; 31) and secondly to the respective reference potential; characterized in that the frequency-dependent voltage divider of each timing circuit (32 to 40; 32' to 40') comprises at least one inductance (33; 33') and a nonreactive resistor (34; 34'), the voltage drop across the nonreactive resistor (34; 34') being coupled to the control path of the first auxiliary transistor (35; 35'); at least one timing circuit (32 to 40; 32' to 40') comprising a second auxiliary transistor (38; 38'), which is connected in parallel with the associated inductance (33; 33'), the second auxiliary transistor (38; 38') comprising a drive circuit, which is designed to bridge the associated inductance (33; 33') as a function of the voltage across the associated secondary winding (30; 31) by virtue of the second auxiliary transistor (38; 38').
2. Circuit arrangement according to Claim 1, characterized in that the at least one second auxiliary transistor (38; 38') has a control electrode, a working electrode and a reference electrode, the working electrode being coupled to that point of the associated voltage divider at which the inductance (33; 33') is coupled to the nonreactive resistor (34; 34'), the reference electrode being coupled to the associated second secondary winding (30; 31).
3. Circuit arrangement according to either of Claims 1 and 2, characterized in that the at least one timing circuit (32 to 40; 32' to 40') furthermore comprises a current-measuring resistor, which is coupled in series between the associated secondary winding (30; 31) and the output of the associated timing circuit (32 to 40; 32' to 40'), the voltage drop across the current-measuring resistor (36; 36') being coupled to the control electrode of the associated second auxiliary transistor (38; 38').
4. Circuit arrangement according to one of the preceding claims, characterized in that a first further nonreactive resistor (39; 39') is coupled between the working electrode of the at least one second auxiliary transistor (38; 38') and that point of the associated voltage divider at which the inductance (33; 33') is coupled to the nonreactive resistor (34; 34').
5. Circuit arrangement according to one of the preceding claims, characterized in that a capacitor (32; 32') is coupled between the point at which the inductance (33; 33') of the respective frequency-dependent voltage divider is coupled to the respective secondary winding (30; 31) and the respective inductance (33; 33').
6. Circuit arrangement according to one of the preceding claims, characterized in that a second further nonreactive resistor (37; 37') is coupled between the current-measuring resistor (36; 36') and the output of the associated timing circuit (32 to 40; 32' to 40').

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